X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fmtd%2Fmaps%2Fdc21285.c;h=b32bb9347d713045bf9db02cdc08470e70b3165f;hb=refs%2Fheads%2Fvserver;hp=8230cc5cd78059bcb52c5691dc69570a53075fa4;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git diff --git a/drivers/mtd/maps/dc21285.c b/drivers/mtd/maps/dc21285.c index 8230cc5cd..b32bb9347 100644 --- a/drivers/mtd/maps/dc21285.c +++ b/drivers/mtd/maps/dc21285.c @@ -4,14 +4,15 @@ * (C) 2000 Nicolas Pitre * * This code is GPL - * - * $Id: dc21285.c,v 1.15 2003/05/21 12:45:18 dwmw2 Exp $ + * + * $Id: dc21285.c,v 1.24 2005/11/07 11:14:26 gleixner Exp $ */ -#include #include #include #include #include +#include +#include #include #include @@ -19,176 +20,231 @@ #include #include +#include + + +static struct mtd_info *dc21285_mtd; + +#ifdef CONFIG_ARCH_NETWINDER +/* + * This is really ugly, but it seams to be the only + * realiable way to do it, as the cpld state machine + * is unpredictible. So we have a 25us penalty per + * write access. + */ +static void nw_en_write(void) +{ + extern spinlock_t gpio_lock; + unsigned long flags; + /* + * we want to write a bit pattern XXX1 to Xilinx to enable + * the write gate, which will be open for about the next 2ms. + */ + spin_lock_irqsave(&gpio_lock, flags); + cpld_modify(1, 1); + spin_unlock_irqrestore(&gpio_lock, flags); -static struct mtd_info *mymtd; + /* + * let the ISA bus to catch on... + */ + udelay(25); +} +#else +#define nw_en_write() do { } while (0) +#endif -__u8 dc21285_read8(struct map_info *map, unsigned long ofs) +static map_word dc21285_read8(struct map_info *map, unsigned long ofs) { - return *(__u8*)(map->map_priv_1 + ofs); + map_word val; + val.x[0] = *(uint8_t*)(map->virt + ofs); + return val; } -__u16 dc21285_read16(struct map_info *map, unsigned long ofs) +static map_word dc21285_read16(struct map_info *map, unsigned long ofs) { - return *(__u16*)(map->map_priv_1 + ofs); + map_word val; + val.x[0] = *(uint16_t*)(map->virt + ofs); + return val; } -__u32 dc21285_read32(struct map_info *map, unsigned long ofs) +static map_word dc21285_read32(struct map_info *map, unsigned long ofs) { - return *(__u32*)(map->map_priv_1 + ofs); + map_word val; + val.x[0] = *(uint32_t*)(map->virt + ofs); + return val; } -void dc21285_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) +static void dc21285_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) { - memcpy(to, (void*)(map->map_priv_1 + from), len); + memcpy(to, (void*)(map->virt + from), len); } -void dc21285_write8(struct map_info *map, __u8 d, unsigned long adr) +static void dc21285_write8(struct map_info *map, const map_word d, unsigned long adr) { + if (machine_is_netwinder()) + nw_en_write(); *CSR_ROMWRITEREG = adr & 3; adr &= ~3; - *(__u8*)(map->map_priv_1 + adr) = d; + *(uint8_t*)(map->virt + adr) = d.x[0]; } -void dc21285_write16(struct map_info *map, __u16 d, unsigned long adr) +static void dc21285_write16(struct map_info *map, const map_word d, unsigned long adr) { + if (machine_is_netwinder()) + nw_en_write(); *CSR_ROMWRITEREG = adr & 3; adr &= ~3; - *(__u16*)(map->map_priv_1 + adr) = d; + *(uint16_t*)(map->virt + adr) = d.x[0]; } -void dc21285_write32(struct map_info *map, __u32 d, unsigned long adr) +static void dc21285_write32(struct map_info *map, const map_word d, unsigned long adr) { - *(__u32*)(map->map_priv_1 + adr) = d; + if (machine_is_netwinder()) + nw_en_write(); + *(uint32_t*)(map->virt + adr) = d.x[0]; } -void dc21285_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len) +static void dc21285_copy_to_32(struct map_info *map, unsigned long to, const void *from, ssize_t len) { - switch (map->buswidth) { - case 4: - while (len > 0) { - __u32 d = *((__u32*)from)++; - dc21285_write32(map, d, to); - to += 4; - len -= 4; - } - break; - case 2: - while (len > 0) { - __u16 d = *((__u16*)from)++; - dc21285_write16(map, d, to); - to += 2; - len -= 2; - } - break; - case 1: - while (len > 0) { - __u8 d = *((__u8*)from)++; - dc21285_write8(map, d, to); - to++; - len--; - } - break; + while (len > 0) { + map_word d; + d.x[0] = *((uint32_t*)from); + dc21285_write32(map, d, to); + from += 4; + to += 4; + len -= 4; + } +} + +static void dc21285_copy_to_16(struct map_info *map, unsigned long to, const void *from, ssize_t len) +{ + while (len > 0) { + map_word d; + d.x[0] = *((uint16_t*)from); + dc21285_write16(map, d, to); + from += 2; + to += 2; + len -= 2; } } -struct map_info dc21285_map = { +static void dc21285_copy_to_8(struct map_info *map, unsigned long to, const void *from, ssize_t len) +{ + map_word d; + d.x[0] = *((uint8_t*)from); + dc21285_write8(map, d, to); + from++; + to++; + len--; +} + +static struct map_info dc21285_map = { .name = "DC21285 flash", .phys = NO_XIP, .size = 16*1024*1024, - .read8 = dc21285_read8, - .read16 = dc21285_read16, - .read32 = dc21285_read32, .copy_from = dc21285_copy_from, - .write8 = dc21285_write8, - .write16 = dc21285_write16, - .write32 = dc21285_write32, - .copy_to = dc21285_copy_to }; /* Partition stuff */ -static struct mtd_partition *dc21285_parts; #ifdef CONFIG_MTD_PARTITIONS +static struct mtd_partition *dc21285_parts; static const char *probes[] = { "RedBoot", "cmdlinepart", NULL }; #endif - -int __init init_dc21285(void) + +static int __init init_dc21285(void) { - /* - * Flash timing is determined with bits 19-16 of the - * CSR_SA110_CNTL. The value is the number of wait cycles, or - * 0 for 16 cycles (the default). Cycles are 20 ns. - * Here we use 7 for 140 ns flash chips. - */ - /* access time */ - *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x000f0000) | (7 << 16)); - /* burst time */ - *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x00f00000) | (7 << 20)); - /* tristate time */ - *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x0f000000) | (7 << 24)); - - /* Determine buswidth */ +#ifdef CONFIG_MTD_PARTITIONS + int nrparts; +#endif + + /* Determine bankwidth */ switch (*CSR_SA110_CNTL & (3<<14)) { - case SA110_CNTL_ROMWIDTH_8: - dc21285_map.buswidth = 1; + case SA110_CNTL_ROMWIDTH_8: + dc21285_map.bankwidth = 1; + dc21285_map.read = dc21285_read8; + dc21285_map.write = dc21285_write8; + dc21285_map.copy_to = dc21285_copy_to_8; break; - case SA110_CNTL_ROMWIDTH_16: - dc21285_map.buswidth = 2; + case SA110_CNTL_ROMWIDTH_16: + dc21285_map.bankwidth = 2; + dc21285_map.read = dc21285_read16; + dc21285_map.write = dc21285_write16; + dc21285_map.copy_to = dc21285_copy_to_16; break; - case SA110_CNTL_ROMWIDTH_32: - dc21285_map.buswidth = 4; + case SA110_CNTL_ROMWIDTH_32: + dc21285_map.bankwidth = 4; + dc21285_map.read = dc21285_read32; + dc21285_map.write = dc21285_write32; + dc21285_map.copy_to = dc21285_copy_to_32; break; default: - printk (KERN_ERR "DC21285 flash: undefined buswidth\n"); + printk (KERN_ERR "DC21285 flash: undefined bankwidth\n"); return -ENXIO; } - printk (KERN_NOTICE "DC21285 flash support (%d-bit buswidth)\n", - dc21285_map.buswidth*8); + printk (KERN_NOTICE "DC21285 flash support (%d-bit bankwidth)\n", + dc21285_map.bankwidth*8); /* Let's map the flash area */ - dc21285_map.map_priv_1 = (unsigned long)ioremap(DC21285_FLASH, 16*1024*1024); - if (!dc21285_map.map_priv_1) { + dc21285_map.virt = ioremap(DC21285_FLASH, 16*1024*1024); + if (!dc21285_map.virt) { printk("Failed to ioremap\n"); return -EIO; } - mymtd = do_map_probe("cfi_probe", &dc21285_map); - if (mymtd) { - int nrparts = 0; + if (machine_is_ebsa285()) { + dc21285_mtd = do_map_probe("cfi_probe", &dc21285_map); + } else { + dc21285_mtd = do_map_probe("jedec_probe", &dc21285_map); + } + + if (!dc21285_mtd) { + iounmap(dc21285_map.virt); + return -ENXIO; + } - mymtd->owner = THIS_MODULE; - - /* partition fixup */ + dc21285_mtd->owner = THIS_MODULE; #ifdef CONFIG_MTD_PARTITIONS - nrparts = parse_mtd_partitions(mymtd, probes, &dc21285_parts, (void *)0); - if (nrparts > 0) { - add_mtd_partitions(mymtd, dc21285_parts, nrparts); - return 0; - } + nrparts = parse_mtd_partitions(dc21285_mtd, probes, &dc21285_parts, 0); + if (nrparts > 0) + add_mtd_partitions(dc21285_mtd, dc21285_parts, nrparts); + else #endif - add_mtd_device(mymtd); - return 0; + add_mtd_device(dc21285_mtd); + + if(machine_is_ebsa285()) { + /* + * Flash timing is determined with bits 19-16 of the + * CSR_SA110_CNTL. The value is the number of wait cycles, or + * 0 for 16 cycles (the default). Cycles are 20 ns. + * Here we use 7 for 140 ns flash chips. + */ + /* access time */ + *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x000f0000) | (7 << 16)); + /* burst time */ + *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x00f00000) | (7 << 20)); + /* tristate time */ + *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x0f000000) | (7 << 24)); } - iounmap((void *)dc21285_map.map_priv_1); - return -ENXIO; + return 0; } static void __exit cleanup_dc21285(void) { #ifdef CONFIG_MTD_PARTITIONS if (dc21285_parts) { - del_mtd_partitions(mymtd); + del_mtd_partitions(dc21285_mtd); kfree(dc21285_parts); } else #endif - del_mtd_device(mymtd); + del_mtd_device(dc21285_mtd); - map_destroy(mymtd); - iounmap((void *)dc21285_map.map_priv_1); + map_destroy(dc21285_mtd); + iounmap(dc21285_map.virt); } module_init(init_dc21285);