X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fmtd%2Fnand%2Fnandsim.c;fp=drivers%2Fmtd%2Fnand%2Fnandsim.c;h=a0af92cc7efd787624f6848d93d618eca898ce84;hb=64ba3f394c830ec48a1c31b53dcae312c56f1604;hp=545ff252d81eb675dfa7c5bf349b212461ee8240;hpb=be1e6109ac94a859551f8e1774eb9a8469fe055c;p=linux-2.6.git diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c index 545ff252d..a0af92cc7 100644 --- a/drivers/mtd/nand/nandsim.c +++ b/drivers/mtd/nand/nandsim.c @@ -25,6 +25,7 @@ * $Id: nandsim.c,v 1.8 2005/03/19 15:33:56 dedekind Exp $ */ +#include #include #include #include @@ -368,7 +369,7 @@ init_nandsim(struct mtd_info *mtd) /* Initialize the NAND flash parameters */ ns->busw = chip->options & NAND_BUSWIDTH_16 ? 16 : 8; ns->geom.totsz = mtd->size; - ns->geom.pgsz = mtd->writesize; + ns->geom.pgsz = mtd->oobblock; ns->geom.oobsz = mtd->oobsize; ns->geom.secsz = mtd->erasesize; ns->geom.pgszoob = ns->geom.pgsz + ns->geom.oobsz; @@ -1070,6 +1071,68 @@ switch_state(struct nandsim *ns) } } +static void +ns_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv; + + switch (cmd) { + + /* set CLE line high */ + case NAND_CTL_SETCLE: + NS_DBG("ns_hwcontrol: start command latch cycles\n"); + ns->lines.cle = 1; + break; + + /* set CLE line low */ + case NAND_CTL_CLRCLE: + NS_DBG("ns_hwcontrol: stop command latch cycles\n"); + ns->lines.cle = 0; + break; + + /* set ALE line high */ + case NAND_CTL_SETALE: + NS_DBG("ns_hwcontrol: start address latch cycles\n"); + ns->lines.ale = 1; + break; + + /* set ALE line low */ + case NAND_CTL_CLRALE: + NS_DBG("ns_hwcontrol: stop address latch cycles\n"); + ns->lines.ale = 0; + break; + + /* set WP line high */ + case NAND_CTL_SETWP: + NS_DBG("ns_hwcontrol: enable write protection\n"); + ns->lines.wp = 1; + break; + + /* set WP line low */ + case NAND_CTL_CLRWP: + NS_DBG("ns_hwcontrol: disable write protection\n"); + ns->lines.wp = 0; + break; + + /* set CE line low */ + case NAND_CTL_SETNCE: + NS_DBG("ns_hwcontrol: enable chip\n"); + ns->lines.ce = 1; + break; + + /* set CE line high */ + case NAND_CTL_CLRNCE: + NS_DBG("ns_hwcontrol: disable chip\n"); + ns->lines.ce = 0; + break; + + default: + NS_ERR("hwcontrol: unknown command\n"); + } + + return; +} + static u_char ns_nand_read_byte(struct mtd_info *mtd) { @@ -1296,18 +1359,6 @@ ns_nand_write_byte(struct mtd_info *mtd, u_char byte) return; } -static void ns_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int bitmask) -{ - struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv; - - ns->lines.cle = bitmask & NAND_CLE ? 1 : 0; - ns->lines.ale = bitmask & NAND_ALE ? 1 : 0; - ns->lines.ce = bitmask & NAND_NCE ? 1 : 0; - - if (cmd != NAND_CMD_NONE) - ns_nand_write_byte(mtd, cmd); -} - static int ns_device_ready(struct mtd_info *mtd) { @@ -1325,6 +1376,17 @@ ns_nand_read_word(struct mtd_info *mtd) return chip->read_byte(mtd) | (chip->read_byte(mtd) << 8); } +static void +ns_nand_write_word(struct mtd_info *mtd, uint16_t word) +{ + struct nand_chip *chip = (struct nand_chip *)mtd->priv; + + NS_DBG("write_word\n"); + + chip->write_byte(mtd, word & 0xFF); + chip->write_byte(mtd, word >> 8); +} + static void ns_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) { @@ -1452,14 +1514,16 @@ static int __init ns_init_module(void) /* * Register simulator's callbacks. */ - chip->cmd_ctrl = ns_hwcontrol; + chip->hwcontrol = ns_hwcontrol; chip->read_byte = ns_nand_read_byte; chip->dev_ready = ns_device_ready; + chip->write_byte = ns_nand_write_byte; chip->write_buf = ns_nand_write_buf; chip->read_buf = ns_nand_read_buf; chip->verify_buf = ns_nand_verify_buf; + chip->write_word = ns_nand_write_word; chip->read_word = ns_nand_read_word; - chip->ecc.mode = NAND_ECC_SOFT; + chip->eccmode = NAND_ECC_SOFT; chip->options |= NAND_SKIP_BBTSCAN; /* @@ -1482,8 +1546,6 @@ static int __init ns_init_module(void) chip->options |= NAND_BUSWIDTH_16; } - nsmtd->owner = THIS_MODULE; - if ((retval = nand_scan(nsmtd, 1)) != 0) { NS_ERR("can't register NAND Simulator\n"); if (retval > 0)