X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fnet%2Fb44.h;h=4944507fad2381470d9084aad4c9b2b2ba3ebbce;hb=16c70f8c1b54b61c3b951b6fb220df250fe09b32;hp=9c9d4f8ba83f97aefee9424b8445e8bfae94d36d;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git diff --git a/drivers/net/b44.h b/drivers/net/b44.h index 9c9d4f8ba..4944507fa 100644 --- a/drivers/net/b44.h +++ b/drivers/net/b44.h @@ -24,6 +24,9 @@ #define WKUP_LEN_P3_MASK 0x7f000000 /* Pattern 3 */ #define WKUP_LEN_P3_SHIFT 24 #define WKUP_LEN_D3 0x80000000 +#define WKUP_LEN_DISABLE 0x80808080 +#define WKUP_LEN_ENABLE_TWO 0x80800000 +#define WKUP_LEN_ENABLE_THREE 0x80000000 #define B44_ISTAT 0x0020UL /* Interrupt Status */ #define ISTAT_LS 0x00000020 /* Link Change (B0 only) */ #define ISTAT_PME 0x00000040 /* Power Management Event */ @@ -223,21 +226,8 @@ #define B44_RX_SYM 0x05D0UL /* MIB RX Symbol Errors */ #define B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */ #define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */ -#define B44_SBIPSFLAG 0x0F08UL /* SB Initiator Port OCP Slave Flag */ -#define SBIPSFLAG_IMASK1 0x0000003f /* Which sbflags --> mips interrupt 1 */ -#define SBIPSFLAG_ISHIFT1 0 -#define SBIPSFLAG_IMASK2 0x00003f00 /* Which sbflags --> mips interrupt 2 */ -#define SBIPSFLAG_ISHIFT2 8 -#define SBIPSFLAG_IMASK3 0x003f0000 /* Which sbflags --> mips interrupt 3 */ -#define SBIPSFLAG_ISHIFT3 16 -#define SBIPSFLAG_IMASK4 0x3f000000 /* Which sbflags --> mips interrupt 4 */ -#define SBIPSFLAG_ISHIFT4 24 -#define B44_SBTPSFLAG 0x0F18UL /* SB Target Port OCP Slave Flag */ -#define SBTPS_NUM0_MASK 0x0000003f -#define SBTPS_F0EN0 0x00000040 -#define B44_SBADMATCH3 0x0F60UL /* SB Address Match 3 */ -#define B44_SBADMATCH2 0x0F68UL /* SB Address Match 2 */ -#define B44_SBADMATCH1 0x0F70UL /* SB Address Match 1 */ + +/* Silicon backplane register definitions */ #define B44_SBIMSTATE 0x0F90UL /* SB Initiator Agent State */ #define SBIMSTATE_PC 0x0000000f /* Pipe Count */ #define SBIMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */ @@ -269,86 +259,6 @@ #define SBTMSHIGH_GCR 0x20000000 /* Gated Clock Request */ #define SBTMSHIGH_BISTF 0x40000000 /* BIST Failed */ #define SBTMSHIGH_BISTD 0x80000000 /* BIST Done */ -#define B44_SBBWA0 0x0FA0UL /* SB Bandwidth Allocation Table 0 */ -#define SBBWA0_TAB0_MASK 0x0000ffff /* Lookup Table 0 */ -#define SBBWA0_TAB0_SHIFT 0 -#define SBBWA0_TAB1_MASK 0xffff0000 /* Lookup Table 0 */ -#define SBBWA0_TAB1_SHIFT 16 -#define B44_SBIMCFGLOW 0x0FA8UL /* SB Initiator Configuration Low */ -#define SBIMCFGLOW_STO_MASK 0x00000003 /* Service Timeout */ -#define SBIMCFGLOW_RTO_MASK 0x00000030 /* Request Timeout */ -#define SBIMCFGLOW_RTO_SHIFT 4 -#define SBIMCFGLOW_CID_MASK 0x00ff0000 /* Connection ID */ -#define SBIMCFGLOW_CID_SHIFT 16 -#define B44_SBIMCFGHIGH 0x0FACUL /* SB Initiator Configuration High */ -#define SBIMCFGHIGH_IEM_MASK 0x0000000c /* Inband Error Mode */ -#define SBIMCFGHIGH_TEM_MASK 0x00000030 /* Timeout Error Mode */ -#define SBIMCFGHIGH_TEM_SHIFT 4 -#define SBIMCFGHIGH_BEM_MASK 0x000000c0 /* Bus Error Mode */ -#define SBIMCFGHIGH_BEM_SHIFT 6 -#define B44_SBADMATCH0 0x0FB0UL /* SB Address Match 0 */ -#define SBADMATCH0_TYPE_MASK 0x00000003 /* Address Type */ -#define SBADMATCH0_AD64 0x00000004 /* Reserved */ -#define SBADMATCH0_AI0_MASK 0x000000f8 /* Type0 Size */ -#define SBADMATCH0_AI0_SHIFT 3 -#define SBADMATCH0_AI1_MASK 0x000001f8 /* Type1 Size */ -#define SBADMATCH0_AI1_SHIFT 3 -#define SBADMATCH0_AI2_MASK 0x000001f8 /* Type2 Size */ -#define SBADMATCH0_AI2_SHIFT 3 -#define SBADMATCH0_ADEN 0x00000400 /* Enable */ -#define SBADMATCH0_ADNEG 0x00000800 /* Negative Decode */ -#define SBADMATCH0_BS0_MASK 0xffffff00 /* Type0 Base Address */ -#define SBADMATCH0_BS0_SHIFT 8 -#define SBADMATCH0_BS1_MASK 0xfffff000 /* Type1 Base Address */ -#define SBADMATCH0_BS1_SHIFT 12 -#define SBADMATCH0_BS2_MASK 0xffff0000 /* Type2 Base Address */ -#define SBADMATCH0_BS2_SHIFT 16 -#define B44_SBTMCFGLOW 0x0FB8UL /* SB Target Configuration Low */ -#define SBTMCFGLOW_CD_MASK 0x000000ff /* Clock Divide Mask */ -#define SBTMCFGLOW_CO_MASK 0x0000f800 /* Clock Offset Mask */ -#define SBTMCFGLOW_CO_SHIFT 11 -#define SBTMCFGLOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */ -#define SBTMCFGLOW_IF_SHIFT 18 -#define SBTMCFGLOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */ -#define SBTMCFGLOW_IM_SHIFT 24 -#define B44_SBTMCFGHIGH 0x0FBCUL /* SB Target Configuration High */ -#define SBTMCFGHIGH_BM_MASK 0x00000003 /* Busy Mode */ -#define SBTMCFGHIGH_RM_MASK 0x0000000C /* Retry Mode */ -#define SBTMCFGHIGH_RM_SHIFT 2 -#define SBTMCFGHIGH_SM_MASK 0x00000030 /* Stop Mode */ -#define SBTMCFGHIGH_SM_SHIFT 4 -#define SBTMCFGHIGH_EM_MASK 0x00000300 /* Error Mode */ -#define SBTMCFGHIGH_EM_SHIFT 8 -#define SBTMCFGHIGH_IM_MASK 0x00000c00 /* Interrupt Mode */ -#define SBTMCFGHIGH_IM_SHIFT 10 -#define B44_SBBCFG 0x0FC0UL /* SB Broadcast Configuration */ -#define SBBCFG_LAT_MASK 0x00000003 /* SB Latency */ -#define SBBCFG_MAX0_MASK 0x000f0000 /* MAX Counter 0 */ -#define SBBCFG_MAX0_SHIFT 16 -#define SBBCFG_MAX1_MASK 0x00f00000 /* MAX Counter 1 */ -#define SBBCFG_MAX1_SHIFT 20 -#define B44_SBBSTATE 0x0FC8UL /* SB Broadcast State */ -#define SBBSTATE_SRD 0x00000001 /* ST Reg Disable */ -#define SBBSTATE_HRD 0x00000002 /* Hold Reg Disable */ -#define B44_SBACTCNFG 0x0FD8UL /* SB Activate Configuration */ -#define B44_SBFLAGST 0x0FE8UL /* SB Current SBFLAGS */ -#define B44_SBIDLOW 0x0FF8UL /* SB Identification Low */ -#define SBIDLOW_CS_MASK 0x00000003 /* Config Space Mask */ -#define SBIDLOW_AR_MASK 0x00000038 /* Num Address Ranges Supported */ -#define SBIDLOW_AR_SHIFT 3 -#define SBIDLOW_SYNCH 0x00000040 /* Sync */ -#define SBIDLOW_INIT 0x00000080 /* Initiator */ -#define SBIDLOW_MINLAT_MASK 0x00000f00 /* Minimum Backplane Latency */ -#define SBIDLOW_MINLAT_SHIFT 8 -#define SBIDLOW_MAXLAT_MASK 0x0000f000 /* Maximum Backplane Latency */ -#define SBIDLOW_MAXLAT_SHIFT 12 -#define SBIDLOW_FIRST 0x00010000 /* This Initiator is First */ -#define SBIDLOW_CW_MASK 0x000c0000 /* Cycle Counter Width */ -#define SBIDLOW_CW_SHIFT 18 -#define SBIDLOW_TP_MASK 0x00f00000 /* Target Ports */ -#define SBIDLOW_TP_SHIFT 20 -#define SBIDLOW_IP_MASK 0x0f000000 /* Initiator Ports */ -#define SBIDLOW_IP_SHIFT 24 #define B44_SBIDHIGH 0x0FFCUL /* SB Identification High */ #define SBIDHIGH_RC_MASK 0x0000000f /* Revision Code */ #define SBIDHIGH_CC_MASK 0x0000fff0 /* Core Code */ @@ -356,23 +266,15 @@ #define SBIDHIGH_VC_MASK 0xffff0000 /* Vendor Code */ #define SBIDHIGH_VC_SHIFT 16 -#define CORE_CODE_ILINE20 0x801 -#define CORE_CODE_SDRAM 0x803 -#define CORE_CODE_PCI 0x804 -#define CORE_CODE_MIPS 0x805 -#define CORE_CODE_ENET 0x806 -#define CORE_CODE_CODEC 0x807 -#define CORE_CODE_USB 0x808 -#define CORE_CODE_ILINE100 0x80a -#define CORE_CODE_EXTIF 0x811 - /* SSB PCI config space registers. */ +#define SSB_PMCSR 0x44 +#define SSB_PE 0x100 #define SSB_BAR0_WIN 0x80 #define SSB_BAR1_WIN 0x84 #define SSB_SPROM_CONTROL 0x88 #define SSB_BAR1_CONTROL 0x8c -/* SSB core and hsot control registers. */ +/* SSB core and host control registers. */ #define SSB_CONTROL 0x0000UL #define SSB_ARBCONTROL 0x0010UL #define SSB_ISTAT 0x0020UL @@ -395,9 +297,6 @@ #define SSB_PCI_MASK1 0xfc000000 #define SSB_PCI_MASK2 0xc0000000 -#define br32(REG) readl(bp->regs + (REG)) -#define bw32(REG,VAL) writel((VAL), bp->regs + (REG)) - /* 4400 PHY registers */ #define B44_MII_AUXCTRL 24 /* Auxiliary Control */ #define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */ @@ -408,20 +307,6 @@ #define B44_MII_TLEDCTRL 27 /* Traffic Meter LED */ #define MII_TLEDCTRL_ENABLE 0x0040 -/* XXX Add this to mii.h */ -#ifndef ADVERTISE_PAUSE -#define ADVERTISE_PAUSE_CAP 0x0400 -#endif -#ifndef ADVERTISE_PAUSE_ASYM -#define ADVERTISE_PAUSE_ASYM 0x0800 -#endif -#ifndef LPA_PAUSE -#define LPA_PAUSE_CAP 0x0400 -#endif -#ifndef LPA_PAUSE_ASYM -#define LPA_PAUSE_ASYM 0x0800 -#endif - struct dma_desc { u32 ctrl; u32 addr; @@ -466,29 +351,63 @@ struct ring_info { #define B44_MCAST_TABLE_SIZE 32 +#define B44_STAT_REG_DECLARE \ + _B44(tx_good_octets) \ + _B44(tx_good_pkts) \ + _B44(tx_octets) \ + _B44(tx_pkts) \ + _B44(tx_broadcast_pkts) \ + _B44(tx_multicast_pkts) \ + _B44(tx_len_64) \ + _B44(tx_len_65_to_127) \ + _B44(tx_len_128_to_255) \ + _B44(tx_len_256_to_511) \ + _B44(tx_len_512_to_1023) \ + _B44(tx_len_1024_to_max) \ + _B44(tx_jabber_pkts) \ + _B44(tx_oversize_pkts) \ + _B44(tx_fragment_pkts) \ + _B44(tx_underruns) \ + _B44(tx_total_cols) \ + _B44(tx_single_cols) \ + _B44(tx_multiple_cols) \ + _B44(tx_excessive_cols) \ + _B44(tx_late_cols) \ + _B44(tx_defered) \ + _B44(tx_carrier_lost) \ + _B44(tx_pause_pkts) \ + _B44(rx_good_octets) \ + _B44(rx_good_pkts) \ + _B44(rx_octets) \ + _B44(rx_pkts) \ + _B44(rx_broadcast_pkts) \ + _B44(rx_multicast_pkts) \ + _B44(rx_len_64) \ + _B44(rx_len_65_to_127) \ + _B44(rx_len_128_to_255) \ + _B44(rx_len_256_to_511) \ + _B44(rx_len_512_to_1023) \ + _B44(rx_len_1024_to_max) \ + _B44(rx_jabber_pkts) \ + _B44(rx_oversize_pkts) \ + _B44(rx_fragment_pkts) \ + _B44(rx_missed_pkts) \ + _B44(rx_crc_align_errs) \ + _B44(rx_undersize) \ + _B44(rx_crc_errs) \ + _B44(rx_align_errs) \ + _B44(rx_symbol_errs) \ + _B44(rx_pause_pkts) \ + _B44(rx_nonpause_pkts) + /* SW copy of device statistics, kept up to date by periodic timer - * which probes HW values. Must have same relative layout as HW - * register above, because b44_stats_update depends upon this. + * which probes HW values. Check b44_stats_update if you mess with + * the layout */ struct b44_hw_stats { - u32 tx_good_octets, tx_good_pkts, tx_octets; - u32 tx_pkts, tx_broadcast_pkts, tx_multicast_pkts; - u32 tx_len_64, tx_len_65_to_127, tx_len_128_to_255; - u32 tx_len_256_to_511, tx_len_512_to_1023, tx_len_1024_to_max; - u32 tx_jabber_pkts, tx_oversize_pkts, tx_fragment_pkts; - u32 tx_underruns, tx_total_cols, tx_single_cols; - u32 tx_multiple_cols, tx_excessive_cols, tx_late_cols; - u32 tx_defered, tx_carrier_lost, tx_pause_pkts; - u32 __pad1[8]; - - u32 rx_good_octets, rx_good_pkts, rx_octets; - u32 rx_pkts, rx_broadcast_pkts, rx_multicast_pkts; - u32 rx_len_64, rx_len_65_to_127, rx_len_128_to_255; - u32 rx_len_256_to_511, rx_len_512_to_1023, rx_len_1024_to_max; - u32 rx_jabber_pkts, rx_oversize_pkts, rx_fragment_pkts; - u32 rx_missed_pkts, rx_crc_align_errs, rx_undersize; - u32 rx_crc_errs, rx_align_errs, rx_symbol_errs; - u32 rx_pause_pkts, rx_nonpause_pkts; +#define _B44(x) u32 x; +B44_STAT_REG_DECLARE +#undef _B44 }; struct b44 { @@ -506,7 +425,7 @@ struct b44 { u32 dma_offset; u32 flags; -#define B44_FLAG_INIT_COMPLETE 0x00000001 +#define B44_FLAG_B0_ANDLATER 0x00000001 #define B44_FLAG_BUGGY_TXPTR 0x00000002 #define B44_FLAG_REORDER_BUG 0x00000004 #define B44_FLAG_PAUSE_AUTO 0x00008000 @@ -520,6 +439,9 @@ struct b44 { #define B44_FLAG_ADV_100HALF 0x04000000 #define B44_FLAG_ADV_100FULL 0x08000000 #define B44_FLAG_INTERNAL_PHY 0x10000000 +#define B44_FLAG_RX_RING_HACK 0x20000000 +#define B44_FLAG_TX_RING_HACK 0x40000000 +#define B44_FLAG_WOL_ENABLE 0x80000000 u32 rx_offset; @@ -530,7 +452,7 @@ struct b44 { struct net_device_stats stats; struct b44_hw_stats hw_stats; - unsigned long regs; + void __iomem *regs; struct pci_dev *pdev; struct net_device *dev; @@ -538,10 +460,10 @@ struct b44 { u32 rx_pending; u32 tx_pending; - u32 pci_cfg_state[64 / sizeof(u32)]; u8 phy_addr; - u8 mdc_port; u8 core_unit; + + struct mii_if_info mii_if; }; #endif /* _B44_H */