X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnx2.c;fp=drivers%2Fnet%2Fbnx2.c;h=ee7b75b976b5c60a41dc0ba3e76651cba42b113c;hb=97bf2856c6014879bd04983a3e9dfcdac1e7fe85;hp=a24200d0a616d8285e3f597d9addd6803ffd1552;hpb=76828883507a47dae78837ab5dec5a5b4513c667;p=linux-2.6.git diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index a24200d0a..ee7b75b97 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c @@ -9,20 +9,63 @@ * Written by: Michael Chan (mchan@broadcom.com) */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef NETIF_F_HW_VLAN_TX +#include +#define BCM_VLAN 1 +#endif +#ifdef NETIF_F_TSO +#include +#include +#include +#define BCM_TSO 1 +#endif +#include +#include +#include +#include +#include + #include "bnx2.h" #include "bnx2_fw.h" +#include "bnx2_fw2.h" #define DRV_MODULE_NAME "bnx2" #define PFX DRV_MODULE_NAME ": " -#define DRV_MODULE_VERSION "1.4.31" -#define DRV_MODULE_RELDATE "January 19, 2006" +#define DRV_MODULE_VERSION "1.5.5" +#define DRV_MODULE_RELDATE "February 1, 2007" #define RUN_AT(x) (jiffies + (x)) /* Time in jiffies before concluding the transmitter is hung. */ #define TX_TIMEOUT (5*HZ) -static char version[] __devinitdata = +static const char version[] __devinitdata = "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; MODULE_AUTHOR("Michael Chan "); @@ -43,10 +86,11 @@ typedef enum { NC370F, BCM5708, BCM5708S, + BCM5709, } board_t; /* indexed by board_t, above */ -static struct { +static const struct { char *name; } board_info[] __devinitdata = { { "Broadcom NetXtreme II BCM5706 1000Base-T" }, @@ -56,6 +100,7 @@ static struct { { "HP NC370F Multifunction Gigabit Server Adapter" }, { "Broadcom NetXtreme II BCM5708 1000Base-T" }, { "Broadcom NetXtreme II BCM5708 1000Base-SX" }, + { "Broadcom NetXtreme II BCM5709 1000Base-T" }, }; static struct pci_device_id bnx2_pci_tbl[] = { @@ -73,6 +118,8 @@ static struct pci_device_id bnx2_pci_tbl[] = { PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S }, { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S }, + { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 }, { 0, } }; @@ -106,7 +153,7 @@ static struct flash_spec flash_table[] = SAIFUN_FLASH_BYTE_ADDR_MASK, 0, "Entry 0100"}, /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ - {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, + {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, @@ -167,10 +214,19 @@ MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); static inline u32 bnx2_tx_avail(struct bnx2 *bp) { - u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons); + u32 diff; + + smp_mb(); - if (diff > MAX_TX_DESC_CNT) - diff = (diff & MAX_TX_DESC_CNT) - 1; + /* The ring uses 256 indices for 255 entries, one of them + * needs to be skipped. + */ + diff = bp->tx_prod - bp->tx_cons; + if (unlikely(diff >= TX_DESC_CNT)) { + diff &= 0xffff; + if (diff == TX_DESC_CNT) + diff = MAX_TX_DESC_CNT; + } return (bp->tx_ring_size - diff); } @@ -192,8 +248,23 @@ static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) { offset += cid_addr; - REG_WR(bp, BNX2_CTX_DATA_ADR, offset); - REG_WR(bp, BNX2_CTX_DATA, val); + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + int i; + + REG_WR(bp, BNX2_CTX_CTX_DATA, val); + REG_WR(bp, BNX2_CTX_CTX_CTRL, + offset | BNX2_CTX_CTX_CTRL_WRITE_REQ); + for (i = 0; i < 5; i++) { + u32 val; + val = REG_RD(bp, BNX2_CTX_CTX_CTRL); + if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0) + break; + udelay(5); + } + } else { + REG_WR(bp, BNX2_CTX_DATA_ADR, offset); + REG_WR(bp, BNX2_CTX_DATA, val); + } } static int @@ -273,7 +344,7 @@ bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) BNX2_EMAC_MDIO_COMM_COMMAND_WRITE | BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT; REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); - + for (i = 0; i < 50; i++) { udelay(10); @@ -313,8 +384,6 @@ bnx2_disable_int(struct bnx2 *bp) static void bnx2_enable_int(struct bnx2 *bp) { - u32 val; - REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx); @@ -322,8 +391,7 @@ bnx2_enable_int(struct bnx2 *bp) REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx); - val = REG_RD(bp, BNX2_HC_COMMAND); - REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW); + REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); } static void @@ -360,15 +428,21 @@ bnx2_netif_start(struct bnx2 *bp) static void bnx2_free_mem(struct bnx2 *bp) { - if (bp->stats_blk) { - pci_free_consistent(bp->pdev, sizeof(struct statistics_block), - bp->stats_blk, bp->stats_blk_mapping); - bp->stats_blk = NULL; + int i; + + for (i = 0; i < bp->ctx_pages; i++) { + if (bp->ctx_blk[i]) { + pci_free_consistent(bp->pdev, BCM_PAGE_SIZE, + bp->ctx_blk[i], + bp->ctx_blk_mapping[i]); + bp->ctx_blk[i] = NULL; + } } if (bp->status_blk) { - pci_free_consistent(bp->pdev, sizeof(struct status_block), + pci_free_consistent(bp->pdev, bp->status_stats_size, bp->status_blk, bp->status_blk_mapping); bp->status_blk = NULL; + bp->stats_blk = NULL; } if (bp->tx_desc_ring) { pci_free_consistent(bp->pdev, @@ -378,25 +452,28 @@ bnx2_free_mem(struct bnx2 *bp) } kfree(bp->tx_buf_ring); bp->tx_buf_ring = NULL; - if (bp->rx_desc_ring) { - pci_free_consistent(bp->pdev, - sizeof(struct rx_bd) * RX_DESC_CNT, - bp->rx_desc_ring, bp->rx_desc_mapping); - bp->rx_desc_ring = NULL; - } - kfree(bp->rx_buf_ring); + for (i = 0; i < bp->rx_max_ring; i++) { + if (bp->rx_desc_ring[i]) + pci_free_consistent(bp->pdev, + sizeof(struct rx_bd) * RX_DESC_CNT, + bp->rx_desc_ring[i], + bp->rx_desc_mapping[i]); + bp->rx_desc_ring[i] = NULL; + } + vfree(bp->rx_buf_ring); bp->rx_buf_ring = NULL; } static int bnx2_alloc_mem(struct bnx2 *bp) { - bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT, - GFP_KERNEL); + int i, status_blk_size; + + bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT, + GFP_KERNEL); if (bp->tx_buf_ring == NULL) return -ENOMEM; - memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT); bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, sizeof(struct tx_bd) * TX_DESC_CNT, @@ -404,35 +481,53 @@ bnx2_alloc_mem(struct bnx2 *bp) if (bp->tx_desc_ring == NULL) goto alloc_mem_err; - bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT, - GFP_KERNEL); + bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT * + bp->rx_max_ring); if (bp->rx_buf_ring == NULL) goto alloc_mem_err; - memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT); - bp->rx_desc_ring = pci_alloc_consistent(bp->pdev, - sizeof(struct rx_bd) * - RX_DESC_CNT, - &bp->rx_desc_mapping); - if (bp->rx_desc_ring == NULL) - goto alloc_mem_err; + memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT * + bp->rx_max_ring); + + for (i = 0; i < bp->rx_max_ring; i++) { + bp->rx_desc_ring[i] = + pci_alloc_consistent(bp->pdev, + sizeof(struct rx_bd) * RX_DESC_CNT, + &bp->rx_desc_mapping[i]); + if (bp->rx_desc_ring[i] == NULL) + goto alloc_mem_err; + + } - bp->status_blk = pci_alloc_consistent(bp->pdev, - sizeof(struct status_block), + /* Combine status and statistics blocks into one allocation. */ + status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block)); + bp->status_stats_size = status_blk_size + + sizeof(struct statistics_block); + + bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size, &bp->status_blk_mapping); if (bp->status_blk == NULL) goto alloc_mem_err; - memset(bp->status_blk, 0, sizeof(struct status_block)); + memset(bp->status_blk, 0, bp->status_stats_size); - bp->stats_blk = pci_alloc_consistent(bp->pdev, - sizeof(struct statistics_block), - &bp->stats_blk_mapping); - if (bp->stats_blk == NULL) - goto alloc_mem_err; + bp->stats_blk = (void *) ((unsigned long) bp->status_blk + + status_blk_size); - memset(bp->stats_blk, 0, sizeof(struct statistics_block)); + bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE; + if (bp->ctx_pages == 0) + bp->ctx_pages = 1; + for (i = 0; i < bp->ctx_pages; i++) { + bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev, + BCM_PAGE_SIZE, + &bp->ctx_blk_mapping[i]); + if (bp->ctx_blk[i] == NULL) + goto alloc_mem_err; + } + } return 0; alloc_mem_err: @@ -537,7 +632,7 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp) u32 local_adv, remote_adv; bp->flow_ctrl = 0; - if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != + if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { if (bp->duplex == DUPLEX_FULL) { @@ -755,13 +850,13 @@ bnx2_set_mac_link(struct bnx2 *bp) val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | - BNX2_EMAC_MODE_25G); + BNX2_EMAC_MODE_25G_MODE); if (bp->link_up) { switch (bp->line_speed) { case SPEED_10: - if (CHIP_NUM(bp) == CHIP_NUM_5708) { - val |= BNX2_EMAC_MODE_PORT_MII_10; + if (CHIP_NUM(bp) != CHIP_NUM_5706) { + val |= BNX2_EMAC_MODE_PORT_MII_10M; break; } /* fall through */ @@ -769,7 +864,7 @@ bnx2_set_mac_link(struct bnx2 *bp) val |= BNX2_EMAC_MODE_PORT_MII; break; case SPEED_2500: - val |= BNX2_EMAC_MODE_25G; + val |= BNX2_EMAC_MODE_25G_MODE; /* fall through */ case SPEED_1000: val |= BNX2_EMAC_MODE_PORT_GMII; @@ -812,7 +907,7 @@ bnx2_set_link(struct bnx2 *bp) u32 bmsr; u8 link_up; - if (bp->loopback == MAC_LOOPBACK) { + if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) { bp->link_up = 1; return 0; } @@ -854,6 +949,7 @@ bnx2_set_link(struct bnx2 *bp) u32 bmcr; bnx2_read_phy(bp, MII_BMCR, &bmcr); + bmcr &= ~BCM5708S_BMCR_FORCE_2500; if (!(bmcr & BMCR_ANENABLE)) { bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANENABLE); @@ -940,7 +1036,21 @@ bnx2_setup_serdes_phy(struct bnx2 *bp) u32 new_bmcr; int force_link_down = 0; - if (CHIP_NUM(bp) == CHIP_NUM_5708) { + bnx2_read_phy(bp, MII_ADVERTISE, &adv); + adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); + + bnx2_read_phy(bp, MII_BMCR, &bmcr); + new_bmcr = bmcr & ~(BMCR_ANENABLE | BCM5708S_BMCR_FORCE_2500); + new_bmcr |= BMCR_SPEED1000; + if (bp->req_line_speed == SPEED_2500) { + new_bmcr |= BCM5708S_BMCR_FORCE_2500; + bnx2_read_phy(bp, BCM5708S_UP1, &up1); + if (!(up1 & BCM5708S_UP1_2G5)) { + up1 |= BCM5708S_UP1_2G5; + bnx2_write_phy(bp, BCM5708S_UP1, up1); + force_link_down = 1; + } + } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { bnx2_read_phy(bp, BCM5708S_UP1, &up1); if (up1 & BCM5708S_UP1_2G5) { up1 &= ~BCM5708S_UP1_2G5; @@ -949,12 +1059,6 @@ bnx2_setup_serdes_phy(struct bnx2 *bp) } } - bnx2_read_phy(bp, MII_ADVERTISE, &adv); - adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); - - bnx2_read_phy(bp, MII_BMCR, &bmcr); - new_bmcr = bmcr & ~BMCR_ANENABLE; - new_bmcr |= BMCR_SPEED1000; if (bp->req_duplex == DUPLEX_FULL) { adv |= ADVERTISE_1000XFULL; new_bmcr |= BMCR_FULLDPLX; @@ -975,6 +1079,7 @@ bnx2_setup_serdes_phy(struct bnx2 *bp) bp->link_up = 0; netif_carrier_off(bp->dev); bnx2_write_phy(bp, MII_BMCR, new_bmcr); + bnx2_report_link(bp); } bnx2_write_phy(bp, MII_ADVERTISE, adv); bnx2_write_phy(bp, MII_BMCR, new_bmcr); @@ -1000,30 +1105,26 @@ bnx2_setup_serdes_phy(struct bnx2 *bp) if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { /* Force a link down visible on the other side */ if (bp->link_up) { - int i; - bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); - for (i = 0; i < 110; i++) { - udelay(100); - } + spin_unlock_bh(&bp->phy_lock); + msleep(20); + spin_lock_bh(&bp->phy_lock); } bnx2_write_phy(bp, MII_ADVERTISE, new_adv); bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); - if (CHIP_NUM(bp) == CHIP_NUM_5706) { - /* Speed up link-up time when the link partner - * does not autonegotiate which is very common - * in blade servers. Some blade servers use - * IPMI for kerboard input and it's important - * to minimize link disruptions. Autoneg. involves - * exchanging base pages plus 3 next pages and - * normally completes in about 120 msec. - */ - bp->current_interval = SERDES_AN_TIMEOUT; - bp->serdes_an_pending = 1; - mod_timer(&bp->timer, jiffies + bp->current_interval); - } + /* Speed up link-up time when the link partner + * does not autonegotiate which is very common + * in blade servers. Some blade servers use + * IPMI for kerboard input and it's important + * to minimize link disruptions. Autoneg. involves + * exchanging base pages plus 3 next pages and + * normally completes in about 120 msec. + */ + bp->current_interval = SERDES_AN_TIMEOUT; + bp->serdes_an_pending = 1; + mod_timer(&bp->timer, jiffies + bp->current_interval); } return 0; @@ -1039,7 +1140,7 @@ bnx2_setup_serdes_phy(struct bnx2 *bp) #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA) - + #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL) static int @@ -1072,7 +1173,7 @@ bnx2_setup_copper_phy(struct bnx2 *bp) new_adv_reg |= ADVERTISE_100FULL; if (bp->advertising & ADVERTISED_1000baseT_Full) new_adv1000_reg |= ADVERTISE_1000FULL; - + new_adv_reg |= ADVERTISE_CSMA; new_adv_reg |= bnx2_phy_get_pause_adv(bp); @@ -1105,20 +1206,19 @@ bnx2_setup_copper_phy(struct bnx2 *bp) } if (new_bmcr != bmcr) { u32 bmsr; - int i = 0; bnx2_read_phy(bp, MII_BMSR, &bmsr); bnx2_read_phy(bp, MII_BMSR, &bmsr); - + if (bmsr & BMSR_LSTATUS) { /* Force link down */ bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); - do { - udelay(100); - bnx2_read_phy(bp, MII_BMSR, &bmsr); - bnx2_read_phy(bp, MII_BMSR, &bmsr); - i++; - } while ((bmsr & BMSR_LSTATUS) && (i < 620)); + spin_unlock_bh(&bp->phy_lock); + msleep(50); + spin_lock_bh(&bp->phy_lock); + + bnx2_read_phy(bp, MII_BMSR, &bmsr); + bnx2_read_phy(bp, MII_BMSR, &bmsr); } bnx2_write_phy(bp, MII_BMCR, new_bmcr); @@ -1210,9 +1310,8 @@ bnx2_init_5706s_phy(struct bnx2 *bp) { bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; - if (CHIP_NUM(bp) == CHIP_NUM_5706) { - REG_WR(bp, BNX2_MISC_UNUSED0, 0x300); - } + if (CHIP_NUM(bp) == CHIP_NUM_5706) + REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); if (bp->dev->mtu > 1500) { u32 val; @@ -1246,8 +1345,6 @@ bnx2_init_copper_phy(struct bnx2 *bp) { u32 val; - bp->phy_flags |= PHY_CRC_FIX_FLAG; - if (bp->phy_flags & PHY_CRC_FIX_FLAG) { bnx2_write_phy(bp, 0x18, 0x0c00); bnx2_write_phy(bp, 0x17, 0x000a); @@ -1259,6 +1356,14 @@ bnx2_init_copper_phy(struct bnx2 *bp) bnx2_write_phy(bp, 0x18, 0x0400); } + if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) { + bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, + MII_BNX2_DSP_EXPAND_REG | 0x8); + bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); + val &= ~(1 << 8); + bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val); + } + if (bp->dev->mtu > 1500) { /* Set extended packet length bit */ bnx2_write_phy(bp, 0x18, 0x7); @@ -1349,13 +1454,13 @@ bnx2_set_phy_loopback(struct bnx2 *bp) for (i = 0; i < 10; i++) { if (bnx2_test_link(bp) == 0) break; - udelay(10); + msleep(100); } mac_mode = REG_RD(bp, BNX2_EMAC_MODE); mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | - BNX2_EMAC_MODE_25G); + BNX2_EMAC_MODE_25G_MODE); mac_mode |= BNX2_EMAC_MODE_PORT_GMII; REG_WR(bp, BNX2_EMAC_MODE, mac_mode); @@ -1406,6 +1511,40 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent) return 0; } +static int +bnx2_init_5709_context(struct bnx2 *bp) +{ + int i, ret = 0; + u32 val; + + val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12); + val |= (BCM_PAGE_BITS - 8) << 16; + REG_WR(bp, BNX2_CTX_COMMAND, val); + for (i = 0; i < bp->ctx_pages; i++) { + int j; + + REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0, + (bp->ctx_blk_mapping[i] & 0xffffffff) | + BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID); + REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1, + (u64) bp->ctx_blk_mapping[i] >> 32); + REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i | + BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); + for (j = 0; j < 10; j++) { + + val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL); + if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) + break; + udelay(5); + } + if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) { + ret = -EBUSY; + break; + } + } + return ret; +} + static void bnx2_init_context(struct bnx2 *bp) { @@ -1499,7 +1638,7 @@ bnx2_alloc_bad_rbuf(struct bnx2 *bp) } static void -bnx2_set_mac_addr(struct bnx2 *bp) +bnx2_set_mac_addr(struct bnx2 *bp) { u32 val; u8 *mac_addr = bp->dev->dev_addr; @@ -1508,7 +1647,7 @@ bnx2_set_mac_addr(struct bnx2 *bp) REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val); - val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | + val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | (mac_addr[4] << 8) | mac_addr[5]; REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val); @@ -1520,19 +1659,17 @@ bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index) struct sk_buff *skb; struct sw_bd *rx_buf = &bp->rx_buf_ring[index]; dma_addr_t mapping; - struct rx_bd *rxbd = &bp->rx_desc_ring[index]; + struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)]; unsigned long align; - skb = dev_alloc_skb(bp->rx_buf_size); + skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size); if (skb == NULL) { return -ENOMEM; } - if (unlikely((align = (unsigned long) skb->data & 0x7))) { - skb_reserve(skb, 8 - align); - } + if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1)))) + skb_reserve(skb, BNX2_RX_ALIGN - align); - skb->dev = bp->dev; mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); @@ -1591,9 +1728,9 @@ bnx2_tx_int(struct bnx2 *bp) tx_buf = &bp->tx_buf_ring[sw_ring_cons]; skb = tx_buf->skb; -#ifdef BCM_TSO +#ifdef BCM_TSO /* partial BD completions possible with TSO packets */ - if (skb_shinfo(skb)->tso_size) { + if (skb_is_gso(skb)) { u16 last_idx, last_ring_idx; last_idx = sw_cons + @@ -1629,7 +1766,7 @@ bnx2_tx_int(struct bnx2 *bp) tx_free_bd += last + 1; - dev_kfree_skb_irq(skb); + dev_kfree_skb(skb); hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0; @@ -1640,15 +1777,20 @@ bnx2_tx_int(struct bnx2 *bp) } bp->tx_cons = sw_cons; + /* Need to make the tx_cons update visible to bnx2_start_xmit() + * before checking for netif_queue_stopped(). Without the + * memory barrier, there is a small possibility that bnx2_start_xmit() + * will miss it and cause the queue to be stopped forever. + */ + smp_mb(); - if (unlikely(netif_queue_stopped(bp->dev))) { - spin_lock(&bp->tx_lock); + if (unlikely(netif_queue_stopped(bp->dev)) && + (bnx2_tx_avail(bp) > bp->tx_wake_thresh)) { + netif_tx_lock(bp->dev); if ((netif_queue_stopped(bp->dev)) && - (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) { - + (bnx2_tx_avail(bp) > bp->tx_wake_thresh)) netif_wake_queue(bp->dev); - } - spin_unlock(&bp->tx_lock); + netif_tx_unlock(bp->dev); } } @@ -1656,23 +1798,30 @@ static inline void bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb, u16 cons, u16 prod) { - struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons]; - struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod]; - struct rx_bd *cons_bd = &bp->rx_desc_ring[cons]; - struct rx_bd *prod_bd = &bp->rx_desc_ring[prod]; + struct sw_bd *cons_rx_buf, *prod_rx_buf; + struct rx_bd *cons_bd, *prod_bd; + + cons_rx_buf = &bp->rx_buf_ring[cons]; + prod_rx_buf = &bp->rx_buf_ring[prod]; pci_dma_sync_single_for_device(bp->pdev, pci_unmap_addr(cons_rx_buf, mapping), bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE); - prod_rx_buf->skb = cons_rx_buf->skb; - pci_unmap_addr_set(prod_rx_buf, mapping, - pci_unmap_addr(cons_rx_buf, mapping)); + bp->rx_prod_bseq += bp->rx_buf_use_size; - memcpy(prod_bd, cons_bd, 8); + prod_rx_buf->skb = skb; - bp->rx_prod_bseq += bp->rx_buf_use_size; + if (cons == prod) + return; + + pci_unmap_addr_set(prod_rx_buf, mapping, + pci_unmap_addr(cons_rx_buf, mapping)); + cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; + prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; + prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; + prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; } static int @@ -1699,14 +1848,19 @@ bnx2_rx_int(struct bnx2 *bp, int budget) u32 status; struct sw_bd *rx_buf; struct sk_buff *skb; + dma_addr_t dma_addr; sw_ring_cons = RX_RING_IDX(sw_cons); sw_ring_prod = RX_RING_IDX(sw_prod); rx_buf = &bp->rx_buf_ring[sw_ring_cons]; skb = rx_buf->skb; - pci_dma_sync_single_for_cpu(bp->pdev, - pci_unmap_addr(rx_buf, mapping), + + rx_buf->skb = NULL; + + dma_addr = pci_unmap_addr(rx_buf, mapping); + + pci_dma_sync_single_for_cpu(bp->pdev, dma_addr, bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE); rx_hdr = (struct l2_fhdr *) skb->data; @@ -1728,7 +1882,7 @@ bnx2_rx_int(struct bnx2 *bp, int budget) if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) { struct sk_buff *new_skb; - new_skb = dev_alloc_skb(len + 2); + new_skb = netdev_alloc_skb(bp->dev, len + 2); if (new_skb == NULL) goto reuse_rx; @@ -1739,7 +1893,6 @@ bnx2_rx_int(struct bnx2 *bp, int budget) skb_reserve(new_skb, 2); skb_put(new_skb, len); - new_skb->dev = bp->dev; bnx2_reuse_rx_skb(bp, skb, sw_ring_cons, sw_ring_prod); @@ -1747,8 +1900,7 @@ bnx2_rx_int(struct bnx2 *bp, int budget) skb = new_skb; } else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) { - pci_unmap_single(bp->pdev, - pci_unmap_addr(rx_buf, mapping), + pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); skb_reserve(skb, bp->rx_offset); @@ -1764,9 +1916,9 @@ reuse_rx: skb->protocol = eth_type_trans(skb, bp->dev); if ((len > (bp->dev->mtu + ETH_HLEN)) && - (htons(skb->protocol) != 0x8100)) { + (ntohs(skb->protocol) != 0x8100)) { - dev_kfree_skb_irq(skb); + dev_kfree_skb(skb); goto next_rx; } @@ -1794,8 +1946,6 @@ reuse_rx: rx_pkt++; next_rx: - rx_buf->skb = NULL; - sw_cons = NEXT_RX_BD(sw_cons); sw_prod = NEXT_RX_BD(sw_prod); @@ -1828,7 +1978,7 @@ next_rx: * is that the MSI interrupt is always serviced. */ static irqreturn_t -bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs) +bnx2_msi(int irq, void *dev_instance) { struct net_device *dev = dev_instance; struct bnx2 *bp = netdev_priv(dev); @@ -1848,7 +1998,7 @@ bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs) } static irqreturn_t -bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs) +bnx2_interrupt(int irq, void *dev_instance) { struct net_device *dev = dev_instance; struct bnx2 *bp = netdev_priv(dev); @@ -1906,6 +2056,13 @@ bnx2_poll(struct net_device *dev, int *budget) spin_lock(&bp->phy_lock); bnx2_phy_int(bp); spin_unlock(&bp->phy_lock); + + /* This is needed to take care of transient status + * during link changes. + */ + REG_WR(bp, BNX2_HC_COMMAND, + bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); + REG_RD(bp, BNX2_HC_COMMAND); } if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons) @@ -1917,12 +2074,12 @@ bnx2_poll(struct net_device *dev, int *budget) if (orig_budget > dev->quota) orig_budget = dev->quota; - + work_done = bnx2_rx_int(bp, orig_budget); *budget -= work_done; dev->quota -= work_done; } - + bp->last_status_idx = bp->status_blk->status_idx; rmb(); @@ -1948,7 +2105,7 @@ bnx2_poll(struct net_device *dev, int *budget) return 1; } -/* Called with rtnl_lock from vlan functions and also dev->xmit_lock +/* Called with rtnl_lock from vlan functions and also netif_tx_lock * from set_multicast. */ static void @@ -1973,7 +2130,8 @@ bnx2_set_rx_mode(struct net_device *dev) if (dev->flags & IFF_PROMISC) { /* Promiscuous mode. */ rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; - sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN; + sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | + BNX2_RPM_SORT_USER0_PROM_VLAN; } else if (dev->flags & IFF_ALLMULTI) { for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { @@ -2022,6 +2180,92 @@ bnx2_set_rx_mode(struct net_device *dev) spin_unlock_bh(&bp->phy_lock); } +#define FW_BUF_SIZE 0x8000 + +static int +bnx2_gunzip_init(struct bnx2 *bp) +{ + if ((bp->gunzip_buf = vmalloc(FW_BUF_SIZE)) == NULL) + goto gunzip_nomem1; + + if ((bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL)) == NULL) + goto gunzip_nomem2; + + bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL); + if (bp->strm->workspace == NULL) + goto gunzip_nomem3; + + return 0; + +gunzip_nomem3: + kfree(bp->strm); + bp->strm = NULL; + +gunzip_nomem2: + vfree(bp->gunzip_buf); + bp->gunzip_buf = NULL; + +gunzip_nomem1: + printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for " + "uncompression.\n", bp->dev->name); + return -ENOMEM; +} + +static void +bnx2_gunzip_end(struct bnx2 *bp) +{ + kfree(bp->strm->workspace); + + kfree(bp->strm); + bp->strm = NULL; + + if (bp->gunzip_buf) { + vfree(bp->gunzip_buf); + bp->gunzip_buf = NULL; + } +} + +static int +bnx2_gunzip(struct bnx2 *bp, u8 *zbuf, int len, void **outbuf, int *outlen) +{ + int n, rc; + + /* check gzip header */ + if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) + return -EINVAL; + + n = 10; + +#define FNAME 0x8 + if (zbuf[3] & FNAME) + while ((zbuf[n++] != 0) && (n < len)); + + bp->strm->next_in = zbuf + n; + bp->strm->avail_in = len - n; + bp->strm->next_out = bp->gunzip_buf; + bp->strm->avail_out = FW_BUF_SIZE; + + rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); + if (rc != Z_OK) + return rc; + + rc = zlib_inflate(bp->strm, Z_FINISH); + + *outlen = FW_BUF_SIZE - bp->strm->avail_out; + *outbuf = bp->gunzip_buf; + + if ((rc != Z_OK) && (rc != Z_STREAM_END)) + printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n", + bp->dev->name, bp->strm->msg); + + zlib_inflateEnd(bp->strm); + + if (rc == Z_STREAM_END) + return 0; + + return rc; +} + static void load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, u32 rv2p_proc) @@ -2031,9 +2275,9 @@ load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, for (i = 0; i < rv2p_code_len; i += 8) { - REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code); + REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code)); rv2p_code++; - REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code); + REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code)); rv2p_code++; if (rv2p_proc == RV2P_PROC1) { @@ -2055,11 +2299,12 @@ load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, } } -static void +static int load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) { u32 offset; u32 val; + int rc; /* Halt the CPU. */ val = REG_RD_IND(bp, cpu_reg->mode); @@ -2069,11 +2314,22 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) /* Load the Text area. */ offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); - if (fw->text) { + if (fw->gz_text) { + u32 text_len; + void *text; + + rc = bnx2_gunzip(bp, fw->gz_text, fw->gz_text_len, &text, + &text_len); + if (rc) + return rc; + + fw->text = text; + } + if (fw->gz_text) { int j; for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { - REG_WR_IND(bp, offset, fw->text[j]); + REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j])); } } @@ -2127,17 +2383,36 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) val &= ~cpu_reg->mode_value_halt; REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); REG_WR_IND(bp, cpu_reg->mode, val); + + return 0; } -static void +static int bnx2_init_cpus(struct bnx2 *bp) { struct cpu_reg cpu_reg; - struct fw_info fw; + struct fw_info *fw; + int rc = 0; + void *text; + u32 text_len; + + if ((rc = bnx2_gunzip_init(bp)) != 0) + return rc; /* Initialize the RV2P processor. */ - load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1); - load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2); + rc = bnx2_gunzip(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), &text, + &text_len); + if (rc) + goto init_cpu_err; + + load_rv2p_fw(bp, text, text_len, RV2P_PROC1); + + rc = bnx2_gunzip(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), &text, + &text_len); + if (rc) + goto init_cpu_err; + + load_rv2p_fw(bp, text, text_len, RV2P_PROC2); /* Initialize the RX Processor. */ cpu_reg.mode = BNX2_RXP_CPU_MODE; @@ -2152,38 +2427,15 @@ bnx2_init_cpus(struct bnx2 *bp) cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT; cpu_reg.spad_base = BNX2_RXP_SCRATCH; cpu_reg.mips_view_base = 0x8000000; - - fw.ver_major = bnx2_RXP_b06FwReleaseMajor; - fw.ver_minor = bnx2_RXP_b06FwReleaseMinor; - fw.ver_fix = bnx2_RXP_b06FwReleaseFix; - fw.start_addr = bnx2_RXP_b06FwStartAddr; - - fw.text_addr = bnx2_RXP_b06FwTextAddr; - fw.text_len = bnx2_RXP_b06FwTextLen; - fw.text_index = 0; - fw.text = bnx2_RXP_b06FwText; - - fw.data_addr = bnx2_RXP_b06FwDataAddr; - fw.data_len = bnx2_RXP_b06FwDataLen; - fw.data_index = 0; - fw.data = bnx2_RXP_b06FwData; - - fw.sbss_addr = bnx2_RXP_b06FwSbssAddr; - fw.sbss_len = bnx2_RXP_b06FwSbssLen; - fw.sbss_index = 0; - fw.sbss = bnx2_RXP_b06FwSbss; - - fw.bss_addr = bnx2_RXP_b06FwBssAddr; - fw.bss_len = bnx2_RXP_b06FwBssLen; - fw.bss_index = 0; - fw.bss = bnx2_RXP_b06FwBss; - - fw.rodata_addr = bnx2_RXP_b06FwRodataAddr; - fw.rodata_len = bnx2_RXP_b06FwRodataLen; - fw.rodata_index = 0; - fw.rodata = bnx2_RXP_b06FwRodata; - - load_cpu_fw(bp, &cpu_reg, &fw); + + if (CHIP_NUM(bp) == CHIP_NUM_5709) + fw = &bnx2_rxp_fw_09; + else + fw = &bnx2_rxp_fw_06; + + rc = load_cpu_fw(bp, &cpu_reg, fw); + if (rc) + goto init_cpu_err; /* Initialize the TX Processor. */ cpu_reg.mode = BNX2_TXP_CPU_MODE; @@ -2198,38 +2450,15 @@ bnx2_init_cpus(struct bnx2 *bp) cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT; cpu_reg.spad_base = BNX2_TXP_SCRATCH; cpu_reg.mips_view_base = 0x8000000; - - fw.ver_major = bnx2_TXP_b06FwReleaseMajor; - fw.ver_minor = bnx2_TXP_b06FwReleaseMinor; - fw.ver_fix = bnx2_TXP_b06FwReleaseFix; - fw.start_addr = bnx2_TXP_b06FwStartAddr; - - fw.text_addr = bnx2_TXP_b06FwTextAddr; - fw.text_len = bnx2_TXP_b06FwTextLen; - fw.text_index = 0; - fw.text = bnx2_TXP_b06FwText; - - fw.data_addr = bnx2_TXP_b06FwDataAddr; - fw.data_len = bnx2_TXP_b06FwDataLen; - fw.data_index = 0; - fw.data = bnx2_TXP_b06FwData; - - fw.sbss_addr = bnx2_TXP_b06FwSbssAddr; - fw.sbss_len = bnx2_TXP_b06FwSbssLen; - fw.sbss_index = 0; - fw.sbss = bnx2_TXP_b06FwSbss; - - fw.bss_addr = bnx2_TXP_b06FwBssAddr; - fw.bss_len = bnx2_TXP_b06FwBssLen; - fw.bss_index = 0; - fw.bss = bnx2_TXP_b06FwBss; - - fw.rodata_addr = bnx2_TXP_b06FwRodataAddr; - fw.rodata_len = bnx2_TXP_b06FwRodataLen; - fw.rodata_index = 0; - fw.rodata = bnx2_TXP_b06FwRodata; - - load_cpu_fw(bp, &cpu_reg, &fw); + + if (CHIP_NUM(bp) == CHIP_NUM_5709) + fw = &bnx2_txp_fw_09; + else + fw = &bnx2_txp_fw_06; + + rc = load_cpu_fw(bp, &cpu_reg, fw); + if (rc) + goto init_cpu_err; /* Initialize the TX Patch-up Processor. */ cpu_reg.mode = BNX2_TPAT_CPU_MODE; @@ -2244,38 +2473,15 @@ bnx2_init_cpus(struct bnx2 *bp) cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT; cpu_reg.spad_base = BNX2_TPAT_SCRATCH; cpu_reg.mips_view_base = 0x8000000; - - fw.ver_major = bnx2_TPAT_b06FwReleaseMajor; - fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor; - fw.ver_fix = bnx2_TPAT_b06FwReleaseFix; - fw.start_addr = bnx2_TPAT_b06FwStartAddr; - - fw.text_addr = bnx2_TPAT_b06FwTextAddr; - fw.text_len = bnx2_TPAT_b06FwTextLen; - fw.text_index = 0; - fw.text = bnx2_TPAT_b06FwText; - - fw.data_addr = bnx2_TPAT_b06FwDataAddr; - fw.data_len = bnx2_TPAT_b06FwDataLen; - fw.data_index = 0; - fw.data = bnx2_TPAT_b06FwData; - - fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr; - fw.sbss_len = bnx2_TPAT_b06FwSbssLen; - fw.sbss_index = 0; - fw.sbss = bnx2_TPAT_b06FwSbss; - - fw.bss_addr = bnx2_TPAT_b06FwBssAddr; - fw.bss_len = bnx2_TPAT_b06FwBssLen; - fw.bss_index = 0; - fw.bss = bnx2_TPAT_b06FwBss; - - fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr; - fw.rodata_len = bnx2_TPAT_b06FwRodataLen; - fw.rodata_index = 0; - fw.rodata = bnx2_TPAT_b06FwRodata; - - load_cpu_fw(bp, &cpu_reg, &fw); + + if (CHIP_NUM(bp) == CHIP_NUM_5709) + fw = &bnx2_tpat_fw_09; + else + fw = &bnx2_tpat_fw_06; + + rc = load_cpu_fw(bp, &cpu_reg, fw); + if (rc) + goto init_cpu_err; /* Initialize the Completion Processor. */ cpu_reg.mode = BNX2_COM_CPU_MODE; @@ -2290,39 +2496,40 @@ bnx2_init_cpus(struct bnx2 *bp) cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT; cpu_reg.spad_base = BNX2_COM_SCRATCH; cpu_reg.mips_view_base = 0x8000000; - - fw.ver_major = bnx2_COM_b06FwReleaseMajor; - fw.ver_minor = bnx2_COM_b06FwReleaseMinor; - fw.ver_fix = bnx2_COM_b06FwReleaseFix; - fw.start_addr = bnx2_COM_b06FwStartAddr; - - fw.text_addr = bnx2_COM_b06FwTextAddr; - fw.text_len = bnx2_COM_b06FwTextLen; - fw.text_index = 0; - fw.text = bnx2_COM_b06FwText; - fw.data_addr = bnx2_COM_b06FwDataAddr; - fw.data_len = bnx2_COM_b06FwDataLen; - fw.data_index = 0; - fw.data = bnx2_COM_b06FwData; - - fw.sbss_addr = bnx2_COM_b06FwSbssAddr; - fw.sbss_len = bnx2_COM_b06FwSbssLen; - fw.sbss_index = 0; - fw.sbss = bnx2_COM_b06FwSbss; + if (CHIP_NUM(bp) == CHIP_NUM_5709) + fw = &bnx2_com_fw_09; + else + fw = &bnx2_com_fw_06; - fw.bss_addr = bnx2_COM_b06FwBssAddr; - fw.bss_len = bnx2_COM_b06FwBssLen; - fw.bss_index = 0; - fw.bss = bnx2_COM_b06FwBss; + rc = load_cpu_fw(bp, &cpu_reg, fw); + if (rc) + goto init_cpu_err; - fw.rodata_addr = bnx2_COM_b06FwRodataAddr; - fw.rodata_len = bnx2_COM_b06FwRodataLen; - fw.rodata_index = 0; - fw.rodata = bnx2_COM_b06FwRodata; + /* Initialize the Command Processor. */ + cpu_reg.mode = BNX2_CP_CPU_MODE; + cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA; + cpu_reg.state = BNX2_CP_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE; + cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK; + cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION; + cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BNX2_CP_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; - load_cpu_fw(bp, &cpu_reg, &fw); + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + fw = &bnx2_cp_fw_09; + rc = load_cpu_fw(bp, &cpu_reg, fw); + if (rc) + goto init_cpu_err; + } +init_cpu_err: + bnx2_gunzip_end(bp); + return rc; } static int @@ -2544,7 +2751,7 @@ bnx2_enable_nvram_access(struct bnx2 *bp) val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); /* Enable both bits, even on read. */ - REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, + REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); } @@ -2555,7 +2762,7 @@ bnx2_disable_nvram_access(struct bnx2 *bp) val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); /* Disable both bits, even after read. */ - REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, + REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, val & ~(BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN)); } @@ -2884,7 +3091,7 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, int buf_size) { u32 written, offset32, len32; - u8 *buf, start[4], end[4]; + u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL; int rc = 0; int align_start, align_end; @@ -2895,7 +3102,7 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, if ((align_start = (offset32 & 3))) { offset32 &= ~3; - len32 += align_start; + len32 += (4 - align_start); if ((rc = bnx2_nvram_read(bp, offset32, start, 4))) return rc; } @@ -2912,16 +3119,25 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, } if (align_start || align_end) { - buf = kmalloc(len32, GFP_KERNEL); - if (buf == 0) + align_buf = kmalloc(len32, GFP_KERNEL); + if (align_buf == NULL) return -ENOMEM; if (align_start) { - memcpy(buf, start, 4); + memcpy(align_buf, start, 4); } if (align_end) { - memcpy(buf + len32 - 4, end, 4); + memcpy(align_buf + len32 - 4, end, 4); + } + memcpy(align_buf + align_start, data_buf, buf_size); + buf = align_buf; + } + + if (bp->flash_info->buffered == 0) { + flash_buffer = kmalloc(264, GFP_KERNEL); + if (flash_buffer == NULL) { + rc = -ENOMEM; + goto nvram_write_end; } - memcpy(buf + align_start, data_buf, buf_size); } written = 0; @@ -2929,7 +3145,6 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, u32 page_start, page_end, data_start, data_end; u32 addr, cmd_flags; int i; - u8 flash_buffer[264]; /* Find the page_start addr */ page_start = offset32 + written; @@ -2939,7 +3154,7 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, /* Find the data_start addr */ data_start = (written == 0) ? offset32 : page_start; /* Find the data_end addr */ - data_end = (page_end > offset32 + len32) ? + data_end = (page_end > offset32 + len32) ? (offset32 + len32) : page_end; /* Request access to the flash interface. */ @@ -2960,8 +3175,8 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, cmd_flags |= BNX2_NVM_COMMAND_LAST; } rc = bnx2_nvram_read_dword(bp, - page_start + j, - &flash_buffer[j], + page_start + j, + &flash_buffer[j], cmd_flags); if (rc) @@ -2988,7 +3203,7 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, if (bp->flash_info->buffered == 0) { for (addr = page_start; addr < data_start; addr += 4, i += 4) { - + rc = bnx2_nvram_write_dword(bp, addr, &flash_buffer[i], cmd_flags); @@ -3000,7 +3215,7 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, } /* Loop to write the new data from data_start to data_end */ - for (addr = data_start; addr < data_end; addr += 4, i++) { + for (addr = data_start; addr < data_end; addr += 4, i += 4) { if ((addr == page_end - 4) || ((bp->flash_info->buffered) && (addr == data_end - 4))) { @@ -3022,7 +3237,7 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, if (bp->flash_info->buffered == 0) { for (addr = data_end; addr < page_end; addr += 4, i += 4) { - + if (addr == page_end-4) { cmd_flags = BNX2_NVM_COMMAND_LAST; } @@ -3048,8 +3263,8 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, } nvram_write_end: - if (align_start || align_end) - kfree(buf); + kfree(flash_buffer); + kfree(align_buf); return rc; } @@ -3081,31 +3296,44 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) * before we issue a reset. */ val = REG_RD(bp, BNX2_MISC_ID); - val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | - BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | - BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET); + REG_RD(bp, BNX2_MISC_COMMAND); + udelay(5); - /* Chip reset. */ - REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); + val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; - if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || - (CHIP_ID(bp) == CHIP_ID_5706_A1)) - msleep(15); + pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val); - /* Reset takes approximate 30 usec */ - for (i = 0; i < 10; i++) { - val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG); - if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | - BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { - break; + } else { + val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; + + /* Chip reset. */ + REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); + + if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || + (CHIP_ID(bp) == CHIP_ID_5706_A1)) { + current->state = TASK_UNINTERRUPTIBLE; + schedule_timeout(HZ / 50); } - udelay(10); - } - if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | - BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { - printk(KERN_ERR PFX "Chip reset did not complete\n"); - return -EBUSY; + /* Reset takes approximate 30 usec */ + for (i = 0; i < 10; i++) { + val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG); + if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) + break; + udelay(10); + } + + if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { + printk(KERN_ERR PFX "Chip reset did not complete\n"); + return -EBUSY; + } } /* Make sure byte swapping is properly configured. */ @@ -3144,9 +3372,9 @@ bnx2_init_chip(struct bnx2 *bp) val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP | BNX2_DMA_CONFIG_DATA_WORD_SWAP | #ifdef __BIG_ENDIAN - BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | + BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | #endif - BNX2_DMA_CONFIG_CNTL_WORD_SWAP | + BNX2_DMA_CONFIG_CNTL_WORD_SWAP | DMA_READ_CHANS << 12 | DMA_WRITE_CHANS << 16; @@ -3183,9 +3411,14 @@ bnx2_init_chip(struct bnx2 *bp) /* Initialize context mapping and zero out the quick contexts. The * context block must have already been enabled. */ - bnx2_init_context(bp); + if (CHIP_NUM(bp) == CHIP_NUM_5709) + bnx2_init_5709_context(bp); + else + bnx2_init_context(bp); + + if ((rc = bnx2_init_cpus(bp)) != 0) + return rc; - bnx2_init_cpus(bp); bnx2_init_nvram(bp); bnx2_set_mac_addr(bp); @@ -3237,7 +3470,7 @@ bnx2_init_chip(struct bnx2 *bp) REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H, (u64) bp->stats_blk_mapping >> 32); - REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, + REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP, @@ -3287,18 +3520,50 @@ bnx2_init_chip(struct bnx2 *bp) udelay(20); + bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND); + return rc; } +static void +bnx2_init_tx_context(struct bnx2 *bp, u32 cid) +{ + u32 val, offset0, offset1, offset2, offset3; + + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + offset0 = BNX2_L2CTX_TYPE_XI; + offset1 = BNX2_L2CTX_CMD_TYPE_XI; + offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI; + offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI; + } else { + offset0 = BNX2_L2CTX_TYPE; + offset1 = BNX2_L2CTX_CMD_TYPE; + offset2 = BNX2_L2CTX_TBDR_BHADDR_HI; + offset3 = BNX2_L2CTX_TBDR_BHADDR_LO; + } + val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2; + CTX_WR(bp, GET_CID_ADDR(cid), offset0, val); + + val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); + CTX_WR(bp, GET_CID_ADDR(cid), offset1, val); + + val = (u64) bp->tx_desc_mapping >> 32; + CTX_WR(bp, GET_CID_ADDR(cid), offset2, val); + + val = (u64) bp->tx_desc_mapping & 0xffffffff; + CTX_WR(bp, GET_CID_ADDR(cid), offset3, val); +} static void bnx2_init_tx_ring(struct bnx2 *bp) { struct tx_bd *txbd; - u32 val; + u32 cid; + + bp->tx_wake_thresh = bp->tx_ring_size / 2; txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT]; - + txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32; txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff; @@ -3306,20 +3571,12 @@ bnx2_init_tx_ring(struct bnx2 *bp) bp->tx_cons = 0; bp->hw_tx_cons = 0; bp->tx_prod_bseq = 0; - - val = BNX2_L2CTX_TYPE_TYPE_L2; - val |= BNX2_L2CTX_TYPE_SIZE_L2; - CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val); - val = BNX2_L2CTX_CMD_TYPE_TYPE_L2; - val |= 8 << 16; - CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val); + cid = TX_CID; + bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX; + bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ; - val = (u64) bp->tx_desc_mapping >> 32; - CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val); - - val = (u64) bp->tx_desc_mapping & 0xffffffff; - CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val); + bnx2_init_tx_context(bp, cid); } static void @@ -3327,40 +3584,48 @@ bnx2_init_rx_ring(struct bnx2 *bp) { struct rx_bd *rxbd; int i; - u16 prod, ring_prod; + u16 prod, ring_prod; u32 val; /* 8 for CRC and VLAN */ bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8; - /* 8 for alignment */ - bp->rx_buf_size = bp->rx_buf_use_size + 8; + /* hw alignment */ + bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN; ring_prod = prod = bp->rx_prod = 0; bp->rx_cons = 0; bp->hw_rx_cons = 0; bp->rx_prod_bseq = 0; - - rxbd = &bp->rx_desc_ring[0]; - for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) { - rxbd->rx_bd_len = bp->rx_buf_use_size; - rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; - } - rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32; - rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff; + for (i = 0; i < bp->rx_max_ring; i++) { + int j; + + rxbd = &bp->rx_desc_ring[i][0]; + for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) { + rxbd->rx_bd_len = bp->rx_buf_use_size; + rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; + } + if (i == (bp->rx_max_ring - 1)) + j = 0; + else + j = i + 1; + rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32; + rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] & + 0xffffffff; + } val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; val |= 0x02 << 8; CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val); - val = (u64) bp->rx_desc_mapping >> 32; + val = (u64) bp->rx_desc_mapping[0] >> 32; CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val); - val = (u64) bp->rx_desc_mapping & 0xffffffff; + val = (u64) bp->rx_desc_mapping[0] & 0xffffffff; CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val); - for ( ;ring_prod < bp->rx_ring_size; ) { + for (i = 0; i < bp->rx_ring_size; i++) { if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) { break; } @@ -3374,6 +3639,29 @@ bnx2_init_rx_ring(struct bnx2 *bp) REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq); } +static void +bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size) +{ + u32 num_rings, max; + + bp->rx_ring_size = size; + num_rings = 1; + while (size > MAX_RX_DESC_CNT) { + size -= MAX_RX_DESC_CNT; + num_rings++; + } + /* round to next power of 2 */ + max = MAX_RX_RINGS; + while ((max & num_rings) == 0) + max >>= 1; + + if (num_rings != max) + max <<= 1; + + bp->rx_max_ring = max; + bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1; +} + static void bnx2_free_tx_skbs(struct bnx2 *bp) { @@ -3405,7 +3693,7 @@ bnx2_free_tx_skbs(struct bnx2 *bp) skb_shinfo(skb)->frags[j].size, PCI_DMA_TODEVICE); } - dev_kfree_skb_any(skb); + dev_kfree_skb(skb); i += j + 1; } @@ -3419,7 +3707,7 @@ bnx2_free_rx_skbs(struct bnx2 *bp) if (bp->rx_buf_ring == NULL) return; - for (i = 0; i < RX_DESC_CNT; i++) { + for (i = 0; i < bp->rx_max_ring_idx; i++) { struct sw_bd *rx_buf = &bp->rx_buf_ring[i]; struct sk_buff *skb = rx_buf->skb; @@ -3431,7 +3719,7 @@ bnx2_free_rx_skbs(struct bnx2 *bp) rx_buf->skb = NULL; - dev_kfree_skb_any(skb); + dev_kfree_skb(skb); } } @@ -3452,7 +3740,9 @@ bnx2_reset_nic(struct bnx2 *bp, u32 reset_code) if (rc) return rc; - bnx2_init_chip(bp); + if ((rc = bnx2_init_chip(bp)) != 0) + return rc; + bnx2_init_tx_ring(bp); bnx2_init_rx_ring(bp); return 0; @@ -3466,7 +3756,9 @@ bnx2_init_nic(struct bnx2 *bp) if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) return rc; + spin_lock_bh(&bp->phy_lock); bnx2_init_phy(bp); + spin_unlock_bh(&bp->phy_lock); bnx2_set_link(bp); return 0; } @@ -3476,7 +3768,7 @@ bnx2_test_registers(struct bnx2 *bp) { int ret; int i; - static struct { + static const struct { u16 offset; u16 flags; u32 rw_mask; @@ -3506,74 +3798,9 @@ bnx2_test_registers(struct bnx2 *bp) { 0x0c00, 0, 0x00000000, 0x00000001 }, { 0x0c04, 0, 0x00000000, 0x03ff0001 }, { 0x0c08, 0, 0x0f0ff073, 0x00000000 }, - { 0x0c0c, 0, 0x00ffffff, 0x00000000 }, - { 0x0c30, 0, 0x00000000, 0xffffffff }, - { 0x0c34, 0, 0x00000000, 0xffffffff }, - { 0x0c38, 0, 0x00000000, 0xffffffff }, - { 0x0c3c, 0, 0x00000000, 0xffffffff }, - { 0x0c40, 0, 0x00000000, 0xffffffff }, - { 0x0c44, 0, 0x00000000, 0xffffffff }, - { 0x0c48, 0, 0x00000000, 0x0007ffff }, - { 0x0c4c, 0, 0x00000000, 0xffffffff }, - { 0x0c50, 0, 0x00000000, 0xffffffff }, - { 0x0c54, 0, 0x00000000, 0xffffffff }, - { 0x0c58, 0, 0x00000000, 0xffffffff }, - { 0x0c5c, 0, 0x00000000, 0xffffffff }, - { 0x0c60, 0, 0x00000000, 0xffffffff }, - { 0x0c64, 0, 0x00000000, 0xffffffff }, - { 0x0c68, 0, 0x00000000, 0xffffffff }, - { 0x0c6c, 0, 0x00000000, 0xffffffff }, - { 0x0c70, 0, 0x00000000, 0xffffffff }, - { 0x0c74, 0, 0x00000000, 0xffffffff }, - { 0x0c78, 0, 0x00000000, 0xffffffff }, - { 0x0c7c, 0, 0x00000000, 0xffffffff }, - { 0x0c80, 0, 0x00000000, 0xffffffff }, - { 0x0c84, 0, 0x00000000, 0xffffffff }, - { 0x0c88, 0, 0x00000000, 0xffffffff }, - { 0x0c8c, 0, 0x00000000, 0xffffffff }, - { 0x0c90, 0, 0x00000000, 0xffffffff }, - { 0x0c94, 0, 0x00000000, 0xffffffff }, - { 0x0c98, 0, 0x00000000, 0xffffffff }, - { 0x0c9c, 0, 0x00000000, 0xffffffff }, - { 0x0ca0, 0, 0x00000000, 0xffffffff }, - { 0x0ca4, 0, 0x00000000, 0xffffffff }, - { 0x0ca8, 0, 0x00000000, 0x0007ffff }, - { 0x0cac, 0, 0x00000000, 0xffffffff }, - { 0x0cb0, 0, 0x00000000, 0xffffffff }, - { 0x0cb4, 0, 0x00000000, 0xffffffff }, - { 0x0cb8, 0, 0x00000000, 0xffffffff }, - { 0x0cbc, 0, 0x00000000, 0xffffffff }, - { 0x0cc0, 0, 0x00000000, 0xffffffff }, - { 0x0cc4, 0, 0x00000000, 0xffffffff }, - { 0x0cc8, 0, 0x00000000, 0xffffffff }, - { 0x0ccc, 0, 0x00000000, 0xffffffff }, - { 0x0cd0, 0, 0x00000000, 0xffffffff }, - { 0x0cd4, 0, 0x00000000, 0xffffffff }, - { 0x0cd8, 0, 0x00000000, 0xffffffff }, - { 0x0cdc, 0, 0x00000000, 0xffffffff }, - { 0x0ce0, 0, 0x00000000, 0xffffffff }, - { 0x0ce4, 0, 0x00000000, 0xffffffff }, - { 0x0ce8, 0, 0x00000000, 0xffffffff }, - { 0x0cec, 0, 0x00000000, 0xffffffff }, - { 0x0cf0, 0, 0x00000000, 0xffffffff }, - { 0x0cf4, 0, 0x00000000, 0xffffffff }, - { 0x0cf8, 0, 0x00000000, 0xffffffff }, - { 0x0cfc, 0, 0x00000000, 0xffffffff }, - { 0x0d00, 0, 0x00000000, 0xffffffff }, - { 0x0d04, 0, 0x00000000, 0xffffffff }, { 0x1000, 0, 0x00000000, 0x00000001 }, { 0x1004, 0, 0x00000000, 0x000f0001 }, - { 0x1044, 0, 0x00000000, 0xffc003ff }, - { 0x1080, 0, 0x00000000, 0x0001ffff }, - { 0x1084, 0, 0x00000000, 0xffffffff }, - { 0x1088, 0, 0x00000000, 0xffffffff }, - { 0x108c, 0, 0x00000000, 0xffffffff }, - { 0x1090, 0, 0x00000000, 0xffffffff }, - { 0x1094, 0, 0x00000000, 0xffffffff }, - { 0x1098, 0, 0x00000000, 0xffffffff }, - { 0x109c, 0, 0x00000000, 0xffffffff }, - { 0x10a0, 0, 0x00000000, 0xffffffff }, { 0x1408, 0, 0x01c00800, 0x00000000 }, { 0x149c, 0, 0x8000ffff, 0x00000000 }, @@ -3585,111 +3812,9 @@ bnx2_test_registers(struct bnx2 *bp) { 0x14c4, 0, 0x00003fff, 0x00000000 }, { 0x14cc, 0, 0x00000000, 0x00000001 }, { 0x14d0, 0, 0xffffffff, 0x00000000 }, - { 0x1500, 0, 0x00000000, 0xffffffff }, - { 0x1504, 0, 0x00000000, 0xffffffff }, - { 0x1508, 0, 0x00000000, 0xffffffff }, - { 0x150c, 0, 0x00000000, 0xffffffff }, - { 0x1510, 0, 0x00000000, 0xffffffff }, - { 0x1514, 0, 0x00000000, 0xffffffff }, - { 0x1518, 0, 0x00000000, 0xffffffff }, - { 0x151c, 0, 0x00000000, 0xffffffff }, - { 0x1520, 0, 0x00000000, 0xffffffff }, - { 0x1524, 0, 0x00000000, 0xffffffff }, - { 0x1528, 0, 0x00000000, 0xffffffff }, - { 0x152c, 0, 0x00000000, 0xffffffff }, - { 0x1530, 0, 0x00000000, 0xffffffff }, - { 0x1534, 0, 0x00000000, 0xffffffff }, - { 0x1538, 0, 0x00000000, 0xffffffff }, - { 0x153c, 0, 0x00000000, 0xffffffff }, - { 0x1540, 0, 0x00000000, 0xffffffff }, - { 0x1544, 0, 0x00000000, 0xffffffff }, - { 0x1548, 0, 0x00000000, 0xffffffff }, - { 0x154c, 0, 0x00000000, 0xffffffff }, - { 0x1550, 0, 0x00000000, 0xffffffff }, - { 0x1554, 0, 0x00000000, 0xffffffff }, - { 0x1558, 0, 0x00000000, 0xffffffff }, - { 0x1600, 0, 0x00000000, 0xffffffff }, - { 0x1604, 0, 0x00000000, 0xffffffff }, - { 0x1608, 0, 0x00000000, 0xffffffff }, - { 0x160c, 0, 0x00000000, 0xffffffff }, - { 0x1610, 0, 0x00000000, 0xffffffff }, - { 0x1614, 0, 0x00000000, 0xffffffff }, - { 0x1618, 0, 0x00000000, 0xffffffff }, - { 0x161c, 0, 0x00000000, 0xffffffff }, - { 0x1620, 0, 0x00000000, 0xffffffff }, - { 0x1624, 0, 0x00000000, 0xffffffff }, - { 0x1628, 0, 0x00000000, 0xffffffff }, - { 0x162c, 0, 0x00000000, 0xffffffff }, - { 0x1630, 0, 0x00000000, 0xffffffff }, - { 0x1634, 0, 0x00000000, 0xffffffff }, - { 0x1638, 0, 0x00000000, 0xffffffff }, - { 0x163c, 0, 0x00000000, 0xffffffff }, - { 0x1640, 0, 0x00000000, 0xffffffff }, - { 0x1644, 0, 0x00000000, 0xffffffff }, - { 0x1648, 0, 0x00000000, 0xffffffff }, - { 0x164c, 0, 0x00000000, 0xffffffff }, - { 0x1650, 0, 0x00000000, 0xffffffff }, - { 0x1654, 0, 0x00000000, 0xffffffff }, { 0x1800, 0, 0x00000000, 0x00000001 }, { 0x1804, 0, 0x00000000, 0x00000003 }, - { 0x1840, 0, 0x00000000, 0xffffffff }, - { 0x1844, 0, 0x00000000, 0xffffffff }, - { 0x1848, 0, 0x00000000, 0xffffffff }, - { 0x184c, 0, 0x00000000, 0xffffffff }, - { 0x1850, 0, 0x00000000, 0xffffffff }, - { 0x1900, 0, 0x7ffbffff, 0x00000000 }, - { 0x1904, 0, 0xffffffff, 0x00000000 }, - { 0x190c, 0, 0xffffffff, 0x00000000 }, - { 0x1914, 0, 0xffffffff, 0x00000000 }, - { 0x191c, 0, 0xffffffff, 0x00000000 }, - { 0x1924, 0, 0xffffffff, 0x00000000 }, - { 0x192c, 0, 0xffffffff, 0x00000000 }, - { 0x1934, 0, 0xffffffff, 0x00000000 }, - { 0x193c, 0, 0xffffffff, 0x00000000 }, - { 0x1944, 0, 0xffffffff, 0x00000000 }, - { 0x194c, 0, 0xffffffff, 0x00000000 }, - { 0x1954, 0, 0xffffffff, 0x00000000 }, - { 0x195c, 0, 0xffffffff, 0x00000000 }, - { 0x1964, 0, 0xffffffff, 0x00000000 }, - { 0x196c, 0, 0xffffffff, 0x00000000 }, - { 0x1974, 0, 0xffffffff, 0x00000000 }, - { 0x197c, 0, 0xffffffff, 0x00000000 }, - { 0x1980, 0, 0x0700ffff, 0x00000000 }, - - { 0x1c00, 0, 0x00000000, 0x00000001 }, - { 0x1c04, 0, 0x00000000, 0x00000003 }, - { 0x1c08, 0, 0x0000000f, 0x00000000 }, - { 0x1c40, 0, 0x00000000, 0xffffffff }, - { 0x1c44, 0, 0x00000000, 0xffffffff }, - { 0x1c48, 0, 0x00000000, 0xffffffff }, - { 0x1c4c, 0, 0x00000000, 0xffffffff }, - { 0x1c50, 0, 0x00000000, 0xffffffff }, - { 0x1d00, 0, 0x7ffbffff, 0x00000000 }, - { 0x1d04, 0, 0xffffffff, 0x00000000 }, - { 0x1d0c, 0, 0xffffffff, 0x00000000 }, - { 0x1d14, 0, 0xffffffff, 0x00000000 }, - { 0x1d1c, 0, 0xffffffff, 0x00000000 }, - { 0x1d24, 0, 0xffffffff, 0x00000000 }, - { 0x1d2c, 0, 0xffffffff, 0x00000000 }, - { 0x1d34, 0, 0xffffffff, 0x00000000 }, - { 0x1d3c, 0, 0xffffffff, 0x00000000 }, - { 0x1d44, 0, 0xffffffff, 0x00000000 }, - { 0x1d4c, 0, 0xffffffff, 0x00000000 }, - { 0x1d54, 0, 0xffffffff, 0x00000000 }, - { 0x1d5c, 0, 0xffffffff, 0x00000000 }, - { 0x1d64, 0, 0xffffffff, 0x00000000 }, - { 0x1d6c, 0, 0xffffffff, 0x00000000 }, - { 0x1d74, 0, 0xffffffff, 0x00000000 }, - { 0x1d7c, 0, 0xffffffff, 0x00000000 }, - { 0x1d80, 0, 0x0700ffff, 0x00000000 }, - - { 0x2004, 0, 0x00000000, 0x0337000f }, - { 0x2008, 0, 0xffffffff, 0x00000000 }, - { 0x200c, 0, 0xffffffff, 0x00000000 }, - { 0x2010, 0, 0xffffffff, 0x00000000 }, - { 0x2014, 0, 0x801fff80, 0x00000000 }, - { 0x2018, 0, 0x000003ff, 0x00000000 }, { 0x2800, 0, 0x00000000, 0x00000001 }, { 0x2804, 0, 0x00000000, 0x00003f01 }, @@ -3707,16 +3832,6 @@ bnx2_test_registers(struct bnx2 *bp) { 0x2c00, 0, 0x00000000, 0x00000011 }, { 0x2c04, 0, 0x00000000, 0x00030007 }, - { 0x3000, 0, 0x00000000, 0x00000001 }, - { 0x3004, 0, 0x00000000, 0x007007ff }, - { 0x3008, 0, 0x00000003, 0x00000000 }, - { 0x300c, 0, 0xffffffff, 0x00000000 }, - { 0x3010, 0, 0xffffffff, 0x00000000 }, - { 0x3014, 0, 0xffffffff, 0x00000000 }, - { 0x3034, 0, 0xffffffff, 0x00000000 }, - { 0x3038, 0, 0xffffffff, 0x00000000 }, - { 0x3050, 0, 0x00000001, 0x00000000 }, - { 0x3c00, 0, 0x00000000, 0x00000001 }, { 0x3c04, 0, 0x00000000, 0x00070000 }, { 0x3c08, 0, 0x00007f71, 0x07f00000 }, @@ -3726,88 +3841,11 @@ bnx2_test_registers(struct bnx2 *bp) { 0x3c18, 0, 0x00000000, 0xffffffff }, { 0x3c1c, 0, 0xfffff000, 0x00000000 }, { 0x3c20, 0, 0xffffff00, 0x00000000 }, - { 0x3c24, 0, 0xffffffff, 0x00000000 }, - { 0x3c28, 0, 0xffffffff, 0x00000000 }, - { 0x3c2c, 0, 0xffffffff, 0x00000000 }, - { 0x3c30, 0, 0xffffffff, 0x00000000 }, - { 0x3c34, 0, 0xffffffff, 0x00000000 }, - { 0x3c38, 0, 0xffffffff, 0x00000000 }, - { 0x3c3c, 0, 0xffffffff, 0x00000000 }, - { 0x3c40, 0, 0xffffffff, 0x00000000 }, - { 0x3c44, 0, 0xffffffff, 0x00000000 }, - { 0x3c48, 0, 0xffffffff, 0x00000000 }, - { 0x3c4c, 0, 0xffffffff, 0x00000000 }, - { 0x3c50, 0, 0xffffffff, 0x00000000 }, - { 0x3c54, 0, 0xffffffff, 0x00000000 }, - { 0x3c58, 0, 0xffffffff, 0x00000000 }, - { 0x3c5c, 0, 0xffffffff, 0x00000000 }, - { 0x3c60, 0, 0xffffffff, 0x00000000 }, - { 0x3c64, 0, 0xffffffff, 0x00000000 }, - { 0x3c68, 0, 0xffffffff, 0x00000000 }, - { 0x3c6c, 0, 0xffffffff, 0x00000000 }, - { 0x3c70, 0, 0xffffffff, 0x00000000 }, - { 0x3c74, 0, 0x0000003f, 0x00000000 }, - { 0x3c78, 0, 0x00000000, 0x00000000 }, - { 0x3c7c, 0, 0x00000000, 0x00000000 }, - { 0x3c80, 0, 0x3fffffff, 0x00000000 }, - { 0x3c84, 0, 0x0000003f, 0x00000000 }, - { 0x3c88, 0, 0x00000000, 0xffffffff }, - { 0x3c8c, 0, 0x00000000, 0xffffffff }, - - { 0x4000, 0, 0x00000000, 0x00000001 }, - { 0x4004, 0, 0x00000000, 0x00030000 }, - { 0x4008, 0, 0x00000ff0, 0x00000000 }, - { 0x400c, 0, 0xffffffff, 0x00000000 }, - { 0x4088, 0, 0x00000000, 0x00070303 }, - - { 0x4400, 0, 0x00000000, 0x00000001 }, - { 0x4404, 0, 0x00000000, 0x00003f01 }, - { 0x4408, 0, 0x7fff00ff, 0x00000000 }, - { 0x440c, 0, 0xffffffff, 0x00000000 }, - { 0x4410, 0, 0xffff, 0x0000 }, - { 0x4414, 0, 0xffff, 0x0000 }, - { 0x4418, 0, 0xffff, 0x0000 }, - { 0x441c, 0, 0xffff, 0x0000 }, - { 0x4428, 0, 0xffffffff, 0x00000000 }, - { 0x442c, 0, 0xffffffff, 0x00000000 }, - { 0x4430, 0, 0xffffffff, 0x00000000 }, - { 0x4434, 0, 0xffffffff, 0x00000000 }, - { 0x4438, 0, 0xffffffff, 0x00000000 }, - { 0x443c, 0, 0xffffffff, 0x00000000 }, - { 0x4440, 0, 0xffffffff, 0x00000000 }, - { 0x4444, 0, 0xffffffff, 0x00000000 }, - - { 0x4c00, 0, 0x00000000, 0x00000001 }, - { 0x4c04, 0, 0x00000000, 0x0000003f }, - { 0x4c08, 0, 0xffffffff, 0x00000000 }, - { 0x4c0c, 0, 0x0007fc00, 0x00000000 }, - { 0x4c10, 0, 0x80003fe0, 0x00000000 }, - { 0x4c14, 0, 0xffffffff, 0x00000000 }, - { 0x4c44, 0, 0x00000000, 0x9fff9fff }, - { 0x4c48, 0, 0x00000000, 0xb3009fff }, - { 0x4c4c, 0, 0x00000000, 0x77f33b30 }, - { 0x4c50, 0, 0x00000000, 0xffffffff }, { 0x5004, 0, 0x00000000, 0x0000007f }, { 0x5008, 0, 0x0f0007ff, 0x00000000 }, { 0x500c, 0, 0xf800f800, 0x07ff07ff }, - { 0x5400, 0, 0x00000008, 0x00000001 }, - { 0x5404, 0, 0x00000000, 0x0000003f }, - { 0x5408, 0, 0x0000001f, 0x00000000 }, - { 0x540c, 0, 0xffffffff, 0x00000000 }, - { 0x5410, 0, 0xffffffff, 0x00000000 }, - { 0x5414, 0, 0x0000ffff, 0x00000000 }, - { 0x5418, 0, 0x0000ffff, 0x00000000 }, - { 0x541c, 0, 0x0000ffff, 0x00000000 }, - { 0x5420, 0, 0x0000ffff, 0x00000000 }, - { 0x5428, 0, 0x000000ff, 0x00000000 }, - { 0x542c, 0, 0xff00ffff, 0x00000000 }, - { 0x5430, 0, 0x001fff80, 0x00000000 }, - { 0x5438, 0, 0xffffffff, 0x00000000 }, - { 0x543c, 0, 0xffffffff, 0x00000000 }, - { 0x5440, 0, 0xf800f800, 0x07ff07ff }, - { 0x5c00, 0, 0x00000000, 0x00000001 }, { 0x5c04, 0, 0x00000000, 0x0003000f }, { 0x5c08, 0, 0x00000003, 0x00000000 }, @@ -3891,7 +3929,7 @@ reg_test_err: static int bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size) { - static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555, + static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555, 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa }; int i; @@ -3916,7 +3954,7 @@ bnx2_test_memory(struct bnx2 *bp) { int ret = 0; int i; - static struct { + static const struct { u32 offset; u32 len; } mem_tbl[] = { @@ -3935,7 +3973,7 @@ bnx2_test_memory(struct bnx2 *bp) return ret; } } - + return ret; } @@ -3949,7 +3987,6 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) struct sk_buff *skb, *rx_skb; unsigned char *packet; u16 rx_start_idx, rx_idx; - u32 val; dma_addr_t map; struct tx_bd *txbd; struct sw_bd *rx_buf; @@ -3961,18 +3998,18 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) bnx2_set_mac_loopback(bp); } else if (loopback_mode == BNX2_PHY_LOOPBACK) { - bp->loopback = 0; + bp->loopback = PHY_LOOPBACK; bnx2_set_phy_loopback(bp); } else return -EINVAL; pkt_size = 1514; - skb = dev_alloc_skb(pkt_size); + skb = netdev_alloc_skb(bp->dev, pkt_size); if (!skb) return -ENOMEM; packet = skb_put(skb, pkt_size); - memcpy(packet, bp->mac_addr, 6); + memcpy(packet, bp->dev->dev_addr, 6); memset(packet + 6, 0x0, 8); for (i = 14; i < pkt_size; i++) packet[i] = (unsigned char) (i & 0xff); @@ -3980,8 +4017,9 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) map = pci_map_single(bp->pdev, skb->data, pkt_size, PCI_DMA_TODEVICE); - val = REG_RD(bp, BNX2_HC_COMMAND); - REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT); + REG_WR(bp, BNX2_HC_COMMAND, + bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); + REG_RD(bp, BNX2_HC_COMMAND); udelay(5); @@ -4000,19 +4038,20 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) bp->tx_prod = NEXT_TX_BD(bp->tx_prod); bp->tx_prod_bseq += pkt_size; - REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, bp->tx_prod); - REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq); + REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod); + REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq); udelay(100); - val = REG_RD(bp, BNX2_HC_COMMAND); - REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT); + REG_WR(bp, BNX2_HC_COMMAND, + bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); + REG_RD(bp, BNX2_HC_COMMAND); udelay(5); pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE); - dev_kfree_skb_irq(skb); + dev_kfree_skb(skb); if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) { goto loopback_test_done; @@ -4131,7 +4170,7 @@ bnx2_test_link(struct bnx2 *bp) bnx2_read_phy(bp, MII_BMSR, &bmsr); bnx2_read_phy(bp, MII_BMSR, &bmsr); spin_unlock_bh(&bp->phy_lock); - + if (bmsr & BMSR_LSTATUS) { return 0; } @@ -4142,7 +4181,6 @@ static int bnx2_test_intr(struct bnx2 *bp) { int i; - u32 val; u16 status_idx; if (!netif_running(bp->dev)) @@ -4151,8 +4189,7 @@ bnx2_test_intr(struct bnx2 *bp) status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; /* This register is not touched during run-time. */ - val = REG_RD(bp, BNX2_HC_COMMAND); - REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW); + REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); REG_RD(bp, BNX2_HC_COMMAND); for (i = 0; i < 10; i++) { @@ -4171,78 +4208,117 @@ bnx2_test_intr(struct bnx2 *bp) } static void -bnx2_timer(unsigned long data) +bnx2_5706_serdes_timer(struct bnx2 *bp) { - struct bnx2 *bp = (struct bnx2 *) data; - u32 msg; + spin_lock(&bp->phy_lock); + if (bp->serdes_an_pending) + bp->serdes_an_pending--; + else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { + u32 bmcr; - if (!netif_running(bp->dev)) - return; + bp->current_interval = bp->timer_interval; - if (atomic_read(&bp->intr_sem) != 0) - goto bnx2_restart_timer; + bnx2_read_phy(bp, MII_BMCR, &bmcr); - msg = (u32) ++bp->fw_drv_pulse_wr_seq; - REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg); + if (bmcr & BMCR_ANENABLE) { + u32 phy1, phy2; - if ((bp->phy_flags & PHY_SERDES_FLAG) && - (CHIP_NUM(bp) == CHIP_NUM_5706)) { + bnx2_write_phy(bp, 0x1c, 0x7c00); + bnx2_read_phy(bp, 0x1c, &phy1); - spin_lock(&bp->phy_lock); - if (bp->serdes_an_pending) { - bp->serdes_an_pending--; + bnx2_write_phy(bp, 0x17, 0x0f01); + bnx2_read_phy(bp, 0x15, &phy2); + bnx2_write_phy(bp, 0x17, 0x0f01); + bnx2_read_phy(bp, 0x15, &phy2); + + if ((phy1 & 0x10) && /* SIGNAL DETECT */ + !(phy2 & 0x20)) { /* no CONFIG */ + + bmcr &= ~BMCR_ANENABLE; + bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; + bnx2_write_phy(bp, MII_BMCR, bmcr); + bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG; + } } - else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { - u32 bmcr; + } + else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && + (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) { + u32 phy2; - bp->current_interval = bp->timer_interval; + bnx2_write_phy(bp, 0x17, 0x0f01); + bnx2_read_phy(bp, 0x15, &phy2); + if (phy2 & 0x20) { + u32 bmcr; bnx2_read_phy(bp, MII_BMCR, &bmcr); + bmcr |= BMCR_ANENABLE; + bnx2_write_phy(bp, MII_BMCR, bmcr); - if (bmcr & BMCR_ANENABLE) { - u32 phy1, phy2; + bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; + } + } else + bp->current_interval = bp->timer_interval; - bnx2_write_phy(bp, 0x1c, 0x7c00); - bnx2_read_phy(bp, 0x1c, &phy1); + spin_unlock(&bp->phy_lock); +} - bnx2_write_phy(bp, 0x17, 0x0f01); - bnx2_read_phy(bp, 0x15, &phy2); - bnx2_write_phy(bp, 0x17, 0x0f01); - bnx2_read_phy(bp, 0x15, &phy2); +static void +bnx2_5708_serdes_timer(struct bnx2 *bp) +{ + if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) { + bp->serdes_an_pending = 0; + return; + } - if ((phy1 & 0x10) && /* SIGNAL DETECT */ - !(phy2 & 0x20)) { /* no CONFIG */ + spin_lock(&bp->phy_lock); + if (bp->serdes_an_pending) + bp->serdes_an_pending--; + else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { + u32 bmcr; - bmcr &= ~BMCR_ANENABLE; - bmcr |= BMCR_SPEED1000 | - BMCR_FULLDPLX; - bnx2_write_phy(bp, MII_BMCR, bmcr); - bp->phy_flags |= - PHY_PARALLEL_DETECT_FLAG; - } - } + bnx2_read_phy(bp, MII_BMCR, &bmcr); + + if (bmcr & BMCR_ANENABLE) { + bmcr &= ~BMCR_ANENABLE; + bmcr |= BMCR_FULLDPLX | BCM5708S_BMCR_FORCE_2500; + bnx2_write_phy(bp, MII_BMCR, bmcr); + bp->current_interval = SERDES_FORCED_TIMEOUT; + } else { + bmcr &= ~(BMCR_FULLDPLX | BCM5708S_BMCR_FORCE_2500); + bmcr |= BMCR_ANENABLE; + bnx2_write_phy(bp, MII_BMCR, bmcr); + bp->serdes_an_pending = 2; + bp->current_interval = bp->timer_interval; } - else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && - (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) { - u32 phy2; - bnx2_write_phy(bp, 0x17, 0x0f01); - bnx2_read_phy(bp, 0x15, &phy2); - if (phy2 & 0x20) { - u32 bmcr; + } else + bp->current_interval = bp->timer_interval; - bnx2_read_phy(bp, MII_BMCR, &bmcr); - bmcr |= BMCR_ANENABLE; - bnx2_write_phy(bp, MII_BMCR, bmcr); + spin_unlock(&bp->phy_lock); +} - bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; +static void +bnx2_timer(unsigned long data) +{ + struct bnx2 *bp = (struct bnx2 *) data; + u32 msg; - } - } - else - bp->current_interval = bp->timer_interval; + if (!netif_running(bp->dev)) + return; - spin_unlock(&bp->phy_lock); + if (atomic_read(&bp->intr_sem) != 0) + goto bnx2_restart_timer; + + msg = (u32) ++bp->fw_drv_pulse_wr_seq; + REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg); + + bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT); + + if (bp->phy_flags & PHY_SERDES_FLAG) { + if (CHIP_NUM(bp) == CHIP_NUM_5706) + bnx2_5706_serdes_timer(bp); + else if (CHIP_NUM(bp) == CHIP_NUM_5708) + bnx2_5708_serdes_timer(bp); } bnx2_restart_timer: @@ -4274,11 +4350,11 @@ bnx2_open(struct net_device *dev) } else { rc = request_irq(bp->pdev->irq, bnx2_interrupt, - SA_SHIRQ, dev->name, dev); + IRQF_SHARED, dev->name, dev); } } else { - rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ, + rc = request_irq(bp->pdev->irq, bnx2_interrupt, IRQF_SHARED, dev->name, dev); } if (rc) { @@ -4298,7 +4374,7 @@ bnx2_open(struct net_device *dev) bnx2_free_mem(bp); return rc; } - + mod_timer(&bp->timer, jiffies + bp->current_interval); atomic_set(&bp->intr_sem, 0); @@ -4325,7 +4401,7 @@ bnx2_open(struct net_device *dev) if (!rc) { rc = request_irq(bp->pdev->irq, bnx2_interrupt, - SA_SHIRQ, dev->name, dev); + IRQF_SHARED, dev->name, dev); } if (rc) { bnx2_free_skbs(bp); @@ -4346,9 +4422,9 @@ bnx2_open(struct net_device *dev) } static void -bnx2_reset_task(void *data) +bnx2_reset_task(struct work_struct *work) { - struct bnx2 *bp = data; + struct bnx2 *bp = container_of(work, struct bnx2, reset_task); if (!netif_running(bp->dev)) return; @@ -4403,11 +4479,9 @@ bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid) } #endif -/* Called with dev->xmit_lock. - * hard_start_xmit is pseudo-lockless - a lock is only required when - * the tx queue is full. This way, we get the benefit of lockless - * operations most of the time without the complexities to handle - * netif_stop_queue/wake_queue race conditions. +/* Called with netif_tx_lock. + * bnx2_tx_int() runs without netif_tx_lock unless it needs to call + * netif_wake_queue(). */ static int bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) @@ -4432,7 +4506,7 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) ring_prod = TX_RING_IDX(prod); vlan_tag_flags = 0; - if (skb->ip_summed == CHECKSUM_HW) { + if (skb->ip_summed == CHECKSUM_PARTIAL) { vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; } @@ -4440,8 +4514,8 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) vlan_tag_flags |= (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16)); } -#ifdef BCM_TSO - if ((mss = skb_shinfo(skb)->tso_size) && +#ifdef BCM_TSO + if ((mss = skb_shinfo(skb)->gso_size) && (skb->len > (bp->dev->mtu + ETH_HLEN))) { u32 tcp_opt_len, ip_tcp_len; @@ -4461,7 +4535,7 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr); skb->nh.iph->check = 0; - skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len); + skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); skb->h.th->check = ~csum_tcpudp_magic(skb->nh.iph->saddr, skb->nh.iph->daddr, @@ -4479,7 +4553,7 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) } mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE); - + tx_buf = &bp->tx_buf_ring[ring_prod]; tx_buf->skb = skb; pci_unmap_addr_set(tx_buf, mapping, mapping); @@ -4517,8 +4591,8 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) prod = NEXT_TX_BD(prod); bp->tx_prod_bseq += skb->len; - REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod); - REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq); + REG_WR16(bp, bp->tx_bidx_addr, prod); + REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq); mmiowb(); @@ -4526,12 +4600,9 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) dev->trans_start = jiffies; if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) { - spin_lock(&bp->tx_lock); netif_stop_queue(dev); - - if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS) + if (bnx2_tx_avail(bp) > bp->tx_wake_thresh) netif_wake_queue(dev); - spin_unlock(&bp->tx_lock); } return NETDEV_TX_OK; @@ -4554,7 +4625,7 @@ bnx2_close(struct net_device *dev) bnx2_netif_stop(bp); del_timer_sync(&bp->timer); if (bp->flags & NO_WOL_FLAG) - reset_code = BNX2_DRV_MSG_CODE_UNLOAD; + reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN; else if (bp->wol) reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; else @@ -4612,23 +4683,23 @@ bnx2_get_stats(struct net_device *dev) net_stats->tx_bytes = GET_NET_STATS(stats_blk->stat_IfHCOutOctets); - net_stats->multicast = + net_stats->multicast = GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts); - net_stats->collisions = + net_stats->collisions = (unsigned long) stats_blk->stat_EtherStatsCollisions; - net_stats->rx_length_errors = + net_stats->rx_length_errors = (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts + stats_blk->stat_EtherStatsOverrsizePkts); - net_stats->rx_over_errors = + net_stats->rx_over_errors = (unsigned long) stats_blk->stat_IfInMBUFDiscards; - net_stats->rx_frame_errors = + net_stats->rx_frame_errors = (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors; - net_stats->rx_crc_errors = + net_stats->rx_crc_errors = (unsigned long) stats_blk->stat_Dot3StatsFCSErrors; net_stats->rx_errors = net_stats->rx_length_errors + @@ -4649,12 +4720,16 @@ bnx2_get_stats(struct net_device *dev) } net_stats->tx_errors = - (unsigned long) + (unsigned long) stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + net_stats->tx_aborted_errors + net_stats->tx_carrier_errors; + net_stats->rx_missed_errors = + (unsigned long) (stats_blk->stat_IfInMBUFDiscards + + stats_blk->stat_FwRxDrop); + return net_stats; } @@ -4706,7 +4781,7 @@ bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) return 0; } - + static int bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) { @@ -4719,7 +4794,7 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) if (cmd->autoneg == AUTONEG_ENABLE) { autoneg |= AUTONEG_SPEED; - cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED; + cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED; /* allow advertising 1 speed */ if ((cmd->advertising == ADVERTISED_10baseT_Half) || @@ -4751,10 +4826,14 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) } else { if (bp->phy_flags & PHY_SERDES_FLAG) { - if ((cmd->speed != SPEED_1000) || - (cmd->duplex != DUPLEX_FULL)) { + if ((cmd->speed != SPEED_1000 && + cmd->speed != SPEED_2500) || + (cmd->duplex != DUPLEX_FULL)) + return -EINVAL; + + if (cmd->speed == SPEED_2500 && + !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) return -EINVAL; - } } else if (cmd->speed == SPEED_1000) { return -EINVAL; @@ -4794,6 +4873,64 @@ bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) info->fw_version[5] = 0; } +#define BNX2_REGDUMP_LEN (32 * 1024) + +static int +bnx2_get_regs_len(struct net_device *dev) +{ + return BNX2_REGDUMP_LEN; +} + +static void +bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p) +{ + u32 *p = _p, i, offset; + u8 *orig_p = _p; + struct bnx2 *bp = netdev_priv(dev); + u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c, + 0x0800, 0x0880, 0x0c00, 0x0c10, + 0x0c30, 0x0d08, 0x1000, 0x101c, + 0x1040, 0x1048, 0x1080, 0x10a4, + 0x1400, 0x1490, 0x1498, 0x14f0, + 0x1500, 0x155c, 0x1580, 0x15dc, + 0x1600, 0x1658, 0x1680, 0x16d8, + 0x1800, 0x1820, 0x1840, 0x1854, + 0x1880, 0x1894, 0x1900, 0x1984, + 0x1c00, 0x1c0c, 0x1c40, 0x1c54, + 0x1c80, 0x1c94, 0x1d00, 0x1d84, + 0x2000, 0x2030, 0x23c0, 0x2400, + 0x2800, 0x2820, 0x2830, 0x2850, + 0x2b40, 0x2c10, 0x2fc0, 0x3058, + 0x3c00, 0x3c94, 0x4000, 0x4010, + 0x4080, 0x4090, 0x43c0, 0x4458, + 0x4c00, 0x4c18, 0x4c40, 0x4c54, + 0x4fc0, 0x5010, 0x53c0, 0x5444, + 0x5c00, 0x5c18, 0x5c80, 0x5c90, + 0x5fc0, 0x6000, 0x6400, 0x6428, + 0x6800, 0x6848, 0x684c, 0x6860, + 0x6888, 0x6910, 0x8000 }; + + regs->version = 0; + + memset(p, 0, BNX2_REGDUMP_LEN); + + if (!netif_running(bp->dev)) + return; + + i = 0; + offset = reg_boundaries[0]; + p += offset; + while (offset < BNX2_REGDUMP_LEN) { + *p++ = REG_RD(bp, offset); + offset += 4; + if (offset == reg_boundaries[i + 1]) { + offset = reg_boundaries[i + 2]; + p = (u32 *) (orig_p + offset); + i += 2; + } + } +} + static void bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) { @@ -4853,11 +4990,10 @@ bnx2_nway_reset(struct net_device *dev) msleep(20); spin_lock_bh(&bp->phy_lock); - if (CHIP_NUM(bp) == CHIP_NUM_5706) { - bp->current_interval = SERDES_AN_TIMEOUT; - bp->serdes_an_pending = 1; - mod_timer(&bp->timer, jiffies + bp->current_interval); - } + + bp->current_interval = SERDES_AN_TIMEOUT; + bp->serdes_an_pending = 1; + mod_timer(&bp->timer, jiffies + bp->current_interval); } bnx2_read_phy(bp, MII_BMCR, &bmcr); @@ -4938,7 +5074,7 @@ bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) bp->rx_ticks = (u16) coal->rx_coalesce_usecs; if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; - bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; + bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq; @@ -4979,7 +5115,7 @@ bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) { struct bnx2 *bp = netdev_priv(dev); - ering->rx_max_pending = MAX_RX_DESC_CNT; + ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT; ering->rx_mini_max_pending = 0; ering->rx_jumbo_max_pending = 0; @@ -4996,17 +5132,28 @@ bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) { struct bnx2 *bp = netdev_priv(dev); - if ((ering->rx_pending > MAX_RX_DESC_CNT) || + if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) || (ering->tx_pending > MAX_TX_DESC_CNT) || (ering->tx_pending <= MAX_SKB_FRAGS)) { return -EINVAL; } - bp->rx_ring_size = ering->rx_pending; + if (netif_running(bp->dev)) { + bnx2_netif_stop(bp); + bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); + bnx2_free_skbs(bp); + bnx2_free_mem(bp); + } + + bnx2_set_rx_ring_size(bp, ering->rx_pending); bp->tx_ring_size = ering->tx_pending; if (netif_running(bp->dev)) { - bnx2_netif_stop(bp); + int rc; + + rc = bnx2_alloc_mem(bp); + if (rc) + return rc; bnx2_init_nic(bp); bnx2_netif_start(bp); } @@ -5068,7 +5215,17 @@ bnx2_set_rx_csum(struct net_device *dev, u32 data) return 0; } -#define BNX2_NUM_STATS 45 +static int +bnx2_set_tso(struct net_device *dev, u32 data) +{ + if (data) + dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN; + else + dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN); + return 0; +} + +#define BNX2_NUM_STATS 46 static struct { char string[ETH_GSTRING_LEN]; @@ -5118,11 +5275,12 @@ static struct { { "rx_mac_ctrl_frames" }, { "rx_filtered_packets" }, { "rx_discards" }, + { "rx_fw_discards" }, }; #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4) -static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = { +static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = { STATS_OFFSET32(stat_IfHCInOctets_hi), STATS_OFFSET32(stat_IfHCInBadOctets_hi), STATS_OFFSET32(stat_IfHCOutOctets_hi), @@ -5134,51 +5292,52 @@ static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = { STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi), STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi), STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors), - STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), - STATS_OFFSET32(stat_Dot3StatsFCSErrors), - STATS_OFFSET32(stat_Dot3StatsAlignmentErrors), - STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames), - STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames), - STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), - STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions), - STATS_OFFSET32(stat_Dot3StatsLateCollisions), - STATS_OFFSET32(stat_EtherStatsCollisions), - STATS_OFFSET32(stat_EtherStatsFragments), - STATS_OFFSET32(stat_EtherStatsJabbers), - STATS_OFFSET32(stat_EtherStatsUndersizePkts), - STATS_OFFSET32(stat_EtherStatsOverrsizePkts), - STATS_OFFSET32(stat_EtherStatsPktsRx64Octets), - STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets), - STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets), - STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets), - STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets), - STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets), - STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets), - STATS_OFFSET32(stat_EtherStatsPktsTx64Octets), - STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets), - STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets), - STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets), - STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets), - STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets), - STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets), - STATS_OFFSET32(stat_XonPauseFramesReceived), - STATS_OFFSET32(stat_XoffPauseFramesReceived), - STATS_OFFSET32(stat_OutXonSent), - STATS_OFFSET32(stat_OutXoffSent), - STATS_OFFSET32(stat_MacControlFramesReceived), - STATS_OFFSET32(stat_IfInFramesL2FilterDiscards), - STATS_OFFSET32(stat_IfInMBUFDiscards), + STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), + STATS_OFFSET32(stat_Dot3StatsFCSErrors), + STATS_OFFSET32(stat_Dot3StatsAlignmentErrors), + STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames), + STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames), + STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), + STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions), + STATS_OFFSET32(stat_Dot3StatsLateCollisions), + STATS_OFFSET32(stat_EtherStatsCollisions), + STATS_OFFSET32(stat_EtherStatsFragments), + STATS_OFFSET32(stat_EtherStatsJabbers), + STATS_OFFSET32(stat_EtherStatsUndersizePkts), + STATS_OFFSET32(stat_EtherStatsOverrsizePkts), + STATS_OFFSET32(stat_EtherStatsPktsRx64Octets), + STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets), + STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets), + STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets), + STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets), + STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets), + STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets), + STATS_OFFSET32(stat_EtherStatsPktsTx64Octets), + STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets), + STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets), + STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets), + STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets), + STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets), + STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets), + STATS_OFFSET32(stat_XonPauseFramesReceived), + STATS_OFFSET32(stat_XoffPauseFramesReceived), + STATS_OFFSET32(stat_OutXonSent), + STATS_OFFSET32(stat_OutXoffSent), + STATS_OFFSET32(stat_MacControlFramesReceived), + STATS_OFFSET32(stat_IfInFramesL2FilterDiscards), + STATS_OFFSET32(stat_IfInMBUFDiscards), + STATS_OFFSET32(stat_FwRxDrop), }; /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are * skipped because of errata. - */ + */ static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = { 8,0,8,8,8,8,8,8,8,8, 4,0,4,4,4,4,4,4,4,4, 4,4,4,4,4,4,4,4,4,4, 4,4,4,4,4,4,4,4,4,4, - 4,4,4,4,4, + 4,4,4,4,4,4, }; static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = { @@ -5186,7 +5345,7 @@ static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = { 4,4,4,4,4,4,4,4,4,4, 4,4,4,4,4,4,4,4,4,4, 4,4,4,4,4,4,4,4,4,4, - 4,4,4,4,4, + 4,4,4,4,4,4, }; #define BNX2_NUM_TESTS 6 @@ -5215,6 +5374,8 @@ bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf) memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); if (etest->flags & ETH_TEST_FL_OFFLINE) { + int i; + bnx2_netif_stop(bp); bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG); bnx2_free_skbs(bp); @@ -5239,9 +5400,11 @@ bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf) } /* wait for link up */ - msleep_interruptible(3000); - if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG)) - msleep_interruptible(4000); + for (i = 0; i < 7; i++) { + if (bp->link_up) + break; + msleep_interruptible(1000); + } } if (bnx2_test_nvram(bp) != 0) { @@ -5356,10 +5519,12 @@ bnx2_phys_id(struct net_device *dev, u32 data) return 0; } -static struct ethtool_ops bnx2_ethtool_ops = { +static const struct ethtool_ops bnx2_ethtool_ops = { .get_settings = bnx2_get_settings, .set_settings = bnx2_set_settings, .get_drvinfo = bnx2_get_drvinfo, + .get_regs_len = bnx2_get_regs_len, + .get_regs = bnx2_get_regs, .get_wol = bnx2_get_wol, .set_wol = bnx2_set_wol, .nway_reset = bnx2_nway_reset, @@ -5381,7 +5546,7 @@ static struct ethtool_ops bnx2_ethtool_ops = { .set_sg = ethtool_op_set_sg, #ifdef BCM_TSO .get_tso = ethtool_op_get_tso, - .set_tso = ethtool_op_set_tso, + .set_tso = bnx2_set_tso, #endif .self_test_count = bnx2_self_test_count, .self_test = bnx2_self_test, @@ -5479,11 +5644,49 @@ poll_bnx2(struct net_device *dev) struct bnx2 *bp = netdev_priv(dev); disable_irq(bp->pdev->irq); - bnx2_interrupt(bp->pdev->irq, dev, NULL); + bnx2_interrupt(bp->pdev->irq, dev); enable_irq(bp->pdev->irq); } #endif +static void __devinit +bnx2_get_5709_media(struct bnx2 *bp) +{ + u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL); + u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID; + u32 strap; + + if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) + return; + else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { + bp->phy_flags |= PHY_SERDES_FLAG; + return; + } + + if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) + strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; + else + strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; + + if (PCI_FUNC(bp->pdev->devfn) == 0) { + switch (strap) { + case 0x4: + case 0x5: + case 0x6: + bp->phy_flags |= PHY_SERDES_FLAG; + return; + } + } else { + switch (strap) { + case 0x1: + case 0x2: + case 0x4: + bp->phy_flags |= PHY_SERDES_FLAG; + return; + } + } +} + static int __devinit bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) { @@ -5502,20 +5705,20 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) /* enable device (incl. PCI PM wakeup), and bus-mastering */ rc = pci_enable_device(pdev); if (rc) { - printk(KERN_ERR PFX "Cannot enable PCI device, aborting."); + dev_err(&pdev->dev, "Cannot enable PCI device, aborting."); goto err_out; } if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { - printk(KERN_ERR PFX "Cannot find PCI device base address, " - "aborting.\n"); + dev_err(&pdev->dev, + "Cannot find PCI device base address, aborting.\n"); rc = -ENODEV; goto err_out_disable; } rc = pci_request_regions(pdev, DRV_MODULE_NAME); if (rc) { - printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n"); + dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n"); goto err_out_disable; } @@ -5523,15 +5726,8 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); if (bp->pm_cap == 0) { - printk(KERN_ERR PFX "Cannot find power management capability, " - "aborting.\n"); - rc = -EIO; - goto err_out_release; - } - - bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); - if (bp->pcix_cap == 0) { - printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n"); + dev_err(&pdev->dev, + "Cannot find power management capability, aborting.\n"); rc = -EIO; goto err_out_release; } @@ -5539,14 +5735,14 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) { bp->flags |= USING_DAC_FLAG; if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) { - printk(KERN_ERR PFX "pci_set_consistent_dma_mask " - "failed, aborting.\n"); + dev_err(&pdev->dev, + "pci_set_consistent_dma_mask failed, aborting.\n"); rc = -EIO; goto err_out_release; } } else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) { - printk(KERN_ERR PFX "System does not support DMA, aborting.\n"); + dev_err(&pdev->dev, "System does not support DMA, aborting.\n"); rc = -EIO; goto err_out_release; } @@ -5555,18 +5751,17 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->pdev = pdev; spin_lock_init(&bp->phy_lock); - spin_lock_init(&bp->tx_lock); - INIT_WORK(&bp->reset_task, bnx2_reset_task, bp); + INIT_WORK(&bp->reset_task, bnx2_reset_task); dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0); - mem_len = MB_GET_CID_ADDR(17); + mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1); dev->mem_end = dev->mem_start + mem_len; dev->irq = pdev->irq; bp->regview = ioremap_nocache(dev->base_addr, mem_len); if (!bp->regview) { - printk(KERN_ERR PFX "Cannot map register space, aborting.\n"); + dev_err(&pdev->dev, "Cannot map register space, aborting.\n"); rc = -ENOMEM; goto err_out_release; } @@ -5583,6 +5778,16 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->chip_id = REG_RD(bp, BNX2_MISC_ID); + if (CHIP_NUM(bp) != CHIP_NUM_5709) { + bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); + if (bp->pcix_cap == 0) { + dev_err(&pdev->dev, + "Cannot find PCIX capability, aborting.\n"); + rc = -EIO; + goto err_out_unmap; + } + } + /* Get bus information. */ reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS); if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { @@ -5591,7 +5796,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->flags |= PCIX_FLAG; clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); - + clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; switch (clkreg) { case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: @@ -5638,8 +5843,8 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) && !(bp->flags & PCIX_FLAG)) { - printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, " - "aborting.\n"); + dev_err(&pdev->dev, + "5706 A1 can only be used in a PCIX bus, aborting.\n"); goto err_out_unmap; } @@ -5648,9 +5853,11 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE); if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) == - BNX2_SHM_HDR_SIGNATURE_SIG) - bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0); - else + BNX2_SHM_HDR_SIGNATURE_SIG) { + u32 off = PCI_FUNC(pdev->devfn) << 2; + + bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0 + off); + } else bp->shmem_base = HOST_VIEW_SHMEM_BASE; /* Get the permanent MAC address. First we need to make sure the @@ -5660,7 +5867,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != BNX2_DEV_INFO_SIGNATURE_MAGIC) { - printk(KERN_ERR PFX "Firmware not running, aborting.\n"); + dev_err(&pdev->dev, "Firmware not running, aborting.\n"); rc = -ENODEV; goto err_out_unmap; } @@ -5678,7 +5885,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->mac_addr[5] = (u8) reg; bp->tx_ring_size = MAX_TX_DESC_CNT; - bp->rx_ring_size = 100; + bnx2_set_rx_ring_size(bp, 255); bp->rx_csum = 1; @@ -5688,7 +5895,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->tx_quick_cons_trip = 20; bp->tx_ticks_int = 80; bp->tx_ticks = 80; - + bp->rx_quick_cons_trip_int = 6; bp->rx_quick_cons_trip = 6; bp->rx_ticks_int = 18; @@ -5702,19 +5909,29 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->phy_addr = 1; /* Disable WOL support if we are running on a SERDES chip. */ - if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) { + if (CHIP_NUM(bp) == CHIP_NUM_5709) + bnx2_get_5709_media(bp); + else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) bp->phy_flags |= PHY_SERDES_FLAG; + + if (bp->phy_flags & PHY_SERDES_FLAG) { bp->flags |= NO_WOL_FLAG; - if (CHIP_NUM(bp) == CHIP_NUM_5708) { + if (CHIP_NUM(bp) != CHIP_NUM_5706) { bp->phy_addr = 2; reg = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG); if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG; } - } + } else if (CHIP_NUM(bp) == CHIP_NUM_5706 || + CHIP_NUM(bp) == CHIP_NUM_5708) + bp->phy_flags |= PHY_CRC_FIX_FLAG; + else if (CHIP_ID(bp) == CHIP_ID_5709_A0) + bp->phy_flags |= PHY_DIS_EARLY_DAC_FLAG; - if (CHIP_NUM(bp) == CHIP_NUM_5708) + if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || + (CHIP_ID(bp) == CHIP_ID_5708_B0) || + (CHIP_ID(bp) == CHIP_ID_5708_B1)) bp->flags |= NO_WOL_FLAG; if (CHIP_ID(bp) == CHIP_ID_5706_A0) { @@ -5729,6 +5946,34 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->cmd_ticks_int = bp->cmd_ticks; } + /* Disable MSI on 5706 if AMD 8132 bridge is found. + * + * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes + * with byte enables disabled on the unused 32-bit word. This is legal + * but causes problems on the AMD 8132 which will eventually stop + * responding after a while. + * + * AMD believes this incompatibility is unique to the 5706, and + * prefers to locally disable MSI rather than globally disabling it + * using pci_msi_quirk. + */ + if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) { + struct pci_dev *amd_8132 = NULL; + + while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_8132_BRIDGE, + amd_8132))) { + u8 rev; + + pci_read_config_byte(amd_8132, PCI_REVISION_ID, &rev); + if (rev >= 0x10 && rev <= 0x13) { + disable_msi = 1; + pci_dev_put(amd_8132); + break; + } + } + } + bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; bp->req_line_speed = 0; if (bp->phy_flags & PHY_SERDES_FLAG) { @@ -5820,7 +6065,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) #endif if ((rc = register_netdev(dev))) { - printk(KERN_ERR PFX "Cannot register net device\n"); + dev_err(&pdev->dev, "Cannot register net device\n"); if (bp->regview) iounmap(bp->regview); pci_release_regions(pdev); @@ -5860,7 +6105,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; #endif #ifdef BCM_TSO - dev->features |= NETIF_F_TSO; + dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN; #endif netif_carrier_off(bp->dev); @@ -5897,11 +6142,12 @@ bnx2_suspend(struct pci_dev *pdev, pm_message_t state) if (!netif_running(dev)) return 0; + flush_scheduled_work(); bnx2_netif_stop(bp); netif_device_detach(dev); del_timer_sync(&bp->timer); if (bp->flags & NO_WOL_FLAG) - reset_code = BNX2_DRV_MSG_CODE_UNLOAD; + reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN; else if (bp->wol) reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; else @@ -5939,7 +6185,7 @@ static struct pci_driver bnx2_pci_driver = { static int __init bnx2_init(void) { - return pci_module_init(&bnx2_pci_driver); + return pci_register_driver(&bnx2_pci_driver); } static void __exit bnx2_cleanup(void)