X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fnet%2Fixgb%2Fixgb_ee.h;h=5c473572f7fdc33f6ce5227d8aec196f69e26920;hb=d939d46ba7caa14e960be18e18f5c07be8806d7a;hp=f19bb548671b0a93057b4cb4cd68ad455092ae7d;hpb=86090fcac5e27b630656fe3d963a6b80e26dac44;p=linux-2.6.git

diff --git a/drivers/net/ixgb/ixgb_ee.h b/drivers/net/ixgb/ixgb_ee.h
index f19bb5486..5c473572f 100644
--- a/drivers/net/ixgb/ixgb_ee.h
+++ b/drivers/net/ixgb/ixgb_ee.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   
-  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
+  Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
   
   This program is free software; you can redistribute it and/or modify it 
   under the terms of the GNU General Public License as published by the Free 
@@ -23,6 +23,7 @@
   Contact Information:
   Linux NICS <linux.nics@intel.com>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
 *******************************************************************************/
 
 #ifndef _IXGB_EE_H_
@@ -33,9 +34,9 @@
 #define IXGB_ETH_LENGTH_OF_ADDRESS   6
 
 /* EEPROM Commands */
-#define EEPROM_READ_OPCODE  0x6		/* EERPOM read opcode */
-#define EEPROM_WRITE_OPCODE 0x5		/* EERPOM write opcode */
-#define EEPROM_ERASE_OPCODE 0x7		/* EERPOM erase opcode */
+#define EEPROM_READ_OPCODE  0x6	/* EERPOM read opcode */
+#define EEPROM_WRITE_OPCODE 0x5	/* EERPOM write opcode */
+#define EEPROM_ERASE_OPCODE 0x7	/* EERPOM erase opcode */
 #define EEPROM_EWEN_OPCODE  0x13	/* EERPOM erase/write enable */
 #define EEPROM_EWDS_OPCODE  0x10	/* EERPOM erast/write disable */
 
@@ -73,32 +74,32 @@
 
 /* EEPROM structure */
 struct ixgb_ee_map_type {
-	u8 mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS];
-	u16 compatibility;
-	u16 reserved1[4];
-	u32 pba_number;
-	u16 init_ctrl_reg_1;
-	u16 subsystem_id;
-	u16 subvendor_id;
-	u16 device_id;
-	u16 vendor_id;
-	u16 init_ctrl_reg_2;
-	u16 oem_reserved[16];
-	u16 swdpins_reg;
-	u16 circuit_ctrl_reg;
-	u8 d3_power;
-	u8 d0_power;
-	u16 reserved2[28];
-	u16 checksum;
+	uint8_t mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS];
+	uint16_t compatibility;
+	uint16_t reserved1[4];
+	uint32_t pba_number;
+	uint16_t init_ctrl_reg_1;
+	uint16_t subsystem_id;
+	uint16_t subvendor_id;
+	uint16_t device_id;
+	uint16_t vendor_id;
+	uint16_t init_ctrl_reg_2;
+	uint16_t oem_reserved[16];
+	uint16_t swdpins_reg;
+	uint16_t circuit_ctrl_reg;
+	uint8_t d3_power;
+	uint8_t d0_power;
+	uint16_t reserved2[28];
+	uint16_t checksum;
 };
 
 /* EEPROM Functions */
-u16 ixgb_read_eeprom(struct ixgb_hw *hw, u16 reg);
+uint16_t ixgb_read_eeprom(struct ixgb_hw *hw, uint16_t reg);
 
 boolean_t ixgb_validate_eeprom_checksum(struct ixgb_hw *hw);
 
 void ixgb_update_eeprom_checksum(struct ixgb_hw *hw);
 
-void ixgb_write_eeprom(struct ixgb_hw *hw, u16 reg, u16 data);
+void ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t reg, uint16_t data);
 
 #endif				/* IXGB_EE_H */