X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fnet%2Fixgb%2Fixgb_hw.h;h=c6898ca6179f05dffd3e60e5f5ccd9fc70cda207;hb=78a6196531f0fe10aae05a9bc4c2701df614ac3d;hp=2129ae9f85710eb546725d1bbe5fd5d943f19193;hpb=86090fcac5e27b630656fe3d963a6b80e26dac44;p=linux-2.6.git diff --git a/drivers/net/ixgb/ixgb_hw.h b/drivers/net/ixgb/ixgb_hw.h index 2129ae9f8..c6898ca61 100644 --- a/drivers/net/ixgb/ixgb_hw.h +++ b/drivers/net/ixgb/ixgb_hw.h @@ -1,7 +1,7 @@ /******************************************************************************* - Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved. + Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free @@ -23,6 +23,7 @@ Contact Information: Linux NICS Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + *******************************************************************************/ #ifndef _IXGB_HW_H_ @@ -37,6 +38,21 @@ typedef enum { ixgb_num_macs } ixgb_mac_type; +/* Types of physical layer modules */ +typedef enum { + ixgb_phy_type_unknown = 0, + ixgb_phy_type_g6005, /* 850nm, MM fiber, XPAK transceiver */ + ixgb_phy_type_g6104, /* 1310nm, SM fiber, XPAK transceiver */ + ixgb_phy_type_txn17201, /* 850nm, MM fiber, XPAK transceiver */ + ixgb_phy_type_txn17401 /* 1310nm, SM fiber, XENPAK transceiver */ +} ixgb_phy_type; + +/* XPAK transceiver vendors, for the SR adapters */ +typedef enum { + ixgb_xpak_vendor_intel, + ixgb_xpak_vendor_infineon +} ixgb_xpak_vendor; + /* Media Types */ typedef enum { ixgb_media_type_unknown = 0, @@ -84,6 +100,9 @@ typedef enum { #define SPEED_10000 10000 #define FULL_DUPLEX 2 +#define MIN_NUMBER_OF_DESCRIPTORS 8 +#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 /* 13 bits in RDLEN/TDLEN, 128B aligned */ + #define IXGB_DELAY_BEFORE_RESET 10 /* allow 10ms after idling rx/tx units */ #define IXGB_DELAY_AFTER_RESET 1 /* allow 1ms after the reset */ #define IXGB_DELAY_AFTER_EE_RESET 10 /* allow 10ms after the EEPROM reset */ @@ -225,6 +244,9 @@ typedef enum { /* CTRL0 Bit Masks */ #define IXGB_CTRL0_LRST 0x00000008 #define IXGB_CTRL0_JFE 0x00000010 +#define IXGB_CTRL0_XLE 0x00000020 +#define IXGB_CTRL0_MDCS 0x00000040 +#define IXGB_CTRL0_CMDC 0x00000080 #define IXGB_CTRL0_SDP0 0x00040000 #define IXGB_CTRL0_SDP1 0x00080000 #define IXGB_CTRL0_SDP2 0x00100000 @@ -239,14 +261,36 @@ typedef enum { #define IXGB_CTRL0_VME 0x40000000 /* CTRL1 Bit Masks */ - +#define IXGB_CTRL1_GPI0_EN 0x00000001 +#define IXGB_CTRL1_GPI1_EN 0x00000002 +#define IXGB_CTRL1_GPI2_EN 0x00000004 +#define IXGB_CTRL1_GPI3_EN 0x00000008 +#define IXGB_CTRL1_SDP4 0x00000010 +#define IXGB_CTRL1_SDP5 0x00000020 +#define IXGB_CTRL1_SDP6 0x00000040 +#define IXGB_CTRL1_SDP7 0x00000080 +#define IXGB_CTRL1_SDP4_DIR 0x00000100 +#define IXGB_CTRL1_SDP5_DIR 0x00000200 +#define IXGB_CTRL1_SDP6_DIR 0x00000400 +#define IXGB_CTRL1_SDP7_DIR 0x00000800 #define IXGB_CTRL1_EE_RST 0x00002000 +#define IXGB_CTRL1_RO_DIS 0x00020000 +#define IXGB_CTRL1_PCIXHM_MASK 0x00C00000 +#define IXGB_CTRL1_PCIXHM_1_2 0x00000000 +#define IXGB_CTRL1_PCIXHM_5_8 0x00400000 +#define IXGB_CTRL1_PCIXHM_3_4 0x00800000 +#define IXGB_CTRL1_PCIXHM_7_8 0x00C00000 /* STATUS Bit Masks */ #define IXGB_STATUS_LU 0x00000002 - +#define IXGB_STATUS_AIP 0x00000004 #define IXGB_STATUS_TXOFF 0x00000010 - +#define IXGB_STATUS_XAUIME 0x00000020 +#define IXGB_STATUS_RES 0x00000040 +#define IXGB_STATUS_RIS 0x00000080 +#define IXGB_STATUS_RIE 0x00000100 +#define IXGB_STATUS_RLF 0x00000200 +#define IXGB_STATUS_RRF 0x00000400 #define IXGB_STATUS_PCI_SPD 0x00000800 #define IXGB_STATUS_BUS64 0x00001000 #define IXGB_STATUS_PCIX_MODE 0x00002000 @@ -254,31 +298,52 @@ typedef enum { #define IXGB_STATUS_PCIX_SPD_66 0x00000000 #define IXGB_STATUS_PCIX_SPD_100 0x00004000 #define IXGB_STATUS_PCIX_SPD_133 0x00008000 +#define IXGB_STATUS_REV_ID_MASK 0x000F0000 +#define IXGB_STATUS_REV_ID_SHIFT 16 /* EECD Bit Masks */ #define IXGB_EECD_SK 0x00000001 #define IXGB_EECD_CS 0x00000002 #define IXGB_EECD_DI 0x00000004 #define IXGB_EECD_DO 0x00000008 +#define IXGB_EECD_FWE_MASK 0x00000030 +#define IXGB_EECD_FWE_DIS 0x00000010 +#define IXGB_EECD_FWE_EN 0x00000020 /* MFS */ #define IXGB_MFS_SHIFT 16 /* Interrupt Register Bit Masks (used for ICR, ICS, IMS, and IMC) */ #define IXGB_INT_TXDW 0x00000001 +#define IXGB_INT_TXQE 0x00000002 #define IXGB_INT_LSC 0x00000004 #define IXGB_INT_RXSEQ 0x00000008 #define IXGB_INT_RXDMT0 0x00000010 #define IXGB_INT_RXO 0x00000040 #define IXGB_INT_RXT0 0x00000080 +#define IXGB_INT_AUTOSCAN 0x00000200 +#define IXGB_INT_GPI0 0x00000800 +#define IXGB_INT_GPI1 0x00001000 +#define IXGB_INT_GPI2 0x00002000 +#define IXGB_INT_GPI3 0x00004000 /* RCTL Bit Masks */ #define IXGB_RCTL_RXEN 0x00000002 +#define IXGB_RCTL_SBP 0x00000004 #define IXGB_RCTL_UPE 0x00000008 #define IXGB_RCTL_MPE 0x00000010 +#define IXGB_RCTL_RDMTS_MASK 0x00000300 #define IXGB_RCTL_RDMTS_1_2 0x00000000 +#define IXGB_RCTL_RDMTS_1_4 0x00000100 +#define IXGB_RCTL_RDMTS_1_8 0x00000200 +#define IXGB_RCTL_MO_MASK 0x00003000 +#define IXGB_RCTL_MO_47_36 0x00000000 +#define IXGB_RCTL_MO_46_35 0x00001000 +#define IXGB_RCTL_MO_45_34 0x00002000 +#define IXGB_RCTL_MO_43_32 0x00003000 #define IXGB_RCTL_MO_SHIFT 12 #define IXGB_RCTL_BAM 0x00008000 +#define IXGB_RCTL_BSIZE_MASK 0x00030000 #define IXGB_RCTL_BSIZE_2048 0x00000000 #define IXGB_RCTL_BSIZE_4096 0x00010000 #define IXGB_RCTL_BSIZE_8192 0x00020000 @@ -286,27 +351,48 @@ typedef enum { #define IXGB_RCTL_VFE 0x00040000 #define IXGB_RCTL_CFIEN 0x00080000 #define IXGB_RCTL_CFI 0x00100000 +#define IXGB_RCTL_RPDA_MASK 0x00600000 +#define IXGB_RCTL_RPDA_MC_MAC 0x00000000 +#define IXGB_RCTL_MC_ONLY 0x00400000 #define IXGB_RCTL_CFF 0x00800000 #define IXGB_RCTL_SECRC 0x04000000 +#define IXGB_RDT_FPDB 0x80000000 + +#define IXGB_RCTL_IDLE_RX_UNIT 0 /* FCRTL Bit Masks */ #define IXGB_FCRTL_XONE 0x80000000 /* RXDCTL Bit Masks */ +#define IXGB_RXDCTL_PTHRESH_MASK 0x000001FF #define IXGB_RXDCTL_PTHRESH_SHIFT 0 +#define IXGB_RXDCTL_HTHRESH_MASK 0x0003FE00 #define IXGB_RXDCTL_HTHRESH_SHIFT 9 +#define IXGB_RXDCTL_WTHRESH_MASK 0x07FC0000 #define IXGB_RXDCTL_WTHRESH_SHIFT 18 /* RAIDC Bit Masks */ +#define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F +#define IXGB_RAIDC_DELAY_MASK 0x000FF800 #define IXGB_RAIDC_DELAY_SHIFT 11 +#define IXGB_RAIDC_POLL_MASK 0x1FF00000 #define IXGB_RAIDC_POLL_SHIFT 20 #define IXGB_RAIDC_RXT_GATE 0x40000000 #define IXGB_RAIDC_EN 0x80000000 +#define IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND 1220 +#define IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND 244 +#define IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND 122 +#define IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND 61 + /* RXCSUM Bit Masks */ +#define IXGB_RXCSUM_IPOFL 0x00000100 #define IXGB_RXCSUM_TUOFL 0x00000200 /* RAH Bit Masks */ +#define IXGB_RAH_ASEL_MASK 0x00030000 +#define IXGB_RAH_ASEL_DEST 0x00000000 +#define IXGB_RAH_ASEL_SRC 0x00010000 #define IXGB_RAH_AV 0x80000000 /* TCTL Bit Masks */ @@ -314,64 +400,145 @@ typedef enum { #define IXGB_TCTL_TXEN 0x00000002 #define IXGB_TCTL_TPDE 0x00000004 +#define IXGB_TCTL_IDLE_TX_UNIT 0 + /* TXDCTL Bit Masks */ +#define IXGB_TXDCTL_PTHRESH_MASK 0x0000007F +#define IXGB_TXDCTL_HTHRESH_MASK 0x00007F00 #define IXGB_TXDCTL_HTHRESH_SHIFT 8 +#define IXGB_TXDCTL_WTHRESH_MASK 0x007F0000 +#define IXGB_TXDCTL_WTHRESH_SHIFT 16 /* TSPMT Bit Masks */ +#define IXGB_TSPMT_TSMT_MASK 0x0000FFFF +#define IXGB_TSPMT_TSPBP_MASK 0xFFFF0000 +#define IXGB_TSPMT_TSPBP_SHIFT 16 /* PAP Bit Masks */ +#define IXGB_PAP_TXPC_MASK 0x0000FFFF +#define IXGB_PAP_TXPV_MASK 0x000F0000 +#define IXGB_PAP_TXPV_10G 0x00000000 +#define IXGB_PAP_TXPV_1G 0x00010000 +#define IXGB_PAP_TXPV_2G 0x00020000 +#define IXGB_PAP_TXPV_3G 0x00030000 +#define IXGB_PAP_TXPV_4G 0x00040000 +#define IXGB_PAP_TXPV_5G 0x00050000 +#define IXGB_PAP_TXPV_6G 0x00060000 +#define IXGB_PAP_TXPV_7G 0x00070000 +#define IXGB_PAP_TXPV_8G 0x00080000 +#define IXGB_PAP_TXPV_9G 0x00090000 +#define IXGB_PAP_TXPV_WAN 0x000F0000 /* PCSC1 Bit Masks */ +#define IXGB_PCSC1_LOOPBACK 0x00004000 /* PCSC2 Bit Masks */ +#define IXGB_PCSC2_PCS_TYPE_MASK 0x00000003 +#define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001 /* PCSS1 Bit Masks */ +#define IXGB_PCSS1_LOCAL_FAULT 0x00000080 +#define IXGB_PCSS1_RX_LINK_STATUS 0x00000004 /* PCSS2 Bit Masks */ +#define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000 +#define IXGB_PCSS2_DEV_PRES 0x00004000 +#define IXGB_PCSS2_TX_LF 0x00000800 +#define IXGB_PCSS2_RX_LF 0x00000400 +#define IXGB_PCSS2_10GBW 0x00000004 +#define IXGB_PCSS2_10GBX 0x00000002 +#define IXGB_PCSS2_10GBR 0x00000001 /* XPCSS Bit Masks */ #define IXGB_XPCSS_ALIGN_STATUS 0x00001000 +#define IXGB_XPCSS_PATTERN_TEST 0x00000800 +#define IXGB_XPCSS_LANE_3_SYNC 0x00000008 +#define IXGB_XPCSS_LANE_2_SYNC 0x00000004 +#define IXGB_XPCSS_LANE_1_SYNC 0x00000002 +#define IXGB_XPCSS_LANE_0_SYNC 0x00000001 /* XPCSTC Bit Masks */ +#define IXGB_XPCSTC_BERT_TRIG 0x00200000 +#define IXGB_XPCSTC_BERT_SST 0x00100000 +#define IXGB_XPCSTC_BERT_PSZ_MASK 0x000C0000 +#define IXGB_XPCSTC_BERT_PSZ_SHIFT 17 +#define IXGB_XPCSTC_BERT_PSZ_INF 0x00000003 +#define IXGB_XPCSTC_BERT_PSZ_68 0x00000001 +#define IXGB_XPCSTC_BERT_PSZ_1028 0x00000000 /* MSCA bit Masks */ /* New Protocol Address */ +#define IXGB_MSCA_NP_ADDR_MASK 0x0000FFFF #define IXGB_MSCA_NP_ADDR_SHIFT 0 /* Either Device Type or Register Address,depending on ST_CODE */ +#define IXGB_MSCA_DEV_TYPE_MASK 0x001F0000 #define IXGB_MSCA_DEV_TYPE_SHIFT 16 +#define IXGB_MSCA_PHY_ADDR_MASK 0x03E00000 #define IXGB_MSCA_PHY_ADDR_SHIFT 21 +#define IXGB_MSCA_OP_CODE_MASK 0x0C000000 +/* OP_CODE == 00, Address cycle, New Protocol */ +/* OP_CODE == 01, Write operation */ +/* OP_CODE == 10, Read operation */ +/* OP_CODE == 11, Read, auto increment, New Protocol */ #define IXGB_MSCA_ADDR_CYCLE 0x00000000 #define IXGB_MSCA_WRITE 0x04000000 #define IXGB_MSCA_READ 0x08000000 +#define IXGB_MSCA_READ_AUTOINC 0x0C000000 +#define IXGB_MSCA_OP_CODE_SHIFT 26 +#define IXGB_MSCA_ST_CODE_MASK 0x30000000 +/* ST_CODE == 00, New Protocol */ +/* ST_CODE == 01, Old Protocol */ +#define IXGB_MSCA_NEW_PROTOCOL 0x00000000 +#define IXGB_MSCA_OLD_PROTOCOL 0x10000000 +#define IXGB_MSCA_ST_CODE_SHIFT 28 /* Initiate command, self-clearing when command completes */ #define IXGB_MSCA_MDI_COMMAND 0x40000000 /*MDI In Progress Enable. */ +#define IXGB_MSCA_MDI_IN_PROG_EN 0x80000000 /* MSRWD bit masks */ +#define IXGB_MSRWD_WRITE_DATA_MASK 0x0000FFFF +#define IXGB_MSRWD_WRITE_DATA_SHIFT 0 +#define IXGB_MSRWD_READ_DATA_MASK 0xFFFF0000 #define IXGB_MSRWD_READ_DATA_SHIFT 16 -/* Definitions for the TXN17401 devices on the MDIO bus. */ +/* Definitions for the optics devices on the MDIO bus. */ #define IXGB_PHY_ADDRESS 0x0 /* Single PHY, multiple "Devices" */ -/* Five bit Device IDs */ -#define TXN17401_PMA_PMD_DID 0x01 -#define TXN17401_PCS_DID 0x03 -#define TXN17401_XGXS_DID 0x04 +/* Standard five-bit Device IDs. See IEEE 802.3ae, clause 45 */ +#define MDIO_PMA_PMD_DID 0x01 +#define MDIO_WIS_DID 0x02 +#define MDIO_PCS_DID 0x03 +#define MDIO_XGXS_DID 0x04 -/* PMA/PMD registers and bit definitions. */ +/* Standard PMA/PMD registers and bit definitions. */ /* Note: This is a very limited set of definitions, */ /* only implemented features are defined. */ -#define TXN17401_PMA_PMD_CR1 0x0000 +#define MDIO_PMA_PMD_CR1 0x0000 +#define MDIO_PMA_PMD_CR1_RESET 0x8000 + +#define MDIO_PMA_PMD_XPAK_VENDOR_NAME 0x803A /* XPAK/XENPAK devices only */ -#define TXN17401_PMA_PMD_CR1_RESET 0x8000 +/* Vendor-specific MDIO registers */ +#define G6XXX_PMA_PMD_VS1 0xC001 /* Vendor-specific register */ +#define G6XXX_XGXS_XAUI_VS2 0x18 /* Vendor-specific register */ +#define G6XXX_PMA_PMD_VS1_PLL_RESET 0x80 +#define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET 0x00 +#define G6XXX_XGXS_XAUI_VS2_INPUT_MASK 0x0F /* XAUI lanes synchronized */ + +/* Layout of a single receive descriptor. The controller assumes that this + * structure is packed into 16 bytes, which is a safe assumption with most + * compilers. However, some compilers may insert padding between the fields, + * in which case the structure must be packed in some compiler-specific + * manner. */ struct ixgb_rx_desc { uint64_t buff_addr; - u16 length; - u16 reserved; - u8 status; - u8 errors; - u16 special; + uint16_t length; + uint16_t reserved; + uint8_t status; + uint8_t errors; + uint16_t special; }; #define IXGB_RX_DESC_STATUS_DD 0x01 @@ -379,23 +546,38 @@ struct ixgb_rx_desc { #define IXGB_RX_DESC_STATUS_IXSM 0x04 #define IXGB_RX_DESC_STATUS_VP 0x08 #define IXGB_RX_DESC_STATUS_TCPCS 0x20 +#define IXGB_RX_DESC_STATUS_IPCS 0x40 +#define IXGB_RX_DESC_STATUS_PIF 0x80 #define IXGB_RX_DESC_ERRORS_CE 0x01 #define IXGB_RX_DESC_ERRORS_SE 0x02 #define IXGB_RX_DESC_ERRORS_P 0x08 #define IXGB_RX_DESC_ERRORS_TCPE 0x20 +#define IXGB_RX_DESC_ERRORS_IPE 0x40 #define IXGB_RX_DESC_ERRORS_RXE 0x80 #define IXGB_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ - +#define IXGB_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ +#define IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ + +/* Layout of a single transmit descriptor. The controller assumes that this + * structure is packed into 16 bytes, which is a safe assumption with most + * compilers. However, some compilers may insert padding between the fields, + * in which case the structure must be packed in some compiler-specific + * manner. */ struct ixgb_tx_desc { uint64_t buff_addr; - u32 cmd_type_len; - u8 status; - u8 popts; - u16 vlan; + uint32_t cmd_type_len; + uint8_t status; + uint8_t popts; + uint16_t vlan; }; +#define IXGB_TX_DESC_LENGTH_MASK 0x000FFFFF +#define IXGB_TX_DESC_TYPE_MASK 0x00F00000 +#define IXGB_TX_DESC_TYPE_SHIFT 20 +#define IXGB_TX_DESC_CMD_MASK 0xFF000000 +#define IXGB_TX_DESC_CMD_SHIFT 24 #define IXGB_TX_DESC_CMD_EOP 0x01000000 #define IXGB_TX_DESC_CMD_TSE 0x04000000 #define IXGB_TX_DESC_CMD_RS 0x08000000 @@ -408,18 +590,19 @@ struct ixgb_tx_desc { #define IXGB_TX_DESC_POPTS_IXSM 0x01 #define IXGB_TX_DESC_POPTS_TXSM 0x02 +#define IXGB_TX_DESC_SPECIAL_PRI_SHIFT IXGB_RX_DESC_SPECIAL_PRI_SHIFT /* Priority is in upper 3 of 16 */ struct ixgb_context_desc { - u8 ipcss; - u8 ipcso; - u16 ipcse; - u8 tucss; - u8 tucso; - u16 tucse; - u32 cmd_type_len; - u8 status; - u8 hdr_len; - u16 mss; + uint8_t ipcss; + uint8_t ipcso; + uint16_t ipcse; + uint8_t tucss; + uint8_t tucso; + uint16_t tucse; + uint32_t cmd_type_len; + uint8_t status; + uint8_t hdr_len; + uint16_t mss; }; #define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000 @@ -430,11 +613,14 @@ struct ixgb_context_desc { #define IXGB_CONTEXT_DESC_TYPE 0x00000000 +#define IXGB_CONTEXT_DESC_STATUS_DD 0x01 + /* Filters */ #define IXGB_RAR_ENTRIES 16 /* Number of entries in Rx Address array */ #define IXGB_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ #define IXGB_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ +#define IXGB_MEMORY_REGISTER_BASE_ADDRESS 0 #define ENET_HEADER_SIZE 14 #define ENET_FCS_LENGTH 4 #define IXGB_MAX_NUM_MULTICAST_ADDRESSES 128 @@ -443,29 +629,46 @@ struct ixgb_context_desc { #define IXGB_MAX_JUMBO_FRAME_SIZE 0x3F00 /* Phy Addresses */ +#define IXGB_OPTICAL_PHY_ADDR 0x0 /* Optical Module phy address */ +#define IXGB_XAUII_PHY_ADDR 0x1 /* Xauii transceiver phy address */ +#define IXGB_DIAG_PHY_ADDR 0x1F /* Diagnostic Device phy address */ + +/* This structure takes a 64k flash and maps it for identification commands */ +struct ixgb_flash_buffer { + uint8_t manufacturer_id; + uint8_t device_id; + uint8_t filler1[0x2AA8]; + uint8_t cmd2; + uint8_t filler2[0x2AAA]; + uint8_t cmd1; + uint8_t filler3[0xAAAA]; +}; /* * This is a little-endian specific check. */ #define IS_MULTICAST(Address) \ - (boolean_t)(((u8 *)(Address))[0] & ((u8)0x01)) + (boolean_t)(((uint8_t *)(Address))[0] & ((uint8_t)0x01)) /* * Check whether an address is broadcast. */ #define IS_BROADCAST(Address) \ - ((((u8 *)(Address))[0] == ((u8)0xff)) && (((u8 *)(Address))[1] == ((u8)0xff))) + ((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && (((uint8_t *)(Address))[1] == ((uint8_t)0xff))) /* Flow control parameters */ struct ixgb_fc { - u32 high_water; /* Flow Control High-water */ - u32 low_water; /* Flow Control Low-water */ - u16 pause_time; /* Flow Control Pause timer */ + uint32_t high_water; /* Flow Control High-water */ + uint32_t low_water; /* Flow Control Low-water */ + uint16_t pause_time; /* Flow Control Pause timer */ boolean_t send_xon; /* Flow control send XON */ ixgb_fc_type type; /* Type of flow control */ }; /* The historical defaults for the flow control values are given below. */ +#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ +#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ +#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ /* Phy definitions */ #define IXGB_MAX_PHY_REG_ADDRESS 0xFFFF @@ -480,32 +683,40 @@ struct ixgb_bus { }; struct ixgb_hw { - u8 *hw_addr; /* Base Address of the hardware */ + uint8_t *hw_addr; /* Base Address of the hardware */ void *back; /* Pointer to OS-dependent struct */ struct ixgb_fc fc; /* Flow control parameters */ struct ixgb_bus bus; /* Bus parameters */ - u32 phy_id; /* Phy Identifier */ - u32 phy_addr; /* XGMII address of Phy */ + uint32_t phy_id; /* Phy Identifier */ + uint32_t phy_addr; /* XGMII address of Phy */ ixgb_mac_type mac_type; /* Identifier for MAC controller */ - u32 max_frame_size; /* Maximum frame size supported */ - u32 mc_filter_type; /* Multicast filter hash type */ - u32 num_mc_addrs; /* Number of current Multicast addrs */ - u8 curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS]; /* Individual address currently programmed in MAC */ - u32 num_tx_desc; /* Number of Transmit descriptors */ - u32 num_rx_desc; /* Number of Receive descriptors */ - u32 rx_buffer_size; /* Size of Receive buffer */ + ixgb_phy_type phy_type; /* Transceiver/phy identifier */ + uint32_t max_frame_size; /* Maximum frame size supported */ + uint32_t mc_filter_type; /* Multicast filter hash type */ + uint32_t num_mc_addrs; /* Number of current Multicast addrs */ + uint8_t curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS]; /* Individual address currently programmed in MAC */ + uint32_t num_tx_desc; /* Number of Transmit descriptors */ + uint32_t num_rx_desc; /* Number of Receive descriptors */ + uint32_t rx_buffer_size; /* Size of Receive buffer */ boolean_t link_up; /* TRUE if link is valid */ boolean_t adapter_stopped; /* State of adapter */ - u16 device_id; /* device id from PCI configuration space */ - u16 vendor_id; /* vendor id from PCI configuration space */ - u16 subsystem_vendor_id; /* subsystem vendor id from PCI configuration space */ - u16 subsystem_id; /* subsystem id from PCI configuration space */ - u16 eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init time */ - uint64_t io_base; /* Our I/O mapped location */ - u32 lastLFC; - u32 lastRFC; + uint16_t device_id; /* device id from PCI configuration space */ + uint16_t vendor_id; /* vendor id from PCI configuration space */ + uint8_t revision_id; /* revision id from PCI configuration space */ + uint16_t subsystem_vendor_id; /* subsystem vendor id from PCI configuration space */ + uint16_t subsystem_id; /* subsystem id from PCI configuration space */ + uint32_t bar0; /* Base Address registers */ + uint32_t bar1; + uint32_t bar2; + uint32_t bar3; + uint16_t pci_cmd_word; /* PCI command register id from PCI configuration space */ + uint16_t eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init time */ + unsigned long io_base; /* Our I/O mapped location */ + uint32_t lastLFC; + uint32_t lastRFC; }; +/* Statistics reported by the hardware */ struct ixgb_hw_stats { uint64_t tprl; uint64_t tprh; @@ -578,48 +789,49 @@ extern void ixgb_check_for_link(struct ixgb_hw *hw); extern boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw); extern boolean_t ixgb_setup_fc(struct ixgb_hw *hw); extern void ixgb_clear_hw_cntrs(struct ixgb_hw *hw); -extern boolean_t mac_addr_valid(u8 * mac_addr); +extern boolean_t mac_addr_valid(uint8_t * mac_addr); -extern u16 ixgb_read_phy_reg(struct ixgb_hw *hw, - u32 reg_addr, - u32 phy_addr, u32 device_type); +extern uint16_t ixgb_read_phy_reg(struct ixgb_hw *hw, + uint32_t reg_addr, + uint32_t phy_addr, uint32_t device_type); extern void ixgb_write_phy_reg(struct ixgb_hw *hw, - u32 reg_addr, - u32 phy_addr, - u32 device_type, u16 data); + uint32_t reg_addr, + uint32_t phy_addr, + uint32_t device_type, uint16_t data); -extern void ixgb_rar_set(struct ixgb_hw *hw, u8 * addr, u32 index); +extern void ixgb_rar_set(struct ixgb_hw *hw, uint8_t * addr, uint32_t index); /* Filters (multicast, vlan, receive) */ extern void ixgb_mc_addr_list_update(struct ixgb_hw *hw, - u8 * mc_addr_list, - u32 mc_addr_count, u32 pad); + uint8_t * mc_addr_list, + uint32_t mc_addr_count, uint32_t pad); /* Vfta functions */ extern void ixgb_write_vfta(struct ixgb_hw *hw, - u32 offset, u32 value); + uint32_t offset, uint32_t value); extern void ixgb_clear_vfta(struct ixgb_hw *hw); /* Access functions to eeprom data */ -void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, u8 * mac_addr); -u16 ixgb_get_ee_compatibility(struct ixgb_hw *hw); -u32 ixgb_get_ee_pba_number(struct ixgb_hw *hw); -u16 ixgb_get_ee_init_ctrl_reg_1(struct ixgb_hw *hw); -u16 ixgb_get_ee_init_ctrl_reg_2(struct ixgb_hw *hw); -u16 ixgb_get_ee_subsystem_id(struct ixgb_hw *hw); -u16 ixgb_get_ee_subvendor_id(struct ixgb_hw *hw); -u16 ixgb_get_ee_device_id(struct ixgb_hw *hw); -u16 ixgb_get_ee_vendor_id(struct ixgb_hw *hw); -u16 ixgb_get_ee_swdpins_reg(struct ixgb_hw *hw); -u8 ixgb_get_ee_d3_power(struct ixgb_hw *hw); -u8 ixgb_get_ee_d0_power(struct ixgb_hw *hw); +void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t * mac_addr); +uint16_t ixgb_get_ee_compatibility(struct ixgb_hw *hw); +uint32_t ixgb_get_ee_pba_number(struct ixgb_hw *hw); +uint16_t ixgb_get_ee_init_ctrl_reg_1(struct ixgb_hw *hw); +uint16_t ixgb_get_ee_init_ctrl_reg_2(struct ixgb_hw *hw); +uint16_t ixgb_get_ee_subsystem_id(struct ixgb_hw *hw); +uint16_t ixgb_get_ee_subvendor_id(struct ixgb_hw *hw); +uint16_t ixgb_get_ee_device_id(struct ixgb_hw *hw); +uint16_t ixgb_get_ee_vendor_id(struct ixgb_hw *hw); +uint16_t ixgb_get_ee_swdpins_reg(struct ixgb_hw *hw); +uint8_t ixgb_get_ee_d3_power(struct ixgb_hw *hw); +uint8_t ixgb_get_ee_d0_power(struct ixgb_hw *hw); boolean_t ixgb_get_eeprom_data(struct ixgb_hw *hw); +uint16_t ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index); /* Everything else */ void ixgb_led_on(struct ixgb_hw *hw); void ixgb_led_off(struct ixgb_hw *hw); -void ixgb_write_pci_cfg(struct ixgb_hw *hw, u32 reg, u16 * value); +void ixgb_write_pci_cfg(struct ixgb_hw *hw, uint32_t reg, uint16_t * value); #endif /* _IXGB_HW_H_ */