X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fnet%2Fs2io.h;h=3b0bafd273c8c74fdd95b5120d5c9f0c7a9aad42;hb=refs%2Fremotes%2Fvserver;hp=31035dbfcd5e0f9f930622c9d974a4825331310b;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h index 31035dbfc..3b0bafd27 100644 --- a/drivers/net/s2io.h +++ b/drivers/net/s2io.h @@ -1,6 +1,6 @@ /************************************************************************ - * s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC - * Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com) + * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC + * Copyright(c) 2002-2005 Neterion Inc. * This software may be used and distributed according to the terms of * the GNU General Public License (GPL), incorporated herein by reference. @@ -16,6 +16,7 @@ #define TBD 0 #define BIT(loc) (0x8000000000000000ULL >> (loc)) #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz)) +#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff) #ifndef BOOL #define BOOL int @@ -30,6 +31,11 @@ #define SUCCESS 0 #define FAILURE -1 +#define CHECKBIT(value, nbit) (value & (1 << nbit)) + +/* Maximum time to flicker LED when asked to identify NIC using ethtool */ +#define MAX_FLICKER_TIME 60000 /* 60 Secs */ + /* Maximum outstanding splits to be configured into xena. */ typedef enum xena_max_outstanding_splits { XENA_ONE_SPLIT_TRANSACTION = 0, @@ -44,16 +50,14 @@ typedef enum xena_max_outstanding_splits { #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4) /* OS concerned variables and constants */ -#define WATCH_DOG_TIMEOUT 5*HZ -#define EFILL 0x1234 -#define ALIGN_SIZE 127 -#define PCIX_COMMAND_REGISTER 0x62 +#define WATCH_DOG_TIMEOUT 15*HZ +#define EFILL 0x1234 +#define ALIGN_SIZE 127 +#define PCIX_COMMAND_REGISTER 0x62 /* * Debug related variables. */ -#define DEBUG_ON TRUE - /* different debug levels. */ #define ERR_DBG 0 #define INIT_DBG 1 @@ -62,7 +66,7 @@ typedef enum xena_max_outstanding_splits { #define INTR_DBG 4 /* Global variable that defines the present debug level of the driver. */ -int debug_level = ERR_DBG; /* Default level. */ +static int debug_level = ERR_DBG; /* DEBUG message print. */ #define DBG_PRINT(dbg_level, args...) if(!(debug_level> 62) + #define MASK_VLAN_TAG vBIT(0xFFFF,48,16) #define SET_VLAN_TAG(val) vBIT(val,48,16) #define SET_NUM_TAG(val) vBIT(val,16,32) -#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16))) -/* -#define TXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) >> (63-31)) -#define TXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) >> (63-47)) -*/ - u64 Buffer0_ptr; + } RxD_t; +/* Rx descriptor structure for 1 buffer mode */ +typedef struct _RxD1_t { + struct _RxD_t h; + +#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14) +#define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14) +#define RXD_GET_BUFFER0_SIZE_1(_Control_2) \ + (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48) + u64 Buffer0_ptr; +} RxD1_t; +/* Rx descriptor structure for 3 or 2 buffer mode */ + +typedef struct _RxD3_t { + struct _RxD_t h; + +#define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14) +#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16) +#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16) +#define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8) +#define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16) +#define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16) +#define RXD_GET_BUFFER0_SIZE_3(Control_2) \ + (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48) +#define RXD_GET_BUFFER1_SIZE_3(Control_2) \ + (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32) +#define RXD_GET_BUFFER2_SIZE_3(Control_2) \ + (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16) +#define BUF0_LEN 40 +#define BUF1_LEN 1 + u64 Buffer0_ptr; + u64 Buffer1_ptr; + u64 Buffer2_ptr; +} RxD3_t; -/* Structure that represents the Rx descriptor block which contains + +/* Structure that represents the Rx descriptor block which contains * 128 Rx descriptors. */ typedef struct _RxD_block { -#define MAX_RXDS_PER_BLOCK 127 - RxD_t rxd[MAX_RXDS_PER_BLOCK]; +#define MAX_RXDS_PER_BLOCK_1 127 + RxD1_t rxd[MAX_RXDS_PER_BLOCK_1]; u64 reserved_0; #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL - u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd in this blk */ - u64 reserved_2_pNext_RxD_block; /*@ Logical ptr to next */ - u64 pNext_RxD_Blk_physical; /* Buff0_ptr. - In a 32 bit arch the upper 32 bits - should be 0 */ + u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last + * Rxd in this blk */ + u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */ + u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch + * the upper 32 bits should + * be 0 */ } RxD_block_t; +#define SIZE_OF_BLOCK 4096 + +#define RXD_MODE_1 0 +#define RXD_MODE_3A 1 +#define RXD_MODE_3B 2 + +/* Structure to hold virtual addresses of Buf0 and Buf1 in + * 2buf mode. */ +typedef struct bufAdd { + void *ba_0_org; + void *ba_1_org; + void *ba_0; + void *ba_1; +} buffAdd_t; + /* Structure which stores all the MAC control parameters */ -/* This structure stores the offset of the RxD in the ring - * from which the Rx Interrupt processor can start picking +/* This structure stores the offset of the RxD in the ring + * from which the Rx Interrupt processor can start picking * up the RxDs for processing. */ typedef struct _rx_curr_get_info_t { @@ -554,7 +565,7 @@ typedef struct _rx_curr_get_info_t { typedef rx_curr_get_info_t rx_curr_put_info_t; /* This structure stores the offset of the TxDl in the FIFO - * from which the Tx Interrupt processor can start picking + * from which the Tx Interrupt processor can start picking * up the TxDLs for send complete interrupt processing. */ typedef struct { @@ -564,61 +575,109 @@ typedef struct { typedef tx_curr_get_info_t tx_curr_put_info_t; -/* Infomation related to the Tx and Rx FIFOs and Rings of Xena - * is maintained in this structure. - */ -typedef struct mac_info { -/* rx side stuff */ - u32 rxd_ring_mem_sz; - RxD_t *RxRing[MAX_RX_RINGS]; /* Logical Rx ring pointers */ - dma_addr_t RxRing_Phy[MAX_RX_RINGS]; - /* Put pointer info which indictes which RxD has to be replenished +typedef struct rxd_info { + void *virt_addr; + dma_addr_t dma_addr; +}rxd_info_t; + +/* Structure that holds the Phy and virt addresses of the Blocks */ +typedef struct rx_block_info { + void *block_virt_addr; + dma_addr_t block_dma_addr; + rxd_info_t *rxds; +} rx_block_info_t; + +/* pre declaration of the nic structure */ +typedef struct s2io_nic nic_t; + +/* Ring specific structure */ +typedef struct ring_info { + /* The ring number */ + int ring_no; + + /* + * Place holders for the virtual and physical addresses of + * all the Rx Blocks + */ + rx_block_info_t rx_blocks[MAX_RX_BLOCKS_PER_RING]; + int block_count; + int pkt_cnt; + + /* + * Put pointer info which indictes which RxD has to be replenished * with a new buffer. */ - rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS]; + rx_curr_put_info_t rx_curr_put_info; - /* Get pointer info which indictes which is the last RxD that was + /* + * Get pointer info which indictes which is the last RxD that was * processed by the driver. */ - rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS]; + rx_curr_get_info_t rx_curr_get_info; - u16 rmac_pause_time; +#ifndef CONFIG_S2IO_NAPI + /* Index to the absolute position of the put pointer of Rx ring */ + int put_pos; +#endif + + /* Buffer Address store. */ + buffAdd_t **ba; + nic_t *nic; +} ring_info_t; + +/* Fifo specific structure */ +typedef struct fifo_info { + /* FIFO number */ + int fifo_no; + + /* Maximum TxDs per TxDL */ + int max_txds; - /* this will be used in receive function, this decides which ring would - be processed first. eg: ring with priority value 0 (highest) should - be processed first. - first 3 LSB bits represent ring number which should be processed - first, similarly next 3 bits represent next ring to be processed. - eg: value of _rx_ring_pri_map = 0x0000 003A means - ring #2 would be processed first and #7 would be processed next + /* Place holder of all the TX List's Phy and Virt addresses. */ + list_info_hold_t *list_info; + + /* + * Current offset within the tx FIFO where driver would write + * new Tx frame */ - u32 _rx_ring_pri_map; + tx_curr_put_info_t tx_curr_put_info; -/* tx side stuff */ - void *txd_list_mem; /* orignal pointer to allocated mem */ - dma_addr_t txd_list_mem_phy; - u32 txd_list_mem_sz; + /* + * Current offset within tx FIFO from where the driver would start freeing + * the buffers + */ + tx_curr_get_info_t tx_curr_get_info; + nic_t *nic; +}fifo_info_t; + +/* Information related to the Tx and Rx FIFOs and Rings of Xena + * is maintained in this structure. + */ +typedef struct mac_info { +/* tx side stuff */ /* logical pointer of start of each Tx FIFO */ - TxFIFO_element_t *tx_FIFO_start[MAX_TX_FIFOS]; + TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS]; - /* logical pointer of start of TxDL which corresponds to each Tx FIFO */ - TxD_t *txdl_start[MAX_TX_FIFOS]; + /* Fifo specific structure */ + fifo_info_t fifos[MAX_TX_FIFOS]; - /* Same as txdl_start but phy addr */ - dma_addr_t txdl_start_phy[MAX_TX_FIFOS]; + /* Save virtual address of TxD page with zero DMA addr(if any) */ + void *zerodma_virt_addr; -/* Current offset within tx_FIFO_start, where driver would write new Tx frame*/ - tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS]; - tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS]; +/* rx side stuff */ + /* Ring specific structure */ + ring_info_t rings[MAX_RX_RINGS]; - u16 txdl_len; /* length of a TxDL, same for all */ + u16 rmac_pause_time; + u16 mc_pause_threshold_q0q3; + u16 mc_pause_threshold_q4q7; void *stats_mem; /* orignal pointer to allocated mem */ dma_addr_t stats_mem_phy; /* Physical address of the stat block */ u32 stats_mem_sz; - StatInfo_t *StatsInfo; /* Logical address of the stat block */ + StatInfo_t *stats_info; /* Logical address of the stat block */ } mac_info_t; /* structure representing the user defined MAC addresses */ @@ -627,53 +686,98 @@ typedef struct { int usage_cnt; } usr_addr_t; -/* Structure that holds the Phy and virt addresses of the Blocks */ -typedef struct rx_block_info { - RxD_t *block_virt_addr; - dma_addr_t block_dma_addr; -} rx_block_info_t; +/* Default Tunable parameters of the NIC. */ +#define DEFAULT_FIFO_0_LEN 4096 +#define DEFAULT_FIFO_1_7_LEN 512 +#define SMALL_BLK_CNT 30 +#define LARGE_BLK_CNT 100 + +/* + * Structure to keep track of the MSI-X vectors and the corresponding + * argument registered against each vector + */ +#define MAX_REQUESTED_MSI_X 17 +struct s2io_msix_entry +{ + u16 vector; + u16 entry; + void *arg; + + u8 type; +#define MSIX_FIFO_TYPE 1 +#define MSIX_RING_TYPE 2 + + u8 in_use; +#define MSIX_REGISTERED_SUCCESS 0xAA +}; + +struct msix_info_st { + u64 addr; + u64 data; +}; + +/* Data structure to represent a LRO session */ +typedef struct lro { + struct sk_buff *parent; + struct sk_buff *last_frag; + u8 *l2h; + struct iphdr *iph; + struct tcphdr *tcph; + u32 tcp_next_seq; + u32 tcp_ack; + int total_len; + int frags_len; + int sg_num; + int in_use; + u16 window; + u32 cur_tsval; + u32 cur_tsecr; + u8 saw_ts; +}lro_t; /* Structure representing one instance of the NIC */ -typedef struct s2io_nic { +struct s2io_nic { + int rxd_mode; +#ifdef CONFIG_S2IO_NAPI + /* + * Count of packets to be processed in a given iteration, it will be indicated + * by the quota field of the device structure when NAPI is enabled. + */ + int pkts_to_process; +#endif + struct net_device *dev; + mac_info_t mac_control; + struct config_param config; + struct pci_dev *pdev; + void __iomem *bar0; + void __iomem *bar1; #define MAX_MAC_SUPPORTED 16 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED - macaddr_t defMacAddr[MAX_MAC_SUPPORTED]; - macaddr_t preMacAddr[MAX_MAC_SUPPORTED]; + macaddr_t def_mac_addr[MAX_MAC_SUPPORTED]; + macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED]; struct net_device_stats stats; - caddr_t bar0; - caddr_t bar1; - struct config_param config; - mac_info_t mac_control; int high_dma_flag; int device_close_flag; int device_enabled_once; - char name[32]; + char name[60]; struct tasklet_struct task; - atomic_t tasklet_status; - struct timer_list timer; - struct net_device *dev; - struct pci_dev *pdev; + volatile unsigned long tasklet_status; - u16 vendor_id; - u16 device_id; - u16 ccmd; - u32 cbar0_1; - u32 cbar0_2; - u32 cbar1_1; - u32 cbar1_2; - u32 cirq; - u8 cache_line; - u32 rom_expansion; - u16 pcix_cmd; + /* Timer that handles I/O errors/exceptions */ + struct timer_list alarm_timer; + + /* Space to back up the PCI config space */ u32 config_space[256 / sizeof(u32)]; - u32 irq; + atomic_t rx_bufs_left[MAX_RX_RINGS]; - spinlock_t isr_lock; spinlock_t tx_lock; +#ifndef CONFIG_S2IO_NAPI + spinlock_t put_lock; +#endif #define PROMISC 1 #define ALL_MULTI 2 @@ -692,44 +796,22 @@ typedef struct s2io_nic { u16 tx_err_count; u16 rx_err_count; -#if DEBUG_ON - u64 rxpkt_bytes; - u64 txpkt_bytes; - int int_cnt; - int rxint_cnt; - int txint_cnt; - u64 rxpkt_cnt; -#endif - - /* Place holders for the virtual and physical addresses of - * all the Rx Blocks - */ - struct rx_block_info - rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING]; - int block_count[MAX_RX_RINGS]; - int pkt_cnt[MAX_RX_RINGS]; - /* Id timer, used to blink NIC to physically identify NIC. */ struct timer_list id_timer; /* Restart timer, used to restart NIC if the device is stuck and - * a schedule task that will set the correct Link state once the + * a schedule task that will set the correct Link state once the * NIC's PHY has stabilized after a state change. */ -#ifdef INIT_TQUEUE - struct tq_struct rst_timer_task; - struct tq_struct set_link_task; -#else struct work_struct rst_timer_task; struct work_struct set_link_task; -#endif - /* Flag that can be used to turn on or turn off the Rx checksum + /* Flag that can be used to turn on or turn off the Rx checksum * offload feature. */ int rx_csum; - /* after blink, the adapter must be restored with original + /* after blink, the adapter must be restored with original * values. */ u64 adapt_ctrl_org; @@ -738,19 +820,51 @@ typedef struct s2io_nic { u16 last_link_state; #define LINK_DOWN 1 #define LINK_UP 2 -} nic_t; + + int task_flag; +#define CARD_DOWN 1 +#define CARD_UP 2 + atomic_t card_state; + volatile unsigned long link_state; + struct vlan_group *vlgrp; +#define MSIX_FLG 0xA5 + struct msix_entry *entries; + struct s2io_msix_entry *s2io_entries; + char desc[MAX_REQUESTED_MSI_X][25]; + + int avail_msix_vectors; /* No. of MSI-X vectors granted by system */ + + struct msix_info_st msix_info[0x3f]; + +#define XFRAME_I_DEVICE 1 +#define XFRAME_II_DEVICE 2 + u8 device_type; + +#define MAX_LRO_SESSIONS 32 + lro_t lro0_n[MAX_LRO_SESSIONS]; + unsigned long clubbed_frms_cnt; + unsigned long sending_both; + u8 lro; + u16 lro_max_aggr_per_sess; + +#define INTA 0 +#define MSI 1 +#define MSI_X 2 + u8 intr_type; + + spinlock_t rx_lock; + atomic_t isr_cnt; + u64 *ufo_in_band_v; +#define VPD_PRODUCT_NAME_LEN 50 + u8 product_name[VPD_PRODUCT_NAME_LEN]; +}; #define RESET_ERROR 1; #define CMD_ERROR 2; -/* Default Tunable parameters of the NIC. */ -#define DEFAULT_FIFO_LEN 4096 -#define SMALL_RXD_CNT 40 * (MAX_RXDS_PER_BLOCK+1) -#define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1) - /* OS related system calls */ #ifndef readq -static inline u64 readq(void *addr) +static inline u64 readq(void __iomem *addr) { u64 ret = 0; ret = readl(addr + 4); @@ -762,13 +876,38 @@ static inline u64 readq(void *addr) #endif #ifndef writeq -static inline void writeq(u64 val, void *addr) +static inline void writeq(u64 val, void __iomem *addr) { writel((u32) (val), addr); writel((u32) (val >> 32), (addr + 4)); } #endif +/* + * Some registers have to be written in a particular order to + * expect correct hardware operation. The macro SPECIAL_REG_WRITE + * is used to perform such ordered writes. Defines UF (Upper First) + * and LF (Lower First) will be used to specify the required write order. + */ +#define UF 1 +#define LF 2 +static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order) +{ + u32 ret; + + if (order == LF) { + writel((u32) (val), addr); + ret = readl(addr); + writel((u32) (val >> 32), (addr + 4)); + ret = readl(addr + 4); + } else { + writel((u32) (val >> 32), (addr + 4)); + ret = readl(addr + 4); + writel((u32) (val), addr); + ret = readl(addr); + } +} + /* Interrupt related values of Xena */ #define ENABLE_INTRS 1 @@ -817,39 +956,69 @@ static inline void writeq(u64 val, void *addr) /* DMA level Inressupts */ #define TXDMA_PFC_INT_M BIT(0) - /* PFC block interrupts */ +#define TXDMA_PCC_INT_M BIT(2) + +/* PFC block interrupts */ #define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */ +/* PCC block interrupts. */ +#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate + PCC_FB_ECC Error. */ + +#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG) /* * Prototype declaration. */ static int __devinit s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre); -static void __exit s2io_rem_nic(struct pci_dev *pdev); -static int initSharedMem(struct s2io_nic *sp); -static void freeSharedMem(struct s2io_nic *sp); -static int initNic(struct s2io_nic *nic); -#ifndef CONFIG_S2IO_NAPI -static void rxIntrHandler(struct s2io_nic *sp); -#endif -static void txIntrHandler(struct s2io_nic *sp); -static void alarmIntrHandler(struct s2io_nic *sp); +static void __devexit s2io_rem_nic(struct pci_dev *pdev); +static int init_shared_mem(struct s2io_nic *sp); +static void free_shared_mem(struct s2io_nic *sp); +static int init_nic(struct s2io_nic *nic); +static void rx_intr_handler(ring_info_t *ring_data); +static void tx_intr_handler(fifo_info_t *fifo_data); +static void alarm_intr_handler(struct s2io_nic *sp); static int s2io_starter(void); -void s2io_closer(void); static void s2io_tx_watchdog(struct net_device *dev); static void s2io_tasklet(unsigned long dev_addr); static void s2io_set_multicast(struct net_device *dev); -static int rxOsmHandler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no); -void s2io_link(nic_t * sp, int link); -void s2io_reset(nic_t * sp); -#ifdef CONFIG_S2IO_NAPI +static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp); +static void s2io_link(nic_t * sp, int link); +#if defined(CONFIG_S2IO_NAPI) static int s2io_poll(struct net_device *dev, int *budget); #endif static void s2io_init_pci(nic_t * sp); -int s2io_set_mac_addr(struct net_device *dev, u8 * addr); -static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs); -static int verify_xena_quiescence(u64 val64, int flag); -static struct ethtool_ops netdev_ethtool_ops; +static int s2io_set_mac_addr(struct net_device *dev, u8 * addr); +static void s2io_alarm_handle(unsigned long data); +static int s2io_enable_msi(nic_t *nic); +static irqreturn_t s2io_msi_handle(int irq, void *dev_id); +static irqreturn_t +s2io_msix_ring_handle(int irq, void *dev_id); +static irqreturn_t +s2io_msix_fifo_handle(int irq, void *dev_id); +static irqreturn_t s2io_isr(int irq, void *dev_id); +static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag); +static const struct ethtool_ops netdev_ethtool_ops; +static void s2io_set_link(struct work_struct *work); +static int s2io_set_swapper(nic_t * sp); +static void s2io_card_down(nic_t *nic); +static int s2io_card_up(nic_t *nic); +static int get_xena_rev_id(struct pci_dev *pdev); +static void restore_xmsi_data(nic_t *nic); + +static int s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro, RxD_t *rxdp, nic_t *sp); +static void clear_lro_session(lro_t *lro); +static void queue_rx_frame(struct sk_buff *skb); +static void update_L3L4_header(nic_t *sp, lro_t *lro); +static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb, u32 tcp_len); + +#define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size +#define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size +#define s2io_offload_type(skb) skb_shinfo(skb)->gso_type + +#define S2IO_PARM_INT(X, def_val) \ + static unsigned int X = def_val;\ + module_param(X , uint, 0); #endif /* _S2IO_H */