X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fnet%2Fsmc91x.h;h=fad8c04373342c36b2a95fe47962645d952952af;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=7679022c072954dbf80a5ebe3aec5e1fdb6fceec;hpb=5fc42a6ed0ec81088c37caadb45898ae6cd0ad2c;p=linux-2.6.git diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h index 7679022c0..fad8c0437 100644 --- a/drivers/net/smc91x.h +++ b/drivers/net/smc91x.h @@ -39,11 +39,7 @@ * Define your architecture specific bus configuration parameters here. */ -#if defined(CONFIG_SA1100_GRAPHICSCLIENT) || \ - defined(CONFIG_SA1100_PFS168) || \ - defined(CONFIG_SA1100_FLEXANET) || \ - defined(CONFIG_SA1100_GRAPHICSMASTER) || \ - defined(CONFIG_ARCH_LUBBOCK) +#if defined(CONFIG_ARCH_LUBBOCK) /* We can only do 16-bit reads and writes in the static memory space. */ #define SMC_CAN_USE_8BIT 0 @@ -96,6 +92,25 @@ } while (0) #define set_irq_type(irq, type) +#elif defined(CONFIG_SA1100_PLEB) +/* We can only do 16-bit reads and writes in the static memory space. */ +#define SMC_CAN_USE_8BIT 1 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_IO_SHIFT 0 +#define SMC_NOWAIT 1 + +#define SMC_inb(a, r) inb((a) + (r)) +#define SMC_insb(a, r, p, l) insb((a) + (r), p, (l)) +#define SMC_inw(a, r) inw((a) + (r)) +#define SMC_insw(a, r, p, l) insw((a) + (r), p, l) +#define SMC_outb(v, a, r) outb(v, (a) + (r)) +#define SMC_outsb(a, r, p, l) outsb((a) + (r), p, (l)) +#define SMC_outw(v, a, r) outw(v, (a) + (r)) +#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) + +#define set_irq_type(irq, type) do {} while (0) + #elif defined(CONFIG_SA1100_ASSABET) #include @@ -160,6 +175,71 @@ SMC_outw(u16 val, unsigned long ioaddr, int reg) #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) +#elif defined(CONFIG_M32R) + +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 + +#define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) +#define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) +#define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) +#define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) +#define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) +#define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) + +#define set_irq_type(irq, type) do {} while(0) + +#define RPC_LSA_DEFAULT RPC_LED_TX_RX +#define RPC_LSB_DEFAULT RPC_LED_100_10 + +#elif defined(CONFIG_MACH_LPD7A400) || defined(CONFIG_MACH_LPD7A404) + +/* The LPD7A40X_IOBARRIER is necessary to overcome a mismatch between + * the way that the CPU handles chip selects and the way that the SMC + * chip expects the chip select to operate. Refer to + * Documentation/arm/Sharp-LH/IOBarrier for details. The read from + * IOBARRIER is a byte as a least-common denominator of possible + * regions to use as the barrier. It would be wasteful to read 32 + * bits from a byte oriented region. + * + * There is no explicit protection against interrupts intervening + * between the writew and the IOBARRIER. In SMC ISR there is a + * preamble that performs an IOBARRIER in the extremely unlikely event + * that the driver interrupts itself between a writew to the chip an + * the IOBARRIER that follows *and* the cache is large enough that the + * first off-chip access while handing the interrupt is to the SMC + * chip. Other devices in the same address space as the SMC chip must + * be aware of the potential for trouble and perform a similar + * IOBARRIER on entry to their ISR. + */ + +#include /* IOBARRIER_VIRT */ + +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_NOWAIT 0 +#define LPD7A40X_IOBARRIER readb (IOBARRIER_VIRT) + +#define SMC_inw(a,r) readw ((void*) ((a) + (r))) +#define SMC_insw(a,r,p,l) readsw ((void*) ((a) + (r)), p, l) +#define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7A40X_IOBARRIER; }) + +static inline void SMC_outsw (unsigned long a, int r, unsigned char* p, int l) +{ + unsigned short* ps = (unsigned short*) p; + while (l-- > 0) { + writew (*ps++, a + r); + LPD7A40X_IOBARRIER; + } +} + +#define SMC_INTERRUPT_PREAMBLE LPD7A40X_IOBARRIER + +#define RPC_LSA_DEFAULT RPC_LED_TX_RX +#define RPC_LSB_DEFAULT RPC_LED_100_10 + #else #define SMC_CAN_USE_8BIT 1 @@ -189,8 +269,9 @@ SMC_outw(u16 val, unsigned long ioaddr, int reg) * different and probably not worth it for that reason, and not as critical * as RX which can overrun memory and lose packets. */ -#include +#include #include +#include #ifdef SMC_insl #undef SMC_insl @@ -210,21 +291,23 @@ smc_pxa_dma_insl(u_long ioaddr, u_long physaddr, int reg, int dma, /* 64 bit alignment is required for memory to memory DMA */ if ((long)buf & 4) { - *((u32 *)buf)++ = SMC_inl(ioaddr, reg); + *((u32 *)buf) = SMC_inl(ioaddr, reg); + buf += 4; len--; } len *= 4; - dmabuf = dma_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE); + dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); DCSR(dma) = DCSR_NODESC; DTADR(dma) = dmabuf; DSADR(dma) = physaddr + reg; DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | DCMD_WIDTH4 | (DCMD_LENGTH & len)); DCSR(dma) = DCSR_NODESC | DCSR_RUN; - while (!(DCSR(dma) & DCSR_STOPSTATE)); + while (!(DCSR(dma) & DCSR_STOPSTATE)) + cpu_relax(); DCSR(dma) = 0; - dma_unmap_single(NULL, dmabuf, len, PCI_DMA_FROMDEVICE); + dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); } #endif @@ -246,21 +329,23 @@ smc_pxa_dma_insw(u_long ioaddr, u_long physaddr, int reg, int dma, /* 64 bit alignment is required for memory to memory DMA */ while ((long)buf & 6) { - *((u16 *)buf)++ = SMC_inw(ioaddr, reg); + *((u16 *)buf) = SMC_inw(ioaddr, reg); + buf += 2; len--; } len *= 2; - dmabuf = dma_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE); + dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); DCSR(dma) = DCSR_NODESC; DTADR(dma) = dmabuf; DSADR(dma) = physaddr + reg; DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | DCMD_WIDTH2 | (DCMD_LENGTH & len)); DCSR(dma) = DCSR_NODESC | DCSR_RUN; - while (!(DCSR(dma) & DCSR_STOPSTATE)); + while (!(DCSR(dma) & DCSR_STOPSTATE)) + cpu_relax(); DCSR(dma) = 0; - dma_unmap_single(NULL, dmabuf, len, PCI_DMA_FROMDEVICE); + dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); } #endif @@ -749,16 +834,9 @@ static const char * chip_ids[ 16 ] = { SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ } while (0) -#define SMC_CLEAR_MCAST() \ - do { \ - SMC_outw( 0, ioaddr, MCAST_REG1 ); \ - SMC_outw( 0, ioaddr, MCAST_REG2 ); \ - SMC_outw( 0, ioaddr, MCAST_REG3 ); \ - SMC_outw( 0, ioaddr, MCAST_REG4 ); \ - } while (0) #define SMC_SET_MCAST(x) \ do { \ - unsigned char *mt = (x); \ + const unsigned char *mt = (x); \ SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ @@ -809,9 +887,10 @@ static const char * chip_ids[ 16 ] = { do { \ char *__ptr = (p); \ int __len = (l); \ - if (__len >= 2 && (long)__ptr & 2) { \ + if (__len >= 2 && (unsigned long)__ptr & 2) { \ __len -= 2; \ - SMC_outw( *((u16 *)__ptr)++, ioaddr, DATA_REG );\ + SMC_outw( *(u16 *)__ptr, ioaddr, DATA_REG ); \ + __ptr += 2; \ } \ SMC_outsl( ioaddr, DATA_REG, __ptr, __len >> 2); \ if (__len & 2) { \ @@ -823,7 +902,7 @@ static const char * chip_ids[ 16 ] = { do { \ char *__ptr = (p); \ int __len = (l); \ - if ((long)__ptr & 2) { \ + if ((unsigned long)__ptr & 2) { \ /* \ * We want 32bit alignment here. \ * Since some buses perform a full 32bit \ @@ -831,7 +910,7 @@ static const char * chip_ids[ 16 ] = { * SMC_inw() here. Back both source (on chip \ * and destination) pointers of 2 bytes. \ */ \ - (long)__ptr &= ~2; \ + __ptr -= 2; \ __len += 2; \ SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \ } \ @@ -862,5 +941,8 @@ static const char * chip_ids[ 16 ] = { }) #endif +#if !defined (SMC_INTERRUPT_PREAMBLE) +# define SMC_INTERRUPT_PREAMBLE +#endif #endif /* _SMC91X_H_ */