X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fnet%2Fsungem.h;h=a70067c85cc9d56892e0928891abde77c3db35e9;hb=97bf2856c6014879bd04983a3e9dfcdac1e7fe85;hp=00343226fb71e9a004189fdaeb6df5f1273006cc;hpb=c7b5ebbddf7bcd3651947760f423e3783bbe6573;p=linux-2.6.git diff --git a/drivers/net/sungem.h b/drivers/net/sungem.h index 00343226f..a70067c85 100644 --- a/drivers/net/sungem.h +++ b/drivers/net/sungem.h @@ -170,6 +170,27 @@ * them later. -DaveM */ +/* WakeOnLan Registers */ +#define WOL_MATCH0 0x3000UL +#define WOL_MATCH1 0x3004UL +#define WOL_MATCH2 0x3008UL +#define WOL_MCOUNT 0x300CUL +#define WOL_WAKECSR 0x3010UL + +/* WOL Match count register + */ +#define WOL_MCOUNT_N 0x00000010 +#define WOL_MCOUNT_M 0x00000000 /* 0 << 8 */ + +#define WOL_WAKECSR_ENABLE 0x00000001 +#define WOL_WAKECSR_MII 0x00000002 +#define WOL_WAKECSR_SEEN 0x00000004 +#define WOL_WAKECSR_FILT_UCAST 0x00000008 +#define WOL_WAKECSR_FILT_MCAST 0x00000010 +#define WOL_WAKECSR_FILT_BCAST 0x00000020 +#define WOL_WAKECSR_FILT_SEEN 0x00000040 + + /* Receive DMA Registers */ #define RXDMA_CFG 0x4000UL /* RX Configuration Register */ #define RXDMA_DBLOW 0x4004UL /* RX Descriptor Base Low */ @@ -792,7 +813,7 @@ /* MII BCM5400 AUXSTATUS register */ #define MII_BCM5400_AUXSTATUS 0x19 #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700 -#define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8 +#define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8 /* When it can, GEM internally caches 4 aligned TX descriptors * at a time, so that it can use full cacheline DMA reads. @@ -952,45 +973,38 @@ enum link_state { }; struct gem { - spinlock_t lock; - spinlock_t tx_lock; - void __iomem *regs; - int rx_new, rx_old; - int tx_new, tx_old; - - /* Set when chip is actually in operational state - * (ie. not power managed) - */ - int hw_running; - int opened; - struct semaphore pm_sem; - struct work_struct pm_task; - struct timer_list pm_timer; - - struct gem_init_block *init_block; - - struct sk_buff *rx_skbs[RX_RING_SIZE]; - struct sk_buff *tx_skbs[RX_RING_SIZE]; + spinlock_t lock; + spinlock_t tx_lock; + void __iomem *regs; + int rx_new, rx_old; + int tx_new, tx_old; + + unsigned int has_wol : 1; /* chip supports wake-on-lan */ + unsigned int asleep : 1; /* chip asleep, protected by pm_mutex */ + unsigned int asleep_wol : 1; /* was asleep with WOL enabled */ + unsigned int opened : 1; /* driver opened, protected by pm_mutex */ + unsigned int running : 1; /* chip running, protected by lock */ + + /* cell enable count, protected by lock */ + int cell_enabled; + + struct mutex pm_mutex; u32 msg_enable; u32 status; struct net_device_stats net_stats; - enum gem_phy_type phy_type; - struct mii_phy phy_mii; - int tx_fifo_sz; int rx_fifo_sz; int rx_pause_off; int rx_pause_on; int rx_buf_sz; - int mii_phy_addr; - + u64 pause_entered; + u16 pause_last_time_recvd; u32 mac_rx_cfg; u32 swrst_base; - /* Autoneg & PHY control */ int want_autoneg; int last_forced_speed; enum link_state lstate; @@ -999,14 +1013,18 @@ struct gem { int wake_on_lan; struct work_struct reset_task; volatile int reset_task_pending; - - /* Diagnostic counters and state. */ - u64 pause_entered; - u16 pause_last_time_recvd; - dma_addr_t gblock_dvma; - struct pci_dev *pdev; - struct net_device *dev; + enum gem_phy_type phy_type; + struct mii_phy phy_mii; + int mii_phy_addr; + + struct gem_init_block *init_block; + struct sk_buff *rx_skbs[RX_RING_SIZE]; + struct sk_buff *tx_skbs[TX_RING_SIZE]; + dma_addr_t gblock_dvma; + + struct pci_dev *pdev; + struct net_device *dev; #ifdef CONFIG_PPC_PMAC struct device_node *of_node; #endif @@ -1014,10 +1032,11 @@ struct gem { #define found_mii_phy(gp) ((gp->phy_type == phy_mii_mdio0 || gp->phy_type == phy_mii_mdio1) \ && gp->phy_mii.def && gp->phy_mii.def->ops) - + #define ALIGNED_RX_SKB_ADDR(addr) \ ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr)) -static __inline__ struct sk_buff *gem_alloc_skb(int size, int gfp_flags) +static __inline__ struct sk_buff *gem_alloc_skb(int size, + gfp_t gfp_flags) { struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);