X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fscsi%2Fqla2xxx%2Fqla_dbg.c;h=f6ed6962bc2b71617b631d422e0221eb8c190488;hb=16c70f8c1b54b61c3b951b6fb220df250fe09b32;hp=23f43ec5e278596b353eb33141c3f8052fed1db4;hpb=9bf4aaab3e101692164d49b7ca357651eb691cb6;p=linux-2.6.git diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c index 23f43ec5e..f6ed6962b 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.c +++ b/drivers/scsi/qla2xxx/qla_dbg.c @@ -1,26 +1,41 @@ /* - * QLOGIC LINUX SOFTWARE - * - * QLogic ISP2x00 device driver for Linux 2.6.x - * Copyright (C) 2003-2004 QLogic Corporation - * (www.qlogic.com) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2, or (at your option) any - * later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. + * QLogic Fibre Channel HBA Driver + * Copyright (c) 2003-2005 QLogic Corporation * + * See LICENSE.qla2xxx for copyright and licensing details. */ #include "qla_def.h" #include -static int qla_uprintf(char **, char *, ...); +static inline void +qla2xxx_prep_dump(scsi_qla_host_t *ha, struct qla2xxx_fw_dump *fw_dump) +{ + fw_dump->fw_major_version = htonl(ha->fw_major_version); + fw_dump->fw_minor_version = htonl(ha->fw_minor_version); + fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); + fw_dump->fw_attributes = htonl(ha->fw_attributes); + + fw_dump->vendor = htonl(ha->pdev->vendor); + fw_dump->device = htonl(ha->pdev->device); + fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); + fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); +} + +static inline void * +qla2xxx_copy_queues(scsi_qla_host_t *ha, void *ptr) +{ + /* Request queue. */ + memcpy(ptr, ha->request_ring, ha->request_q_length * + sizeof(request_t)); + + /* Response queue. */ + ptr += ha->request_q_length * sizeof(request_t); + memcpy(ptr, ha->response_ring, ha->response_q_length * + sizeof(response_t)); + + return ptr + (ha->response_q_length * sizeof(response_t)); +} /** * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. @@ -36,13 +51,12 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked) uint16_t mb0, mb2; uint32_t stat; - device_reg_t *reg; - uint16_t *dmp_reg; + struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; + uint16_t __iomem *dmp_reg; unsigned long flags; struct qla2300_fw_dump *fw; - uint32_t dump_size, data_ram_cnt; + uint32_t data_ram_cnt; - reg = ha->iobase; risc_address = data_ram_cnt = 0; mb0 = mb2 = 0; flags = 0; @@ -50,32 +64,26 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked) if (!hardware_locked) spin_lock_irqsave(&ha->hardware_lock, flags); - if (ha->fw_dump != NULL) { + if (!ha->fw_dump) { qla_printk(KERN_WARNING, ha, - "Firmware has been previously dumped (%p) -- ignoring " - "request...\n", ha->fw_dump); + "No buffer available for dump!!!\n"); goto qla2300_fw_dump_failed; } - /* Allocate (large) dump buffer. */ - dump_size = sizeof(struct qla2300_fw_dump); - dump_size += (ha->fw_memory_size - 0x11000) * sizeof(uint16_t); - ha->fw_dump_order = get_order(dump_size); - ha->fw_dump = (struct qla2300_fw_dump *) __get_free_pages(GFP_ATOMIC, - ha->fw_dump_order); - if (ha->fw_dump == NULL) { + if (ha->fw_dumped) { qla_printk(KERN_WARNING, ha, - "Unable to allocated memory for firmware dump (%d/%d).\n", - ha->fw_dump_order, dump_size); + "Firmware has been previously dumped (%p) -- ignoring " + "request...\n", ha->fw_dump); goto qla2300_fw_dump_failed; } - fw = ha->fw_dump; + fw = &ha->fw_dump->isp.isp23; + qla2xxx_prep_dump(ha, ha->fw_dump); rval = QLA_SUCCESS; - fw->hccr = RD_REG_WORD(®->hccr); + fw->hccr = htons(RD_REG_WORD(®->hccr)); /* Pause RISC. */ - WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); + WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); if (IS_QLA2300(ha)) { for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && @@ -86,91 +94,93 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked) rval = QLA_FUNCTION_TIMEOUT; } } else { + RD_REG_WORD(®->hccr); /* PCI Posting. */ udelay(10); } if (rval == QLA_SUCCESS) { - dmp_reg = (uint16_t *)(reg + 0); - for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) - fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++); + dmp_reg = (uint16_t __iomem *)(reg + 0); + for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) + fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x10); - for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) - fw->risc_host_reg[cnt] = RD_REG_WORD(dmp_reg++); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10); + for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) + fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x40); - for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) - fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40); + for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) + fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); WRT_REG_WORD(®->ctrl_status, 0x40); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++) - fw->resp_dma_reg[cnt] = RD_REG_WORD(dmp_reg++); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++) + fw->resp_dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); WRT_REG_WORD(®->ctrl_status, 0x50); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) - fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) + fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); WRT_REG_WORD(®->ctrl_status, 0x00); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0xA0); - for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) - fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2000); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++) - fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2200); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++) - fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2400); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++) - fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2600); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++) - fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2800); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++) - fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2A00); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++) - fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2C00); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++) - fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2E00); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++) - fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->ctrl_status, 0x10); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++) - fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->ctrl_status, 0x20); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++) - fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->ctrl_status, 0x30); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++) - fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0); + for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) + fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2000); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++) + fw->risc_gp0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2200); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++) + fw->risc_gp1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2400); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++) + fw->risc_gp2_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2600); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++) + fw->risc_gp3_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2800); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++) + fw->risc_gp4_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2A00); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++) + fw->risc_gp5_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2C00); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++) + fw->risc_gp6_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2E00); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++) + fw->risc_gp7_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->ctrl_status, 0x10); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++) + fw->frame_buf_hdw_reg[cnt] = + htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->ctrl_status, 0x20); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++) + fw->fpm_b0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->ctrl_status, 0x30); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++) + fw->fpm_b1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); /* Reset RISC. */ WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); @@ -221,6 +231,7 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked) WRT_REG_WORD(®->semaphore, 0); WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); + RD_REG_WORD(®->hccr); break; } else if (stat == 0x10 || stat == 0x11) { set_bit(MBX_INTERRUPT, @@ -231,18 +242,20 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked) WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); + RD_REG_WORD(®->hccr); break; } /* clear this intr; it wasn't a mailbox intr */ WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); + RD_REG_WORD(®->hccr); } udelay(5); } if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { rval = mb0 & MBS_MASK; - fw->risc_ram[cnt] = mb2; + fw->risc_ram[cnt] = htons(mb2); } else { rval = QLA_FUNCTION_FAILED; } @@ -277,6 +290,7 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked) WRT_REG_WORD(®->semaphore, 0); WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); + RD_REG_WORD(®->hccr); break; } else if (stat == 0x10 || stat == 0x11) { set_bit(MBX_INTERRUPT, @@ -287,18 +301,20 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked) WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); + RD_REG_WORD(®->hccr); break; } /* clear this intr; it wasn't a mailbox intr */ WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); + RD_REG_WORD(®->hccr); } udelay(5); } if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { rval = mb0 & MBS_MASK; - fw->stack_ram[cnt] = mb2; + fw->stack_ram[cnt] = htons(mb2); } else { rval = QLA_FUNCTION_FAILED; } @@ -334,6 +350,7 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked) WRT_REG_WORD(®->semaphore, 0); WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); + RD_REG_WORD(®->hccr); break; } else if (stat == 0x10 || stat == 0x11) { set_bit(MBX_INTERRUPT, @@ -344,34 +361,38 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked) WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); + RD_REG_WORD(®->hccr); break; } /* clear this intr; it wasn't a mailbox intr */ WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); + RD_REG_WORD(®->hccr); } udelay(5); } if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { rval = mb0 & MBS_MASK; - fw->data_ram[cnt] = mb2; + fw->data_ram[cnt] = htons(mb2); } else { rval = QLA_FUNCTION_FAILED; } } + if (rval == QLA_SUCCESS) + qla2xxx_copy_queues(ha, &fw->data_ram[cnt]); if (rval != QLA_SUCCESS) { qla_printk(KERN_WARNING, ha, "Failed to dump firmware (%x)!!!\n", rval); + ha->fw_dumped = 0; - free_pages((unsigned long)ha->fw_dump, ha->fw_dump_order); - ha->fw_dump = NULL; } else { qla_printk(KERN_INFO, ha, "Firmware dump saved to temp buffer (%ld/%p).\n", ha->host_no, ha->fw_dump); + ha->fw_dumped = 1; } qla2300_fw_dump_failed: @@ -379,193 +400,6 @@ qla2300_fw_dump_failed: spin_unlock_irqrestore(&ha->hardware_lock, flags); } -/** - * qla2300_ascii_fw_dump() - Converts a binary firmware dump to ASCII. - * @ha: HA context - */ -void -qla2300_ascii_fw_dump(scsi_qla_host_t *ha) -{ - uint32_t cnt; - char *uiter; - char fw_info[30]; - struct qla2300_fw_dump *fw; - uint32_t data_ram_cnt; - - uiter = ha->fw_dump_buffer; - fw = ha->fw_dump; - - qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number, - qla2x00_get_fw_version_str(ha, fw_info)); - - qla_uprintf(&uiter, "\n[==>BEG]\n"); - - qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr); - - qla_uprintf(&uiter, "PBIU Registers:"); - for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nReqQ-RspQ-Risc2Host Status registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_host_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->risc_host_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nMailbox Registers:"); - for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nAuto Request Response DMA Registers:"); - for (cnt = 0; cnt < sizeof (fw->resp_dma_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->resp_dma_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nDMA Registers:"); - for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nRISC Hardware Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nRISC GP0 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nRISC GP1 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nRISC GP2 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nRISC GP3 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nRISC GP4 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nRISC GP5 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nRISC GP6 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nRISC GP7 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:"); - for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nFPM B0 Registers:"); - for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nFPM B1 Registers:"); - for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]); - } - - qla_uprintf(&uiter, "\n\nCode RAM Dump:"); - for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n%04x: ", cnt + 0x0800); - } - qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]); - } - - qla_uprintf(&uiter, "\n\nStack RAM Dump:"); - for (cnt = 0; cnt < sizeof (fw->stack_ram) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n%05x: ", cnt + 0x10000); - } - qla_uprintf(&uiter, "%04x ", fw->stack_ram[cnt]); - } - - qla_uprintf(&uiter, "\n\nData RAM Dump:"); - data_ram_cnt = ha->fw_memory_size - 0x11000 + 1; - for (cnt = 0; cnt < data_ram_cnt; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n%05x: ", cnt + 0x11000); - } - qla_uprintf(&uiter, "%04x ", fw->data_ram[cnt]); - } - - qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump."); -} - /** * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. * @ha: HA context @@ -578,13 +412,11 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked) uint32_t cnt, timer; uint16_t risc_address; uint16_t mb0, mb2; - - device_reg_t *reg; - uint16_t *dmp_reg; + struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; + uint16_t __iomem *dmp_reg; unsigned long flags; struct qla2100_fw_dump *fw; - reg = ha->iobase; risc_address = 0; mb0 = mb2 = 0; flags = 0; @@ -592,30 +424,26 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked) if (!hardware_locked) spin_lock_irqsave(&ha->hardware_lock, flags); - if (ha->fw_dump != NULL) { + if (!ha->fw_dump) { qla_printk(KERN_WARNING, ha, - "Firmware has been previously dumped (%p) -- ignoring " - "request...\n", ha->fw_dump); + "No buffer available for dump!!!\n"); goto qla2100_fw_dump_failed; } - /* Allocate (large) dump buffer. */ - ha->fw_dump_order = get_order(sizeof(struct qla2100_fw_dump)); - ha->fw_dump = (struct qla2100_fw_dump *) __get_free_pages(GFP_ATOMIC, - ha->fw_dump_order); - if (ha->fw_dump == NULL) { + if (ha->fw_dumped) { qla_printk(KERN_WARNING, ha, - "Unable to allocated memory for firmware dump (%d/%Zd).\n", - ha->fw_dump_order, sizeof(struct qla2100_fw_dump)); + "Firmware has been previously dumped (%p) -- ignoring " + "request...\n", ha->fw_dump); goto qla2100_fw_dump_failed; } - fw = ha->fw_dump; + fw = &ha->fw_dump->isp.isp21; + qla2xxx_prep_dump(ha, ha->fw_dump); rval = QLA_SUCCESS; - fw->hccr = RD_REG_WORD(®->hccr); + fw->hccr = htons(RD_REG_WORD(®->hccr)); /* Pause RISC. */ - WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); + WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && rval == QLA_SUCCESS; cnt--) { if (cnt) @@ -624,81 +452,83 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked) rval = QLA_FUNCTION_TIMEOUT; } if (rval == QLA_SUCCESS) { - dmp_reg = (uint16_t *)(reg + 0); - for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) - fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++); + dmp_reg = (uint16_t __iomem *)(reg + 0); + for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) + fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x10); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10); for (cnt = 0; cnt < ha->mbx_count; cnt++) { if (cnt == 8) { - dmp_reg = (uint16_t *)((uint8_t *)reg + 0xe0); + dmp_reg = (uint16_t __iomem *) + ((uint8_t __iomem *)reg + 0xe0); } - fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++); + fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); } - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x20); - for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) - fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x20); + for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) + fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); WRT_REG_WORD(®->ctrl_status, 0x00); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0xA0); - for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) - fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2000); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++) - fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2100); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++) - fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2200); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++) - fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2300); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++) - fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2400); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++) - fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2500); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++) - fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2600); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++) - fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->pcr, 0x2700); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++) - fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->ctrl_status, 0x10); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++) - fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->ctrl_status, 0x20); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++) - fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++); - - WRT_REG_WORD(®->ctrl_status, 0x30); - dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80); - for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++) - fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0); + for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) + fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2000); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++) + fw->risc_gp0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2100); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++) + fw->risc_gp1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2200); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++) + fw->risc_gp2_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2300); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++) + fw->risc_gp3_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2400); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++) + fw->risc_gp4_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2500); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++) + fw->risc_gp5_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2600); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++) + fw->risc_gp6_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->pcr, 0x2700); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++) + fw->risc_gp7_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->ctrl_status, 0x10); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++) + fw->frame_buf_hdw_reg[cnt] = + htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->ctrl_status, 0x20); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++) + fw->fpm_b0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); + + WRT_REG_WORD(®->ctrl_status, 0x30); + dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++) + fw->fpm_b1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); /* Reset the ISP. */ WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); @@ -716,7 +546,7 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked) if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { - WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); + WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && rval == QLA_SUCCESS; cnt--) { @@ -731,6 +561,7 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked) WRT_REG_WORD(®->mctr, 0xf1); else WRT_REG_WORD(®->mctr, 0xf2); + RD_REG_WORD(®->mctr); /* PCI Posting. */ /* Release RISC. */ WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); @@ -761,31 +592,36 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked) WRT_REG_WORD(®->semaphore, 0); WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); + RD_REG_WORD(®->hccr); break; } WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); + RD_REG_WORD(®->hccr); } udelay(5); } if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { rval = mb0 & MBS_MASK; - fw->risc_ram[cnt] = mb2; + fw->risc_ram[cnt] = htons(mb2); } else { rval = QLA_FUNCTION_FAILED; } } + if (rval == QLA_SUCCESS) + qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); + if (rval != QLA_SUCCESS) { qla_printk(KERN_WARNING, ha, "Failed to dump firmware (%x)!!!\n", rval); + ha->fw_dumped = 0; - free_pages((unsigned long)ha->fw_dump, ha->fw_dump_order); - ha->fw_dump = NULL; } else { qla_printk(KERN_INFO, ha, "Firmware dump saved to temp buffer (%ld/%p).\n", ha->host_no, ha->fw_dump); + ha->fw_dumped = 1; } qla2100_fw_dump_failed: @@ -793,190 +629,722 @@ qla2100_fw_dump_failed: spin_unlock_irqrestore(&ha->hardware_lock, flags); } -/** - * qla2100_ascii_fw_dump() - Converts a binary firmware dump to ASCII. - * @ha: HA context - */ void -qla2100_ascii_fw_dump(scsi_qla_host_t *ha) +qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) { - uint32_t cnt; - char *uiter; - char fw_info[30]; - struct qla2100_fw_dump *fw; - - uiter = ha->fw_dump_buffer; - fw = ha->fw_dump; + int rval; + uint32_t cnt, timer; + uint32_t risc_address; + uint16_t mb[4], wd; - qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number, - qla2x00_get_fw_version_str(ha, fw_info)); + uint32_t stat; + struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; + uint32_t __iomem *dmp_reg; + uint32_t *iter_reg; + uint16_t __iomem *mbx_reg; + unsigned long flags; + struct qla24xx_fw_dump *fw; + uint32_t ext_mem_cnt; + void *eft; - qla_uprintf(&uiter, "\n[==>BEG]\n"); + risc_address = ext_mem_cnt = 0; + memset(mb, 0, sizeof(mb)); + flags = 0; - qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr); + if (!hardware_locked) + spin_lock_irqsave(&ha->hardware_lock, flags); - qla_uprintf(&uiter, "PBIU Registers:"); - for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]); + if (!ha->fw_dump) { + qla_printk(KERN_WARNING, ha, + "No buffer available for dump!!!\n"); + goto qla24xx_fw_dump_failed; } - qla_uprintf(&uiter, "\n\nMailbox Registers:"); - for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]); + if (ha->fw_dumped) { + qla_printk(KERN_WARNING, ha, + "Firmware has been previously dumped (%p) -- ignoring " + "request...\n", ha->fw_dump); + goto qla24xx_fw_dump_failed; } + fw = &ha->fw_dump->isp.isp24; + qla2xxx_prep_dump(ha, ha->fw_dump); - qla_uprintf(&uiter, "\n\nDMA Registers:"); - for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]); - } + rval = QLA_SUCCESS; + fw->host_status = htonl(RD_REG_DWORD(®->host_status)); - qla_uprintf(&uiter, "\n\nRISC Hardware Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); + /* Pause RISC. */ + if ((RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0) { + WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET | + HCCRX_CLR_HOST_INT); + RD_REG_DWORD(®->hccr); /* PCI Posting. */ + WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); + for (cnt = 30000; + (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 && + rval == QLA_SUCCESS; cnt--) { + if (cnt) + udelay(100); + else + rval = QLA_FUNCTION_TIMEOUT; } - qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]); } - qla_uprintf(&uiter, "\n\nRISC GP0 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]); - } + if (rval == QLA_SUCCESS) { + /* Host interface registers. */ + dmp_reg = (uint32_t __iomem *)(reg + 0); + for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) + fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Disable interrupts. */ + WRT_REG_DWORD(®->ictrl, 0); + RD_REG_DWORD(®->ictrl); + + /* Shadow registers. */ + WRT_REG_DWORD(®->iobase_addr, 0x0F70); + RD_REG_DWORD(®->iobase_addr); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); + WRT_REG_DWORD(dmp_reg, 0xB0000000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); + fw->shadow_reg[0] = htonl(RD_REG_DWORD(dmp_reg)); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); + WRT_REG_DWORD(dmp_reg, 0xB0100000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); + fw->shadow_reg[1] = htonl(RD_REG_DWORD(dmp_reg)); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); + WRT_REG_DWORD(dmp_reg, 0xB0200000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); + fw->shadow_reg[2] = htonl(RD_REG_DWORD(dmp_reg)); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); + WRT_REG_DWORD(dmp_reg, 0xB0300000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); + fw->shadow_reg[3] = htonl(RD_REG_DWORD(dmp_reg)); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); + WRT_REG_DWORD(dmp_reg, 0xB0400000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); + fw->shadow_reg[4] = htonl(RD_REG_DWORD(dmp_reg)); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); + WRT_REG_DWORD(dmp_reg, 0xB0500000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); + fw->shadow_reg[5] = htonl(RD_REG_DWORD(dmp_reg)); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); + WRT_REG_DWORD(dmp_reg, 0xB0600000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); + fw->shadow_reg[6] = htonl(RD_REG_DWORD(dmp_reg)); + + /* Mailbox registers. */ + mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) + fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); + + /* Transfer sequence registers. */ + iter_reg = fw->xseq_gp_reg; + WRT_REG_DWORD(®->iobase_addr, 0xBF00); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBF10); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBF20); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBF30); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBF40); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBF50); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBF60); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBF70); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBFE0); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) + fw->xseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBFF0); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) + fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Receive sequence registers. */ + iter_reg = fw->rseq_gp_reg; + WRT_REG_DWORD(®->iobase_addr, 0xFF00); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFF10); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFF20); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFF30); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFF40); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFF50); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFF60); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFF70); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFFD0); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) + fw->rseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFFE0); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) + fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFFF0); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) + fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Command DMA registers. */ + WRT_REG_DWORD(®->iobase_addr, 0x7100); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) + fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Queues. */ + iter_reg = fw->req0_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7200); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 8; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); + for (cnt = 0; cnt < 7; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->resp0_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7300); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 8; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); + for (cnt = 0; cnt < 7; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->req1_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7400); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 8; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); + for (cnt = 0; cnt < 7; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Transmit DMA registers. */ + iter_reg = fw->xmt0_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7600); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x7610); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->xmt1_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7620); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x7630); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->xmt2_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7640); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x7650); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->xmt3_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7660); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x7670); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->xmt4_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7680); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x7690); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x76A0); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) + fw->xmt_data_dma_reg[cnt] = + htonl(RD_REG_DWORD(dmp_reg++)); + + /* Receive DMA registers. */ + iter_reg = fw->rcvt0_data_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7700); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x7710); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->rcvt1_data_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7720); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x7730); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + /* RISC registers. */ + iter_reg = fw->risc_gp_reg; + WRT_REG_DWORD(®->iobase_addr, 0x0F00); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x0F10); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x0F20); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x0F30); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x0F40); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x0F50); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x0F60); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x0F70); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Local memory controller registers. */ + iter_reg = fw->lmc_reg; + WRT_REG_DWORD(®->iobase_addr, 0x3000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x3010); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x3020); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x3030); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x3040); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x3050); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x3060); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Fibre Protocol Module registers. */ + iter_reg = fw->fpm_hdw_reg; + WRT_REG_DWORD(®->iobase_addr, 0x4000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4010); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4020); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4030); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4040); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4050); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4060); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4070); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4080); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4090); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x40A0); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x40B0); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Frame Buffer registers. */ + iter_reg = fw->fb_hdw_reg; + WRT_REG_DWORD(®->iobase_addr, 0x6000); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6010); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6020); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6030); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6040); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6100); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6130); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6150); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6170); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6190); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x61B0); + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); - qla_uprintf(&uiter, "\n\nRISC GP1 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); + /* Reset RISC. */ + WRT_REG_DWORD(®->ctrl_status, + CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); + for (cnt = 0; cnt < 30000; cnt++) { + if ((RD_REG_DWORD(®->ctrl_status) & + CSRX_DMA_ACTIVE) == 0) + break; + + udelay(10); } - qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]); - } - qla_uprintf(&uiter, "\n\nRISC GP2 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); + WRT_REG_DWORD(®->ctrl_status, + CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); + pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); + + udelay(100); + /* Wait for firmware to complete NVRAM accesses. */ + mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0); + for (cnt = 10000 ; cnt && mb[0]; cnt--) { + udelay(5); + mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0); + barrier(); } - qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]); - } - qla_uprintf(&uiter, "\n\nRISC GP3 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); + /* Wait for soft-reset to complete. */ + for (cnt = 0; cnt < 30000; cnt++) { + if ((RD_REG_DWORD(®->ctrl_status) & + CSRX_ISP_SOFT_RESET) == 0) + break; + + udelay(10); } - qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]); + WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); + RD_REG_DWORD(®->hccr); /* PCI Posting. */ } - qla_uprintf(&uiter, "\n\nRISC GP4 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]); + for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && + rval == QLA_SUCCESS; cnt--) { + if (cnt) + udelay(100); + else + rval = QLA_FUNCTION_TIMEOUT; } - qla_uprintf(&uiter, "\n\nRISC GP5 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]); + /* Memory. */ + if (rval == QLA_SUCCESS) { + /* Code RAM. */ + risc_address = 0x20000; + WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED); + clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); } + for (cnt = 0; cnt < sizeof(fw->code_ram) / 4 && rval == QLA_SUCCESS; + cnt++, risc_address++) { + WRT_REG_WORD(®->mailbox1, LSW(risc_address)); + WRT_REG_WORD(®->mailbox8, MSW(risc_address)); + RD_REG_WORD(®->mailbox8); + WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); + + for (timer = 6000000; timer; timer--) { + /* Check for pending interrupts. */ + stat = RD_REG_DWORD(®->host_status); + if (stat & HSRX_RISC_INT) { + stat &= 0xff; + + if (stat == 0x1 || stat == 0x2 || + stat == 0x10 || stat == 0x11) { + set_bit(MBX_INTERRUPT, + &ha->mbx_cmd_flags); + + mb[0] = RD_REG_WORD(®->mailbox0); + mb[2] = RD_REG_WORD(®->mailbox2); + mb[3] = RD_REG_WORD(®->mailbox3); + + WRT_REG_DWORD(®->hccr, + HCCRX_CLR_RISC_INT); + RD_REG_DWORD(®->hccr); + break; + } - qla_uprintf(&uiter, "\n\nRISC GP6 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); + /* Clear this intr; it wasn't a mailbox intr */ + WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); + RD_REG_DWORD(®->hccr); + } + udelay(5); } - qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]); - } - qla_uprintf(&uiter, "\n\nRISC GP7 Registers:"); - for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); + if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { + rval = mb[0] & MBS_MASK; + fw->code_ram[cnt] = htonl((mb[3] << 16) | mb[2]); + } else { + rval = QLA_FUNCTION_FAILED; } - qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]); } - qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:"); - for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); - } - qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]); + if (rval == QLA_SUCCESS) { + /* External Memory. */ + risc_address = 0x100000; + ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1; + WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED); + clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); } + for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS; + cnt++, risc_address++) { + WRT_REG_WORD(®->mailbox1, LSW(risc_address)); + WRT_REG_WORD(®->mailbox8, MSW(risc_address)); + RD_REG_WORD(®->mailbox8); + WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); + + for (timer = 6000000; timer; timer--) { + /* Check for pending interrupts. */ + stat = RD_REG_DWORD(®->host_status); + if (stat & HSRX_RISC_INT) { + stat &= 0xff; + + if (stat == 0x1 || stat == 0x2 || + stat == 0x10 || stat == 0x11) { + set_bit(MBX_INTERRUPT, + &ha->mbx_cmd_flags); + + mb[0] = RD_REG_WORD(®->mailbox0); + mb[2] = RD_REG_WORD(®->mailbox2); + mb[3] = RD_REG_WORD(®->mailbox3); - qla_uprintf(&uiter, "\n\nFPM B0 Registers:"); - for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); + WRT_REG_DWORD(®->hccr, + HCCRX_CLR_RISC_INT); + RD_REG_DWORD(®->hccr); + break; + } + + /* Clear this intr; it wasn't a mailbox intr */ + WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); + RD_REG_DWORD(®->hccr); + } + udelay(5); } - qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]); - } - qla_uprintf(&uiter, "\n\nFPM B1 Registers:"); - for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n"); + if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { + rval = mb[0] & MBS_MASK; + fw->ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]); + } else { + rval = QLA_FUNCTION_FAILED; } - qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]); } - qla_uprintf(&uiter, "\n\nRISC SRAM:"); - for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) { - if (cnt % 8 == 0) { - qla_uprintf(&uiter, "\n%04x: ", cnt + 0x1000); - } - qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]); + if (rval == QLA_SUCCESS) { + eft = qla2xxx_copy_queues(ha, &fw->ext_mem[cnt]); + if (ha->eft) + memcpy(eft, ha->eft, ntohl(ha->fw_dump->eft_size)); } - qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump."); + if (rval != QLA_SUCCESS) { + qla_printk(KERN_WARNING, ha, + "Failed to dump firmware (%x)!!!\n", rval); + ha->fw_dumped = 0; - return; -} + } else { + qla_printk(KERN_INFO, ha, + "Firmware dump saved to temp buffer (%ld/%p).\n", + ha->host_no, ha->fw_dump); + ha->fw_dumped = 1; + } -static int -qla_uprintf(char **uiter, char *fmt, ...) -{ - int iter, len; - char buf[128]; - va_list args; - - va_start(args, fmt); - len = vsprintf(buf, fmt, args); - va_end(args); - - for (iter = 0; iter < len; iter++, *uiter += 1) - *uiter[0] = buf[iter]; - - return (len); +qla24xx_fw_dump_failed: + if (!hardware_locked) + spin_unlock_irqrestore(&ha->hardware_lock, flags); } -//FIXME - /****************************************************************************/ /* Driver Debug Functions. */ /****************************************************************************/ -void -qla2x00_dump_regs(scsi_qla_host_t *ha) +void +qla2x00_dump_regs(scsi_qla_host_t *ha) { - device_reg_t *reg; - - reg = ha->iobase; + struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; printk("Mailbox registers:\n"); printk("scsi(%ld): mbox 0 0x%04x \n", @@ -995,7 +1363,7 @@ qla2x00_dump_regs(scsi_qla_host_t *ha) void -qla2x00_dump_buffer(uint8_t * b, uint32_t size) +qla2x00_dump_buffer(uint8_t * b, uint32_t size) { uint32_t cnt; uint8_t c; @@ -1021,11 +1389,11 @@ qla2x00_dump_buffer(uint8_t * b, uint32_t size) /************************************************************************** * qla2x00_print_scsi_cmd * Dumps out info about the scsi cmd and srb. - * Input + * Input * cmd : struct scsi_cmnd **************************************************************************/ void -qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd) +qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd) { int i; struct scsi_qla_host *ha; @@ -1042,28 +1410,34 @@ qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd) for (i = 0; i < cmd->cmd_len; i++) { printk("0x%02x ", cmd->cmnd[i]); } - printk("\n seg_cnt=%d, allowed=%d, retries=%d, " - "serial_number_at_timeout=0x%lx\n", - cmd->use_sg, cmd->allowed, cmd->retries, - cmd->serial_number_at_timeout); + printk("\n seg_cnt=%d, allowed=%d, retries=%d\n", + cmd->use_sg, cmd->allowed, cmd->retries); printk(" request buffer=0x%p, request buffer len=0x%x\n", cmd->request_buffer, cmd->request_bufflen); printk(" tag=%d, transfersize=0x%x\n", cmd->tag, cmd->transfersize); - printk(" serial_number=%lx, SP=%p\n", cmd->serial_number, sp); + printk(" serial_number=%lx, SP=%p\n", cmd->serial_number, sp); printk(" data direction=%d\n", cmd->sc_data_direction); if (!sp) return; printk(" sp flags=0x%x\n", sp->flags); - printk(" r_start=0x%lx, u_start=0x%lx, f_start=0x%lx, state=%d\n", - sp->r_start, sp->u_start, sp->f_start, sp->state); +} + +void +qla2x00_dump_pkt(void *pkt) +{ + uint32_t i; + uint8_t *data = (uint8_t *) pkt; + + for (i = 0; i < 64; i++) { + if (!(i % 4)) + printk("\n%02x: ", i); - printk(" e_start= 0x%lx, ext_history=%d, fo retry=%d, loopid=%x, " - "port path=%d\n", sp->e_start, sp->ext_history, sp->fo_retry_cnt, - sp->lun_queue->fclun->fcport->loop_id, - sp->lun_queue->fclun->fcport->cur_path); + printk("%02x ", data[i]); + } + printk("\n"); } #if defined(QL_DEBUG_ROUTINES) @@ -1078,8 +1452,8 @@ qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd) * count = number of words. */ void -qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer, - uint8_t wd_size, uint32_t count) +qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer, + uint8_t wd_size, uint32_t count) { uint32_t cnt; uint16_t *buf16;