X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=drivers%2Fvideo%2Friva%2Ffbdev.c;h=b0c886de04043c1ad872377e3739a0f48f3d34a2;hb=f7f1b0f1e2fbadeab12d24236000e778aa9b1ead;hp=fec70246027c71cb5dfd4f18117f8145ab5a0a04;hpb=9bf4aaab3e101692164d49b7ca357651eb691cb6;p=linux-2.6.git diff --git a/drivers/video/riva/fbdev.c b/drivers/video/riva/fbdev.c index fec702460..b0c886de0 100644 --- a/drivers/video/riva/fbdev.c +++ b/drivers/video/riva/fbdev.c @@ -111,177 +111,92 @@ static int rivafb_blank(int blank, struct fb_info *info); * * ------------------------------------------------------------------------- */ -enum riva_chips { - CH_RIVA_128 = 0, - CH_RIVA_TNT, - CH_RIVA_TNT2, - CH_RIVA_UTNT2, - CH_RIVA_VTNT2, - CH_RIVA_UVTNT2, - CH_RIVA_ITNT2, - CH_GEFORCE_SDR, - CH_GEFORCE_DDR, - CH_QUADRO, - CH_GEFORCE2_MX, - CH_GEFORCE2_MX2, - CH_GEFORCE2_GO, - CH_QUADRO2_MXR, - CH_GEFORCE2_GTS, - CH_GEFORCE2_GTS2, - CH_GEFORCE2_ULTRA, - CH_QUADRO2_PRO, - CH_GEFORCE4_MX_460, - CH_GEFORCE4_MX_440, - CH_GEFORCE4_MX_420, - CH_GEFORCE4_440_GO, - CH_GEFORCE4_420_GO, - CH_GEFORCE4_420_GO_M32, - CH_QUADRO4_500XGL, - CH_GEFORCE4_440_GO_M64, - CH_QUADRO4_200, - CH_QUADRO4_550XGL, - CH_QUADRO4_500_GOGL, - CH_IGEFORCE2, - CH_GEFORCE3, - CH_GEFORCE3_1, - CH_GEFORCE3_2, - CH_QUADRO_DDC, - CH_GEFORCE4_TI_4600, - CH_GEFORCE4_TI_4400, - CH_GEFORCE4_TI_4200, - CH_QUADRO4_900XGL, - CH_QUADRO4_750XGL, - CH_QUADRO4_700XGL -}; - -/* directly indexed by riva_chips enum, above */ -static struct riva_chip_info { - const char *name; - unsigned arch_rev; -} riva_chip_info[] __initdata = { - { "RIVA-128", NV_ARCH_03 }, - { "RIVA-TNT", NV_ARCH_04 }, - { "RIVA-TNT2", NV_ARCH_04 }, - { "RIVA-UTNT2", NV_ARCH_04 }, - { "RIVA-VTNT2", NV_ARCH_04 }, - { "RIVA-UVTNT2", NV_ARCH_04 }, - { "RIVA-ITNT2", NV_ARCH_04 }, - { "GeForce-SDR", NV_ARCH_10 }, - { "GeForce-DDR", NV_ARCH_10 }, - { "Quadro", NV_ARCH_10 }, - { "GeForce2-MX", NV_ARCH_10 }, - { "GeForce2-MX", NV_ARCH_10 }, - { "GeForce2-GO", NV_ARCH_10 }, - { "Quadro2-MXR", NV_ARCH_10 }, - { "GeForce2-GTS", NV_ARCH_10 }, - { "GeForce2-GTS", NV_ARCH_10 }, - { "GeForce2-ULTRA", NV_ARCH_10 }, - { "Quadro2-PRO", NV_ARCH_10 }, - { "GeForce4-MX-460", NV_ARCH_10 }, - { "GeForce4-MX-440", NV_ARCH_10 }, - { "GeForce4-MX-420", NV_ARCH_10 }, - { "GeForce4-440-GO", NV_ARCH_10 }, - { "GeForce4-420-GO", NV_ARCH_10 }, - { "GeForce4-420-GO-M32", NV_ARCH_10 }, - { "Quadro4-500-XGL", NV_ARCH_10 }, - { "GeForce4-440-GO-M64", NV_ARCH_10 }, - { "Quadro4-200", NV_ARCH_10 }, - { "Quadro4-550-XGL", NV_ARCH_10 }, - { "Quadro4-500-GOGL", NV_ARCH_10 }, - { "GeForce2", NV_ARCH_10 }, - { "GeForce3", NV_ARCH_20 }, - { "GeForce3 Ti 200", NV_ARCH_20 }, - { "GeForce3 Ti 500", NV_ARCH_20 }, - { "Quadro DDC", NV_ARCH_20 }, - { "GeForce4 Ti 4600", NV_ARCH_20 }, - { "GeForce4 Ti 4400", NV_ARCH_20 }, - { "GeForce4 Ti 4200", NV_ARCH_20 }, - { "Quadro4-900-XGL", NV_ARCH_20 }, - { "Quadro4-750-XGL", NV_ARCH_20 }, - { "Quadro4-700-XGL", NV_ARCH_20 } -}; - static struct pci_device_id rivafb_pci_tbl[] = { { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_128 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT2 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_UTNT2 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_ITNT2 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE_SDR }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE_DDR }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX2 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GO }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_MXR }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS2 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_ULTRA }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_PRO }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_460 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_440 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, + // NF2/IGP version, GeForce 4 MX, NV18 + { PCI_VENDOR_ID_NVIDIA, 0x01f0, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_420 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_440_GO }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_420_GO }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_420_GO_M32 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_500XGL }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_440_GO_M64 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_200 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_550XGL }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_500_GOGL }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_IGEFORCE2 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_1 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_2 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO_DDC }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4600 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4400 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4200 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_900XGL }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_750XGL }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_700XGL }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { 0, } /* terminate list */ }; MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl); @@ -293,24 +208,23 @@ MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl); * ------------------------------------------------------------------------- */ /* command line data, set in rivafb_setup() */ -static u32 pseudo_palette[17]; -static int flatpanel __initdata = -1; /* Autodetect later */ -static int forceCRTC __initdata = -1; +static int flatpanel __devinitdata = -1; /* Autodetect later */ +static int forceCRTC __devinitdata = -1; +static int noaccel __devinitdata = 0; #ifdef CONFIG_MTRR -static int nomtrr __initdata = 0; +static int nomtrr __devinitdata = 0; #endif -static char *mode_option __initdata = NULL; +static char *mode_option __devinitdata = NULL; static int strictmode = 0; -static struct fb_fix_screeninfo rivafb_fix = { - .id = "nVidia", +static struct fb_fix_screeninfo __devinitdata rivafb_fix = { .type = FB_TYPE_PACKED_PIXELS, .xpanstep = 1, .ypanstep = 1, }; -static struct fb_var_screeninfo rivafb_default_var = { +static struct fb_var_screeninfo __devinitdata rivafb_default_var = { .xres = 640, .yres = 480, .xres_virtual = 640, @@ -323,7 +237,6 @@ static struct fb_var_screeninfo rivafb_default_var = { .activate = FB_ACTIVATE_NOW, .height = -1, .width = -1, - .accel_flags = FB_ACCELF_TEXT, .pixclock = 39721, .left_margin = 40, .right_margin = 24, @@ -533,6 +446,10 @@ static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8, int i, j, k = 0; u32 b, tmp; u32 *data = (u32 *)data8; + bg = le16_to_cpu(bg); + fg = le16_to_cpu(fg); + + w = (w + 1) & ~1; for (i = 0; i < h; i++) { b = *data++; @@ -606,7 +523,7 @@ static void riva_rclut(RIVA_HW_INST *chip, unsigned char *green, unsigned char *blue) { - VGA_WR08(chip->PDIO, 0x3c8, regnum); + VGA_WR08(chip->PDIO, 0x3c7, regnum); *red = VGA_RD08(chip->PDIO, 0x3c9); *green = VGA_RD08(chip->PDIO, 0x3c9); *blue = VGA_RD08(chip->PDIO, 0x3c9); @@ -807,7 +724,7 @@ static void riva_load_video_mode(struct fb_info *info) newmode.ext.interlace = 0xff; /* interlace off */ if (par->riva.Architecture >= NV_ARCH_10) - par->riva.CURSOR = (U032 *)(info->screen_base + par->riva.CursorStart); + par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart); if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) newmode.misc_output &= ~0x40; @@ -821,22 +738,27 @@ static void riva_load_video_mode(struct fb_info *info) par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width, hDisplaySize, height, dotClock); - newmode.ext.scale = par->riva.PRAMDAC[0x00000848/4] & 0xfff000ff; + newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) & + 0xfff000ff; if (par->FlatPanel == 1) { newmode.ext.pixel |= (1 << 7); newmode.ext.scale |= (1 << 8); } if (par->SecondCRTC) { - newmode.ext.head = par->riva.PCRTC0[0x00000860/4] & ~0x00001000; - newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] | 0x00001000; + newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) & + ~0x00001000; + newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) | + 0x00001000; newmode.ext.crtcOwner = 3; newmode.ext.pllsel |= 0x20000800; newmode.ext.vpll2 = newmode.ext.vpll; } else if (par->riva.twoHeads) { - newmode.ext.head = par->riva.PCRTC0[0x00000860/4] | 0x00001000; - newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] & ~0x00001000; + newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) | + 0x00001000; + newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) & + ~0x00001000; newmode.ext.crtcOwner = 0; - newmode.ext.vpll2 = par->riva.PRAMDAC0[0x00000520/4]; + newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520); } if (par->FlatPanel == 1) { newmode.ext.pixel |= (1 << 7); @@ -977,14 +899,14 @@ static void riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1) { RIVA_FIFO_FREE(par->riva, Patt, 4); - par->riva.Patt->Color0 = clr0; - par->riva.Patt->Color1 = clr1; - par->riva.Patt->Monochrome[0] = pat0; - par->riva.Patt->Monochrome[1] = pat1; + NV_WR32(&par->riva.Patt->Color0, 0, clr0); + NV_WR32(&par->riva.Patt->Color1, 0, clr1); + NV_WR32(par->riva.Patt->Monochrome, 0, pat0); + NV_WR32(par->riva.Patt->Monochrome, 4, pat1); } /* acceleration routines */ -inline void wait_for_idle(struct riva_par *par) +static inline void wait_for_idle(struct riva_par *par) { while (par->riva.Busy(&par->riva)); } @@ -997,18 +919,19 @@ riva_set_rop_solid(struct riva_par *par, int rop) { riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); RIVA_FIFO_FREE(par->riva, Rop, 1); - par->riva.Rop->Rop3 = rop; + NV_WR32(&par->riva.Rop->Rop3, 0, rop); } -void riva_setup_accel(struct fb_info *info) +static void riva_setup_accel(struct fb_info *info) { struct riva_par *par = (struct riva_par *) info->par; RIVA_FIFO_FREE(par->riva, Clip, 2); - par->riva.Clip->TopLeft = 0x0; - par->riva.Clip->WidthHeight = (info->var.xres_virtual & 0xffff) | - (info->var.yres_virtual << 16); + NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0); + NV_WR32(&par->riva.Clip->WidthHeight, 0, + (info->var.xres_virtual & 0xffff) | + (info->var.yres_virtual << 16)); riva_set_rop_solid(par, 0xcc); wait_for_idle(par); } @@ -1090,14 +1013,14 @@ static int rivafb_open(struct fb_info *info, int user) NVTRACE_ENTER(); if (!cnt) { +#ifdef CONFIG_X86 memset(&par->state, 0, sizeof(struct vgastate)); par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS; /* save the DAC for Riva128 */ if (par->riva.Architecture == NV_ARCH_03) par->state.flags |= VGA_SAVE_CMAP; save_vga(&par->state); - - RivaGetConfig(&par->riva, par->Chipset); +#endif /* vgaHWunlock() + riva unlock (0x7F) */ CRTCout(par, 0x11, 0xFF); par->riva.LockUnlock(&par->riva, 0); @@ -1121,7 +1044,9 @@ static int rivafb_release(struct fb_info *info, int user) par->riva.LockUnlock(&par->riva, 0); par->riva.LoadStateExt(&par->riva, &par->initial_state.ext); riva_load_state(par, &par->initial_state); +#ifdef CONFIG_X86 restore_vga(&par->state); +#endif par->riva.LockUnlock(&par->riva, 1); } atomic_dec(&par->ref_count); @@ -1131,7 +1056,8 @@ static int rivafb_release(struct fb_info *info, int user) static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { - struct fb_monspecs *specs = &info->monspecs; + struct fb_videomode *mode; + struct riva_par *par = (struct riva_par *) info->par; int nom, den; /* translating from pixels->bytes */ int mode_valid = 0; @@ -1148,6 +1074,9 @@ static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) /* fall through */ case 16: var->bits_per_pixel = 16; + /* The Riva128 supports RGB555 only */ + if (par->riva.Architecture == NV_ARCH_03) + var->green.length = 5; if (var->green.length == 5) { /* 0rrrrrgg gggbbbbb */ var->red.offset = 10; @@ -1186,58 +1115,9 @@ static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) } if (!strictmode) { - if (!fb_validate_mode(var, info)) - mode_valid = 1; - } - - /* find best mode from modedb */ - if (!mode_valid && specs->modedb_len) { - int i, best, best_refresh, best_x, best_y, diff_x, diff_y; - - best_refresh = best = best_x = best_y = 0; - diff_x = diff_y = -1; - - for (i = 0; i < specs->modedb_len; i++) { - if (var->xres <= specs->modedb[i].xres && - !(specs->modedb[i].flag & FB_MODE_IS_CALCULATED) && - specs->modedb[i].xres - var->xres < diff_x) { - best_x = specs->modedb[i].xres; - diff_x = best_x - var->xres; - } - if (!diff_x) break; - } - - if (diff_x != -1) { - for (i = 0; i < specs->modedb_len; i++) { - if (best_x == specs->modedb[i].xres && - var->yres <= specs->modedb[i].yres && - !(specs->modedb[i].flag & - FB_MODE_IS_CALCULATED) && - specs->modedb[i].yres-var->yres < diff_y) { - best_y = specs->modedb[i].yres; - diff_y = best_y - var->yres; - } - if (!diff_y) break; - } - } - - if (diff_y != -1) { - for (i = 0; i < specs->modedb_len; i++) { - if (best_x == specs->modedb[i].xres && - best_y == specs->modedb[i].yres && - !(specs->modedb[i].flag & - FB_MODE_IS_CALCULATED) && - specs->modedb[i].refresh > best_refresh) { - best_refresh=specs->modedb[i].refresh; - best = i; - } - } - } - - if (best_refresh) { - riva_update_var(var, &specs->modedb[best]); + if (!info->monspecs.vfmax || !info->monspecs.hfmax || + !info->monspecs.dclkmax || !fb_validate_mode(var, info)) mode_valid = 1; - } } /* calculate modeline if supported by monitor */ @@ -1245,6 +1125,15 @@ static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) mode_valid = 1; } + + if (!mode_valid) { + mode = fb_find_best_mode(var, &info->modelist); + if (mode) { + riva_update_var(var, mode); + mode_valid = 1; + } + } + if (!mode_valid && info->monspecs.modedb_len) return -EINVAL; @@ -1280,19 +1169,22 @@ static int rivafb_set_par(struct fb_info *info) struct riva_par *par = (struct riva_par *) info->par; NVTRACE_ENTER(); - riva_common_setup(par); - RivaGetConfig(&par->riva, par->Chipset); /* vgaHWunlock() + riva unlock (0x7F) */ CRTCout(par, 0x11, 0xFF); par->riva.LockUnlock(&par->riva, 0); - riva_load_video_mode(info); - riva_setup_accel(info); + if(!(info->flags & FBINFO_HWACCEL_DISABLED)) + riva_setup_accel(info); - memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2); + par->cursor_reset = 1; info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3)); info->fix.visual = (info->var.bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; + + if (info->flags & FBINFO_HWACCEL_DISABLED) + info->pixmap.scan_align = 1; + else + info->pixmap.scan_align = 4; NVTRACE_LEAVE(); return 0; } @@ -1356,22 +1248,25 @@ static int rivafb_blank(int blank, struct fb_info *info) vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */ NVTRACE_ENTER(); - if (blank) { + + if (blank) tmp |= 0x20; - switch (blank - 1) { - case VESA_NO_BLANKING: - break; - case VESA_VSYNC_SUSPEND: - vesa |= 0x80; - break; - case VESA_HSYNC_SUSPEND: - vesa |= 0x40; - break; - case VESA_POWERDOWN: - vesa |= 0xc0; - break; - } + + switch (blank) { + case FB_BLANK_UNBLANK: + case FB_BLANK_NORMAL: + break; + case FB_BLANK_VSYNC_SUSPEND: + vesa |= 0x80; + break; + case FB_BLANK_HSYNC_SUSPEND: + vesa |= 0x40; + break; + case FB_BLANK_POWERDOWN: + vesa |= 0xc0; + break; } + SEQout(par, 0x01, tmp); CRTCout(par, 0x1a, vesa); @@ -1382,6 +1277,7 @@ static int rivafb_blank(int blank, struct fb_info *info) #endif NVTRACE_LEAVE(); + return 0; } @@ -1413,7 +1309,7 @@ static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green, int i; if (regno >= riva_get_cmap_len(&info->var)) - return -EINVAL; + return -EINVAL; if (info->var.grayscale) { /* gray = 0.30*R + 0.59*G + 0.11*B */ @@ -1421,6 +1317,31 @@ static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green, (red * 77 + green * 151 + blue * 28) >> 8; } + if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { + ((u32 *) info->pseudo_palette)[regno] = + (regno << info->var.red.offset) | + (regno << info->var.green.offset) | + (regno << info->var.blue.offset); + /* + * The Riva128 2D engine requires color information in + * TrueColor format even if framebuffer is in DirectColor + */ + if (par->riva.Architecture == NV_ARCH_03) { + switch (info->var.bits_per_pixel) { + case 16: + par->palette[regno] = ((red & 0xf800) >> 1) | + ((green & 0xf800) >> 6) | + ((blue & 0xf800) >> 11); + break; + case 32: + par->palette[regno] = ((red & 0xff00) << 8) | + ((green & 0xff00)) | + ((blue & 0xff00) >> 8); + break; + } + } + } + switch (info->var.bits_per_pixel) { case 8: /* "transparent" stuff is completely ignored. */ @@ -1428,45 +1349,27 @@ static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green, break; case 16: if (info->var.green.length == 5) { - if (regno < 16) { - /* 0rrrrrgg gggbbbbb */ - ((u32 *)info->pseudo_palette)[regno] = - ((red & 0xf800) >> 1) | - ((green & 0xf800) >> 6) | - ((blue & 0xf800) >> 11); - } - for (i = 0; i < 8; i++) + for (i = 0; i < 8; i++) { riva_wclut(chip, regno*8+i, red >> 8, green >> 8, blue >> 8); + } } else { u8 r, g, b; - if (regno < 16) { - /* rrrrrggg gggbbbbb */ - ((u32 *)info->pseudo_palette)[regno] = - ((red & 0xf800) >> 0) | - ((green & 0xf800) >> 5) | - ((blue & 0xf800) >> 11); - } if (regno < 32) { for (i = 0; i < 8; i++) { - riva_wclut(chip, regno*8+i, red >> 8, - green >> 8, blue >> 8); + riva_wclut(chip, regno*8+i, + red >> 8, green >> 8, + blue >> 8); } } - for (i = 0; i < 4; i++) { - riva_rclut(chip, regno*2+i, &r, &g, &b); - riva_wclut(chip, regno*4+i, r, green >> 8, b); - } + riva_rclut(chip, regno*4, &r, &g, &b); + for (i = 0; i < 4; i++) + riva_wclut(chip, regno*4+i, r, + green >> 8, b); } break; case 32: - if (regno < 16) { - ((u32 *)info->pseudo_palette)[regno] = - ((red & 0xff00) << 8) | - ((green & 0xff00)) | ((blue & 0xff00) >> 8); - - } riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); break; default: @@ -1493,10 +1396,19 @@ static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect struct riva_par *par = (struct riva_par *) info->par; u_int color, rop = 0; + if ((info->flags & FBINFO_HWACCEL_DISABLED)) { + cfb_fillrect(info, rect); + return; + } + if (info->var.bits_per_pixel == 8) color = rect->color; - else - color = ((u32 *)info->pseudo_palette)[rect->color]; + else { + if (par->riva.Architecture != NV_ARCH_03) + color = ((u32 *)info->pseudo_palette)[rect->color]; + else + color = par->palette[rect->color]; + } switch (rect->rop) { case ROP_XOR: @@ -1511,14 +1423,14 @@ static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect riva_set_rop_solid(par, rop); RIVA_FIFO_FREE(par->riva, Bitmap, 1); - par->riva.Bitmap->Color1A = color; + NV_WR32(&par->riva.Bitmap->Color1A, 0, color); RIVA_FIFO_FREE(par->riva, Bitmap, 2); - par->riva.Bitmap->UnclippedRectangle[0].TopLeft = - (rect->dx << 16) | rect->dy; + NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0, + (rect->dx << 16) | rect->dy); mb(); - par->riva.Bitmap->UnclippedRectangle[0].WidthHeight = - (rect->width << 16) | rect->height; + NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0, + (rect->width << 16) | rect->height); mb(); riva_set_rop_solid(par, 0xcc); @@ -1539,11 +1451,19 @@ static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *regi { struct riva_par *par = (struct riva_par *) info->par; + if ((info->flags & FBINFO_HWACCEL_DISABLED)) { + cfb_copyarea(info, region); + return; + } + RIVA_FIFO_FREE(par->riva, Blt, 3); - par->riva.Blt->TopLeftSrc = (region->sy << 16) | region->sx; - par->riva.Blt->TopLeftDst = (region->dy << 16) | region->dx; + NV_WR32(&par->riva.Blt->TopLeftSrc, 0, + (region->sy << 16) | region->sx); + NV_WR32(&par->riva.Blt->TopLeftDst, 0, + (region->dy << 16) | region->dx); mb(); - par->riva.Blt->WidthHeight = (region->height << 16) | region->width; + NV_WR32(&par->riva.Blt->WidthHeight, 0, + (region->height << 16) | region->width); mb(); } @@ -1578,10 +1498,10 @@ static void rivafb_imageblit(struct fb_info *info, struct riva_par *par = (struct riva_par *) info->par; u32 fgx = 0, bgx = 0, width, tmp; u8 *cdat = (u8 *) image->data; - volatile u32 *d; + volatile u32 __iomem *d; int i, size; - if (image->depth != 1) { + if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) { cfb_imageblit(info, image); return; } @@ -1592,31 +1512,33 @@ static void rivafb_imageblit(struct fb_info *info, bgx = image->bg_color; break; case 16: - fgx = ((u32 *)info->pseudo_palette)[image->fg_color]; - bgx = ((u32 *)info->pseudo_palette)[image->bg_color]; + case 32: + if (par->riva.Architecture != NV_ARCH_03) { + fgx = ((u32 *)info->pseudo_palette)[image->fg_color]; + bgx = ((u32 *)info->pseudo_palette)[image->bg_color]; + } else { + fgx = par->palette[image->fg_color]; + bgx = par->palette[image->bg_color]; + } if (info->var.green.length == 6) convert_bgcolor_16(&bgx); break; - case 32: - fgx = ((u32 *)info->pseudo_palette)[image->fg_color]; - bgx = ((u32 *)info->pseudo_palette)[image->bg_color]; - break; } RIVA_FIFO_FREE(par->riva, Bitmap, 7); - par->riva.Bitmap->ClipE.TopLeft = - (image->dy << 16) | (image->dx & 0xFFFF); - par->riva.Bitmap->ClipE.BottomRight = + NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0, + (image->dy << 16) | (image->dx & 0xFFFF)); + NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0, (((image->dy + image->height) << 16) | - ((image->dx + image->width) & 0xffff)); - par->riva.Bitmap->Color0E = bgx; - par->riva.Bitmap->Color1E = fgx; - par->riva.Bitmap->WidthHeightInE = - (image->height << 16) | ((image->width + 31) & ~31); - par->riva.Bitmap->WidthHeightOutE = - (image->height << 16) | ((image->width + 31) & ~31); - par->riva.Bitmap->PointE = - (image->dy << 16) | (image->dx & 0xFFFF); + ((image->dx + image->width) & 0xffff))); + NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx); + NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx); + NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0, + (image->height << 16) | ((image->width + 31) & ~31)); + NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0, + (image->height << 16) | ((image->width + 31) & ~31)); + NV_WR32(&par->riva.Bitmap->PointE, 0, + (image->dy << 16) | (image->dx & 0xFFFF)); d = &par->riva.Bitmap->MonochromeData01E; @@ -1628,7 +1550,7 @@ static void rivafb_imageblit(struct fb_info *info, tmp = *((u32 *)cdat); cdat = (u8 *)((u32 *)cdat + 1); reverse_order(&tmp); - d[i] = tmp; + NV_WR32(d, i*4, tmp); } size -= 16; } @@ -1638,7 +1560,7 @@ static void rivafb_imageblit(struct fb_info *info, tmp = *((u32 *) cdat); cdat = (u8 *)((u32 *)cdat + 1); reverse_order(&tmp); - d[i] = tmp; + NV_WR32(d, i*4, tmp); } } } @@ -1661,77 +1583,86 @@ static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor) struct riva_par *par = (struct riva_par *) info->par; u8 data[MAX_CURS * MAX_CURS/8]; u16 fg, bg; - int i; + int i, set = cursor->set; + + if (cursor->image.width > MAX_CURS || + cursor->image.height > MAX_CURS) + return soft_cursor(info, cursor); par->riva.ShowHideCursor(&par->riva, 0); - if (cursor->set & FB_CUR_SETPOS) { + if (par->cursor_reset) { + set = FB_CUR_SETALL; + par->cursor_reset = 0; + } + + if (set & FB_CUR_SETSIZE) + memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2); + + if (set & FB_CUR_SETPOS) { u32 xx, yy, temp; - info->cursor.image.dx = cursor->image.dx; - info->cursor.image.dy = cursor->image.dy; yy = cursor->image.dy - info->var.yoffset; xx = cursor->image.dx - info->var.xoffset; temp = xx & 0xFFFF; temp |= yy << 16; - par->riva.PRAMDAC[0x0000300/4] = temp; - } - - if (cursor->set & FB_CUR_SETSIZE) { - info->cursor.image.height = cursor->image.height; - info->cursor.image.width = cursor->image.width; - memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2); + NV_WR32(par->riva.PRAMDAC, 0x0000300, temp); } - if (cursor->set & FB_CUR_SETCMAP) { - info->cursor.image.bg_color = cursor->image.bg_color; - info->cursor.image.fg_color = cursor->image.fg_color; - } - if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETCUR)) { - u32 bg_idx = info->cursor.image.bg_color; - u32 fg_idx = info->cursor.image.fg_color; - u32 s_pitch = (info->cursor.image.width+7) >> 3; + if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { + u32 bg_idx = cursor->image.bg_color; + u32 fg_idx = cursor->image.fg_color; + u32 s_pitch = (cursor->image.width+7) >> 3; u32 d_pitch = MAX_CURS/8; u8 *dat = (u8 *) cursor->image.data; - u8 *msk = (u8 *) info->cursor.mask; - u8 src[64]; - - info->cursor.image.data = cursor->image.data; - switch (info->cursor.rop) { - case ROP_XOR: - for (i = 0; i < s_pitch * info->cursor.image.height; - i++) - src[i] = dat[i] ^ msk[i]; - break; - case ROP_COPY: - default: - for (i = 0; i < s_pitch * info->cursor.image.height; - i++) - src[i] = dat[i] & msk[i]; - break; - } + u8 *msk = (u8 *) cursor->mask; + u8 *src; - fb_sysmove_buf_aligned(info, &info->sprite, data, d_pitch, src, - s_pitch, info->cursor.image.height); + src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC); + + if (src) { + switch (cursor->rop) { + case ROP_XOR: + for (i = 0; i < s_pitch * cursor->image.height; + i++) + src[i] = dat[i] ^ msk[i]; + break; + case ROP_COPY: + default: + for (i = 0; i < s_pitch * cursor->image.height; + i++) + src[i] = dat[i] & msk[i]; + break; + } - bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | - ((info->cmap.green[bg_idx] & 0xf8) << 2) | - ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15; + fb_sysmove_buf_aligned(info, &info->pixmap, data, + d_pitch, src, s_pitch, + cursor->image.height); - fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | - ((info->cmap.green[fg_idx] & 0xf8) << 2) | - ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15; + bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | + ((info->cmap.green[bg_idx] & 0xf8) << 2) | + ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | + 1 << 15; - par->riva.LockUnlock(&par->riva, 0); + fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | + ((info->cmap.green[fg_idx] & 0xf8) << 2) | + ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | + 1 << 15; + + par->riva.LockUnlock(&par->riva, 0); - rivafb_load_cursor_image(par, data, bg, fg, - info->cursor.image.width, - info->cursor.image.height); + rivafb_load_cursor_image(par, data, bg, fg, + cursor->image.width, + cursor->image.height); + kfree(src); + } } - if (info->cursor.enable) + + if (cursor->enable) par->riva.ShowHideCursor(&par->riva, 1); + return 0; } @@ -1769,6 +1700,7 @@ static struct fb_ops riva_fb_ops = { static int __devinit riva_set_fbinfo(struct fb_info *info) { unsigned int cmap_len; + struct riva_par *par = (struct riva_par *) info->par; NVTRACE_ENTER(); info->flags = FBINFO_DEFAULT @@ -1776,19 +1708,25 @@ static int __devinit riva_set_fbinfo(struct fb_info *info) | FBINFO_HWACCEL_YPAN | FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT - | FBINFO_HWACCEL_IMAGEBLIT - | FBINFO_MISC_MODESWITCHLATE; + | FBINFO_HWACCEL_IMAGEBLIT; + + /* Accel seems to not work properly on NV30 yet...*/ + if ((par->riva.Architecture == NV_ARCH_30) || noaccel) { + printk(KERN_DEBUG PFX "disabling acceleration\n"); + info->flags |= FBINFO_HWACCEL_DISABLED; + } + info->var = rivafb_default_var; info->fix.visual = (info->var.bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; - info->pseudo_palette = pseudo_palette; + + info->pseudo_palette = par->pseudo_palette; cmap_len = riva_get_cmap_len(&info->var); fb_alloc_cmap(&info->cmap, cmap_len, 0); - info->pixmap.size = 64 * 1024; + info->pixmap.size = 8 * 1024; info->pixmap.buf_align = 4; - info->pixmap.scan_align = 4; info->pixmap.flags = FB_PIXMAP_SYSTEM; info->var.yres_virtual = -1; NVTRACE_LEAVE(); @@ -1796,7 +1734,7 @@ static int __devinit riva_set_fbinfo(struct fb_info *info) } #ifdef CONFIG_PPC_OF -static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd) +static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd) { struct riva_par *par = (struct riva_par *) info->par; struct device_node *dp; @@ -1818,17 +1756,41 @@ static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd) pedid = (unsigned char *) get_property(dp, propnames[i], NULL); if (pedid != NULL) { - par->EDID = pedid; - return 1; + par->EDID = pedid; + NVTRACE("LCD found.\n"); + return 1; } } } NVTRACE_LEAVE(); - return 0; + return 0; } #endif /* CONFIG_PPC_OF */ -static void riva_update_default_var(struct fb_var_screeninfo *var, struct fb_info *info) +#if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF) +static int __devinit riva_get_EDID_i2c(struct fb_info *info) +{ + struct riva_par *par = (struct riva_par *) info->par; + struct fb_var_screeninfo var; + int i; + + NVTRACE_ENTER(); + riva_create_i2c_busses(par); + for (i = 0; i < par->bus; i++) { + riva_probe_i2c_connector(par, i+1, &par->EDID); + if (par->EDID && !fb_parse_edid(par->EDID, &var)) { + printk(PFX "Found EDID Block from BUS %i\n", i); + break; + } + } + + NVTRACE_LEAVE(); + return (par->EDID) ? 1 : 0; +} +#endif /* CONFIG_FB_RIVA_I2C */ + +static void __devinit riva_update_default_var(struct fb_var_screeninfo *var, + struct fb_info *info) { struct fb_monspecs *specs = &info->monspecs; struct fb_videomode modedb; @@ -1857,46 +1819,32 @@ static void riva_update_default_var(struct fb_var_screeninfo *var, struct fb_inf var->bits_per_pixel = 8; riva_update_var(var, &modedb); } - var->accel_flags |= FB_ACCELF_TEXT; NVTRACE_LEAVE(); } -static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev) +static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev) { - struct riva_par *par; - int i; - NVTRACE_ENTER(); #ifdef CONFIG_PPC_OF if (!riva_get_EDID_OF(info, pdev)) - printk("rivafb: could not retrieve EDID from OF\n"); -#else - /* XXX use other methods later */ -#ifdef CONFIG_FB_RIVA_I2C - - par = (struct riva_par *) info->par; - riva_create_i2c_busses(par); - for (i = par->bus; i >= 1; i--) { - riva_probe_i2c_connector(par, i, &par->EDID); - if (par->EDID) { - printk("rivafb: Found EDID Block from BUS %i\n", i); - break; - } - } - riva_delete_i2c_busses(par); -#endif + printk(PFX "could not retrieve EDID from OF\n"); +#elif CONFIG_FB_RIVA_I2C + if (!riva_get_EDID_i2c(info)) + printk(PFX "could not retrieve EDID from DDC/I2C\n"); #endif NVTRACE_LEAVE(); } -static void riva_get_edidinfo(struct fb_info *info) +static void __devinit riva_get_edidinfo(struct fb_info *info) { struct fb_var_screeninfo *var = &rivafb_default_var; struct riva_par *par = (struct riva_par *) info->par; fb_edid_to_monspecs(par->EDID, &info->monspecs); + fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len, + &info->modelist); riva_update_default_var(var, info); /* if user specified flatpanel, we respect that */ @@ -1910,50 +1858,104 @@ static void riva_get_edidinfo(struct fb_info *info) * * ------------------------------------------------------------------------- */ +static u32 __devinit riva_get_arch(struct pci_dev *pd) +{ + u32 arch = 0; + + switch (pd->device & 0x0ff0) { + case 0x0100: /* GeForce 256 */ + case 0x0110: /* GeForce2 MX */ + case 0x0150: /* GeForce2 */ + case 0x0170: /* GeForce4 MX */ + case 0x0180: /* GeForce4 MX (8x AGP) */ + case 0x01A0: /* nForce */ + case 0x01F0: /* nForce2 */ + arch = NV_ARCH_10; + break; + case 0x0200: /* GeForce3 */ + case 0x0250: /* GeForce4 Ti */ + case 0x0280: /* GeForce4 Ti (8x AGP) */ + arch = NV_ARCH_20; + break; + case 0x0300: /* GeForceFX 5800 */ + case 0x0310: /* GeForceFX 5600 */ + case 0x0320: /* GeForceFX 5200 */ + case 0x0330: /* GeForceFX 5900 */ + case 0x0340: /* GeForceFX 5700 */ + arch = NV_ARCH_30; + break; + case 0x0020: /* TNT, TNT2 */ + arch = NV_ARCH_04; + break; + case 0x0010: /* Riva128 */ + arch = NV_ARCH_03; + break; + default: /* unknown architecture */ + break; + } + return arch; +} + static int __devinit rivafb_probe(struct pci_dev *pd, const struct pci_device_id *ent) { - struct riva_chip_info *rci = &riva_chip_info[ent->driver_data]; struct riva_par *default_par; struct fb_info *info; + int ret; NVTRACE_ENTER(); assert(pd != NULL); - assert(rci != NULL); - - info = kmalloc(sizeof(struct fb_info), GFP_KERNEL); - if (!info) - goto err_out; - - default_par = kmalloc(sizeof(struct riva_par), GFP_KERNEL); - if (!default_par) - goto err_out_kfree; - memset(info, 0, sizeof(struct fb_info)); - memset(default_par, 0, sizeof(struct riva_par)); + info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev); + if (!info) { + printk (KERN_ERR PFX "could not allocate memory\n"); + ret = -ENOMEM; + goto err_ret; + } + default_par = (struct riva_par *) info->par; default_par->pdev = pd; - info->pixmap.addr = kmalloc(64 * 1024, GFP_KERNEL); - if (info->pixmap.addr == NULL) - goto err_out_kfree1; - memset(info->pixmap.addr, 0, 64 * 1024); + info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL); + if (info->pixmap.addr == NULL) { + ret = -ENOMEM; + goto err_framebuffer_release; + } + memset(info->pixmap.addr, 0, 8 * 1024); - if (pci_enable_device(pd)) { + ret = pci_enable_device(pd); + if (ret < 0) { printk(KERN_ERR PFX "cannot enable PCI device\n"); - goto err_out_enable; + goto err_free_pixmap; } - if (pci_request_regions(pd, "rivafb")) { + ret = pci_request_regions(pd, "rivafb"); + if (ret < 0) { printk(KERN_ERR PFX "cannot request PCI regions\n"); - goto err_out_request; + goto err_disable_device; } - strcat(rivafb_fix.id, rci->name); - default_par->riva.Architecture = rci->arch_rev; + default_par->riva.Architecture = riva_get_arch(pd); default_par->Chipset = (pd->vendor << 16) | pd->device; printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset); +#ifdef CONFIG_PCI_NAMES + printk(KERN_INFO PFX "%s\n", pd->pretty_name); +#endif + + if(default_par->riva.Architecture == 0) { + printk(KERN_ERR PFX "unknown NV_ARCH\n"); + ret=-ENODEV; + goto err_release_region; + } + if(default_par->riva.Architecture == NV_ARCH_10 || + default_par->riva.Architecture == NV_ARCH_20 || + default_par->riva.Architecture == NV_ARCH_30) { + sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); + } else { + sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture); + } + default_par->FlatPanel = flatpanel; if (flatpanel == 1) printk(KERN_INFO PFX "flatpanel support enabled\n"); @@ -1978,11 +1980,10 @@ static int __devinit rivafb_probe(struct pci_dev *pd, rivafb_fix.mmio_len); if (!default_par->ctrl_base) { printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); - goto err_out_free_base0; + ret = -EIO; + goto err_release_region; } - info->par = default_par; - switch (default_par->riva.Architecture) { case NV_ARCH_03: /* Riva128's PRAMIN is in the "framebuffer" space @@ -1992,35 +1993,35 @@ static int __devinit rivafb_probe(struct pci_dev *pd, default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000); if (!default_par->riva.PRAMIN) { printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n"); - goto err_out_free_nv3_pramin; + ret = -EIO; + goto err_iounmap_ctrl_base; } - rivafb_fix.accel = FB_ACCEL_NV3; - default_par->bus = 1; break; case NV_ARCH_04: case NV_ARCH_10: case NV_ARCH_20: - default_par->riva.PCRTC0 = (unsigned *)(default_par->ctrl_base + 0x00600000); - default_par->riva.PRAMIN = (unsigned *)(default_par->ctrl_base + 0x00710000); - rivafb_fix.accel = FB_ACCEL_NV4; - default_par->bus = 2; + case NV_ARCH_30: + default_par->riva.PCRTC0 = + (u32 __iomem *)(default_par->ctrl_base + 0x00600000); + default_par->riva.PRAMIN = + (u32 __iomem *)(default_par->ctrl_base + 0x00710000); break; } - riva_common_setup(default_par); if (default_par->riva.Architecture == NV_ARCH_03) { - default_par->riva.PCRTC = default_par->riva.PCRTC0 = default_par->riva.PGRAPH; + default_par->riva.PCRTC = default_par->riva.PCRTC0 + = default_par->riva.PGRAPH; } rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024; default_par->dclk_max = riva_get_maxdclk(default_par) * 1000; - info->screen_base = ioremap(rivafb_fix.smem_start, rivafb_fix.smem_len); if (!info->screen_base) { printk(KERN_ERR PFX "cannot ioremap FB base\n"); - goto err_out_free_base1; + ret = -EIO; + goto err_iounmap_pramin; } #ifdef CONFIG_MTRR @@ -2043,24 +2044,27 @@ static int __devinit rivafb_probe(struct pci_dev *pd, riva_get_EDID(info, pd); riva_get_edidinfo(info); - if (riva_set_fbinfo(info) < 0) { + ret=riva_set_fbinfo(info); + if (ret < 0) { printk(KERN_ERR PFX "error setting initial video mode\n"); - goto err_out_iounmap_fb; + goto err_iounmap_screen_base; } - if (register_framebuffer(info) < 0) { + fb_destroy_modedb(info->monspecs.modedb); + info->monspecs.modedb = NULL; + ret = register_framebuffer(info); + if (ret < 0) { printk(KERN_ERR PFX "error registering riva framebuffer\n"); - goto err_out_iounmap_fb; + goto err_iounmap_screen_base; } pci_set_drvdata(pd, info); printk(KERN_INFO PFX - "PCI nVidia NV%x framebuffer ver %s (%s, %dMB @ 0x%lX)\n", - default_par->riva.Architecture, - RIVAFB_VERSION, + "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n", info->fix.id, + RIVAFB_VERSION, info->fix.smem_len / (1024 * 1024), info->fix.smem_start); #ifdef CONFIG_PMAC_BACKLIGHT @@ -2071,25 +2075,26 @@ static int __devinit rivafb_probe(struct pci_dev *pd, NVTRACE_LEAVE(); return 0; -err_out_iounmap_fb: +err_iounmap_screen_base: +#ifdef CONFIG_FB_RIVA_I2C + riva_delete_i2c_busses((struct riva_par *) info->par); +#endif iounmap(info->screen_base); -err_out_free_base1: +err_iounmap_pramin: if (default_par->riva.Architecture == NV_ARCH_03) - iounmap((caddr_t)default_par->riva.PRAMIN); -err_out_free_nv3_pramin: + iounmap(default_par->riva.PRAMIN); +err_iounmap_ctrl_base: iounmap(default_par->ctrl_base); -err_out_free_base0: +err_release_region: pci_release_regions(pd); -err_out_request: +err_disable_device: pci_disable_device(pd); -err_out_enable: +err_free_pixmap: kfree(info->pixmap.addr); -err_out_kfree1: - kfree(default_par); -err_out_kfree: - kfree(info); -err_out: - return -ENODEV; +err_framebuffer_release: + framebuffer_release(info); +err_ret: + return ret; } static void __exit rivafb_remove(struct pci_dev *pd) @@ -2101,6 +2106,11 @@ static void __exit rivafb_remove(struct pci_dev *pd) if (!info) return; +#ifdef CONFIG_FB_RIVA_I2C + riva_delete_i2c_busses(par); + kfree(par->EDID); +#endif + unregister_framebuffer(info); #ifdef CONFIG_MTRR if (par->mtrr.vram_valid) @@ -2111,13 +2121,11 @@ static void __exit rivafb_remove(struct pci_dev *pd) iounmap(par->ctrl_base); iounmap(info->screen_base); if (par->riva.Architecture == NV_ARCH_03) - iounmap((caddr_t)par->riva.PRAMIN); + iounmap(par->riva.PRAMIN); pci_release_regions(pd); pci_disable_device(pd); - fb_destroy_modedb(info->monspecs.modedb); kfree(info->pixmap.addr); - kfree(par); - kfree(info); + framebuffer_release(info); pci_set_drvdata(pd, NULL); NVTRACE_LEAVE(); } @@ -2129,7 +2137,7 @@ static void __exit rivafb_remove(struct pci_dev *pd) * ------------------------------------------------------------------------- */ #ifndef MODULE -int __init rivafb_setup(char *options) +static int __init rivafb_setup(char *options) { char *this_opt; @@ -2154,6 +2162,8 @@ int __init rivafb_setup(char *options) #endif } else if (!strncmp(this_opt, "strictmode", 10)) { strictmode = 1; + } else if (!strncmp(this_opt, "noaccel", 7)) { + noaccel = 1; } else mode_option = this_opt; } @@ -2177,36 +2187,42 @@ static struct pci_driver rivafb_driver = { * * ------------------------------------------------------------------------- */ -int __init rivafb_init(void) +static int __devinit rivafb_init(void) { - if (pci_register_driver(&rivafb_driver) > 0) - return 0; - pci_unregister_driver(&rivafb_driver); - return -ENODEV; +#ifndef MODULE + char *option = NULL; + + if (fb_get_options("rivafb", &option)) + return -ENODEV; + rivafb_setup(option); +#endif + return pci_register_driver(&rivafb_driver); } +module_init(rivafb_init); + #ifdef MODULE static void __exit rivafb_exit(void) { pci_unregister_driver(&rivafb_driver); } -module_init(rivafb_init); module_exit(rivafb_exit); +#endif /* MODULE */ -MODULE_PARM(flatpanel, "i"); +module_param(noaccel, bool, 0); +MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); +module_param(flatpanel, int, 0); MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)"); -MODULE_PARM(forceCRTC, "i"); +module_param(forceCRTC, int, 0); MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)"); - #ifdef CONFIG_MTRR -MODULE_PARM(nomtrr, "i"); +module_param(nomtrr, bool, 0); MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)"); -MODULE_PARM(strictmode, "i"); -MODULE_PARM_DESC(strictmode, "Only use video modes from EDID"); #endif -#endif /* MODULE */ +module_param(strictmode, bool, 0); +MODULE_PARM_DESC(strictmode, "Only use video modes from EDID"); MODULE_AUTHOR("Ani Joshi, maintainer"); MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");