X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=include%2Fasm-arm%2Farch-ixp2000%2Fixp2000-regs.h;h=6c56708d0ff0c98a4e484330a447c30b6ad76524;hb=f7f1b0f1e2fbadeab12d24236000e778aa9b1ead;hp=99dd524eaecba119da326fef0f413eae0f607108;hpb=e3f6fb6212a7102bdb56ba38fa1e98fe72950475;p=linux-2.6.git diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h index 99dd524ea..6c56708d0 100644 --- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h +++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h @@ -19,41 +19,57 @@ #define _IXP2000_REGS_H_ /* - * Static I/O regions. The manual defines each region as being several - * MB in size, but all the registers are within the first 4K, so there's - * no purpose in mapping the whole region in. + * Static I/O regions. + * + * Most of the registers are clumped in 4K regions spread throughout + * the 0xc0000000 -> 0xc0100000 address range, but we just map in + * the whole range using a single 1 MB section instead of small + * 4K pages. This has two advantages for us: + * + * 1) We use only one TLB entry for large number of on-chip I/O devices. + * + * 2) We can easily set the Section attributes to XCB=101 on the IXP2400 + * as required per erratum #66. We accomplish this by using a + * new MT_IXP2000_DEVICE memory type with the bits set as required. + * + * CAP stands for CSR Access Proxy. + * + * If you change the virtual address of this mapping, please propagate + * the change to arch/arm/kernel/debug.S, which hardcodes the virtual + * address of the UART located in this region. */ -#define IXP2000_SLOWPORT_CSR_PHYS_BASE 0xc0080000 -#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfefff000 -#define IXP2000_SLOWPORT_CSR_SIZE 0x1000 -#define IXP2000_GLOBAL_REG_PHYS_BASE 0xc0004000 -#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfeffe000 -#define IXP2000_GLOBAL_REG_SIZE 0x1000 +#define IXP2000_CAP_PHYS_BASE 0xc0000000 +#define IXP2000_CAP_VIRT_BASE 0xfef00000 +#define IXP2000_CAP_SIZE 0x00100000 +/* + * Addresses for specific on-chip peripherals + */ +#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000 +#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000 #define IXP2000_UART_PHYS_BASE 0xc0030000 #define IXP2000_UART_VIRT_BASE 0xfef30000 -#define IXP2000_UART_SIZE 0x1000 - -#define IXP2000_TIMER_PHYS_BASE 0xc0020000 -#define IXP2000_TIMER_VIRT_BASE 0xfeffc000 -#define IXP2000_TIMER_SIZE 0x1000 - -#define IXP2000_GPIO_PHYS_BASE 0xc0010000 -#define IXP2000_GPIO_VIRT_BASE 0xfeffb000 -#define IXP2000_GPIO_SIZE 0x1000 +#define IXP2000_TIMER_VIRT_BASE 0xfef20000 +#define IXP2000_GPIO_VIRT_BASE 0Xfef10000 +/* + * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual + * addresses of the INTCTL and PCI_CSR mappings are hardcoded in + * entry-macro.S, so if you ever change these please propagate + * the change. + */ #define IXP2000_INTCTL_PHYS_BASE 0xd6000000 -#define IXP2000_INTCTL_VIRT_BASE 0xfeffa000 -#define IXP2000_INTCTL_SIZE 0x01000 +#define IXP2000_INTCTL_VIRT_BASE 0xfee00000 +#define IXP2000_INTCTL_SIZE 0x00100000 #define IXP2000_PCI_CREG_PHYS_BASE 0xde000000 -#define IXP2000_PCI_CREG_VIRT_BASE 0xfeff0000 -#define IXP2000_PCI_CREG_SIZE 0x1000 +#define IXP2000_PCI_CREG_VIRT_BASE 0xfed00000 +#define IXP2000_PCI_CREG_SIZE 0x00100000 #define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000 -#define IXP2000_PCI_CSR_VIRT_BASE 0xfefde000 -#define IXP2000_PCI_CSR_SIZE 0x1000 +#define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000 +#define IXP2000_PCI_CSR_SIZE 0x00100000 #define IXP2000_PCI_IO_PHYS_BASE 0xd8000000 #define IXP2000_PCI_IO_VIRT_BASE 0xfd000000 @@ -67,7 +83,6 @@ #define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000 #define IXP2000_PCI_CFG1_SIZE 0x01000000 - /* * Timers */ @@ -113,6 +128,30 @@ #define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c) #define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30) #define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34) +#define IXP2000_IRQ_THD_RAW_STATUS_A_0 IXP2000_INTCTL_REG(0x60) +#define IXP2000_IRQ_THD_RAW_STATUS_A_1 IXP2000_INTCTL_REG(0x64) +#define IXP2000_IRQ_THD_RAW_STATUS_A_2 IXP2000_INTCTL_REG(0x68) +#define IXP2000_IRQ_THD_RAW_STATUS_A_3 IXP2000_INTCTL_REG(0x6c) +#define IXP2000_IRQ_THD_RAW_STATUS_B_0 IXP2000_INTCTL_REG(0x80) +#define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84) +#define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88) +#define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c) +#define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160) +#define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164) +#define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168) +#define IXP2000_IRQ_THD_ENABLE_SET_A_3 IXP2000_INTCTL_REG(0x16c) +#define IXP2000_IRQ_THD_ENABLE_SET_B_0 IXP2000_INTCTL_REG(0x180) +#define IXP2000_IRQ_THD_ENABLE_SET_B_1 IXP2000_INTCTL_REG(0x184) +#define IXP2000_IRQ_THD_ENABLE_SET_B_2 IXP2000_INTCTL_REG(0x188) +#define IXP2000_IRQ_THD_ENABLE_SET_B_3 IXP2000_INTCTL_REG(0x18c) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0 IXP2000_INTCTL_REG(0x1e0) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1 IXP2000_INTCTL_REG(0x1e4) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2 IXP2000_INTCTL_REG(0x1e8) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3 IXP2000_INTCTL_REG(0x1ec) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0 IXP2000_INTCTL_REG(0x200) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1 IXP2000_INTCTL_REG(0x204) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2 IXP2000_INTCTL_REG(0x208) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3 IXP2000_INTCTL_REG(0x20c) /* * Mask of valid IRQs in the 32-bit IRQ register. We use @@ -195,7 +234,7 @@ #define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */ #define IXP2000_PCICNTL_PCF (1<<28) /* PCI Centrolfunction bit */ -#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */ +#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */ /* These are from the IRQ register in the PCI ISR register */ #define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */