X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=include%2Fasm-arm%2Farch-ixp4xx%2Fio.h;h=0d517267fb63edf0d49809fd64c701629e2c1d41;hb=97bf2856c6014879bd04983a3e9dfcdac1e7fe85;hp=942b622455bc438ad2a164580ce190c03bcdeea4;hpb=76828883507a47dae78837ab5dec5a5b4513c667;p=linux-2.6.git

diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index 942b62245..0d517267f 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -38,7 +38,7 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
  * 2) If > 64MB of memory space is required, the IXP4xx can be configured
  *    to use indirect registers to access PCI (as we do below for I/O
  *    transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
- *    of memory on the bus. The disadvantadge of this is that every 
+ *    of memory on the bus. The disadvantage of this is that every 
  *    PCI access requires three local register accesses plus a spinlock,
  *    but in some cases the performance hit is acceptable. In addition,
  *    you cannot mmap() PCI devices in this case.
@@ -260,6 +260,12 @@ out:
 
 #endif
 
+#ifndef CONFIG_PCI
+
+#define	__io(v)		v
+
+#else
+
 /*
  * IXP4xx does not have a transparent cpu -> PCI I/O translation
  * window.  Instead, it has a set of registers that must be tweaked
@@ -578,6 +584,7 @@ __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
 
 #define	ioport_map(port, nr)		((void __iomem*)(port + PIO_OFFSET))
 #define	ioport_unmap(addr)
+#endif	// !CONFIG_PCI
 
 #endif	//  __ASM_ARM_ARCH_IO_H