X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=include%2Fasm-arm%2Fassembler.h;h=f31ac92b6c7f1c0f69dc90e861a0bad367ff6c5e;hb=987b0145d94eecf292d8b301228356f44611ab7c;hp=d53bafa9bf1c58f80fffdb2910571d3544340e1d;hpb=9464c7cf61b9433057924c36e6e02f303a00e768;p=linux-2.6.git

diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index d53bafa9b..f31ac92b6 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -79,34 +79,17 @@
 #define RETINSTR(instr, regs...)\
 	instr	regs
 
-/*
- * Enable and disable interrupts
- */
-#if __LINUX_ARM_ARCH__ >= 6
-	.macro	disable_irq
-	cpsid	i
-	.endm
-
-	.macro	enable_irq
-	cpsie	i
-	.endm
-#else
-	.macro	disable_irq
-	msr	cpsr_c, #PSR_I_BIT | SVC_MODE
-	.endm
-
-	.macro	enable_irq
-	msr	cpsr_c, #SVC_MODE
-	.endm
-#endif
-
 /*
  * Save the current IRQ state and disable IRQs.  Note that this macro
  * assumes FIQs are enabled, and that the processor is in SVC mode.
  */
 	.macro	save_and_disable_irqs, oldcpsr
 	mrs	\oldcpsr, cpsr
-	disable_irq
+#if __LINUX_ARM_ARCH__ >= 6
+	cpsid	i
+#else
+	msr	cpsr_c, #PSR_I_BIT | MODE_SVC
+#endif
 	.endm
 
 /*