X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=include%2Fasm-arm%2Fassembler.h;h=fce8328208258bcd64cae06279608a8d4008f347;hb=97bf2856c6014879bd04983a3e9dfcdac1e7fe85;hp=f31ac92b6c7f1c0f69dc90e861a0bad367ff6c5e;hpb=76828883507a47dae78837ab5dec5a5b4513c667;p=linux-2.6.git

diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index f31ac92b6..fce832820 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -55,29 +55,26 @@
 #define PLD(code...)
 #endif
 
-#define MODE_USR	USR_MODE
-#define MODE_FIQ	FIQ_MODE
-#define MODE_IRQ	IRQ_MODE
-#define MODE_SVC	SVC_MODE
-
-#define DEFAULT_FIQ	MODE_FIQ
-
 /*
- * LOADREGS - ldm with PC in register list (eg, ldmfd sp!, {pc})
+ * Enable and disable interrupts
  */
-#ifdef __STDC__
-#define LOADREGS(cond, base, reglist...)\
-	ldm##cond	base,reglist
+#if __LINUX_ARM_ARCH__ >= 6
+	.macro	disable_irq
+	cpsid	i
+	.endm
+
+	.macro	enable_irq
+	cpsie	i
+	.endm
 #else
-#define LOADREGS(cond, base, reglist...)\
-	ldm/**/cond	base,reglist
-#endif
+	.macro	disable_irq
+	msr	cpsr_c, #PSR_I_BIT | SVC_MODE
+	.endm
 
-/*
- * Build a return instruction for this processor type.
- */
-#define RETINSTR(instr, regs...)\
-	instr	regs
+	.macro	enable_irq
+	msr	cpsr_c, #SVC_MODE
+	.endm
+#endif
 
 /*
  * Save the current IRQ state and disable IRQs.  Note that this macro
@@ -85,11 +82,7 @@
  */
 	.macro	save_and_disable_irqs, oldcpsr
 	mrs	\oldcpsr, cpsr
-#if __LINUX_ARM_ARCH__ >= 6
-	cpsid	i
-#else
-	msr	cpsr_c, #PSR_I_BIT | MODE_SVC
-#endif
+	disable_irq
 	.endm
 
 /*
@@ -100,18 +93,6 @@
 	msr	cpsr_c, \oldcpsr
 	.endm
 
-/*
- * These two are used to save LR/restore PC over a user-based access.
- * The old 26-bit architecture requires that we do.  On 32-bit
- * architecture, we can safely ignore this requirement.
- */
-	.macro	save_lr
-	.endm
-
-	.macro	restore_pc
-	mov	pc, lr
-	.endm
-
 #define USER(x...)				\
 9999:	x;					\
 	.section __ex_table,"a";		\