X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=include%2Fasm-arm%2Fio.h;h=b3479fc1cc8f33ab2090eaf3431424bee027e3a6;hb=43bc926fffd92024b46cafaf7350d669ba9ca884;hp=658ffa384fdab980edae60e9a48df8bfd8979b96;hpb=cee37fe97739d85991964371c1f3a745c00dd236;p=linux-2.6.git diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index 658ffa384..b3479fc1c 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -26,7 +26,6 @@ #include #include #include -#include /* * ISA I/O bus memory addresses are 1:1 with the physical address. @@ -43,9 +42,9 @@ extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen); extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen); extern void __raw_writesl(void __iomem *addr, const void *data, int longlen); -extern void __raw_readsb(void __iomem *addr, void *data, int bytelen); -extern void __raw_readsw(void __iomem *addr, void *data, int wordlen); -extern void __raw_readsl(void __iomem *addr, void *data, int longlen); +extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen); +extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen); +extern void __raw_readsl(const void __iomem *addr, void *data, int longlen); #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v)) #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)) @@ -55,6 +54,17 @@ extern void __raw_readsl(void __iomem *addr, void *data, int longlen); #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) #define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a)) +/* + * Architecture ioremap implementation. + * + * __ioremap takes CPU physical address. + * + * __ioremap_pfn takes a Page Frame Number and an offset into that page + */ +extern void __iomem * __ioremap_pfn(unsigned long, unsigned long, size_t, unsigned long); +extern void __iomem * __ioremap(unsigned long, size_t, unsigned long); +extern void __iounmap(void __iomem *addr); + /* * Bad read/write accesses... */ @@ -82,7 +92,7 @@ extern void __readwrite_bug(const char *fn); * only. Their primary purpose is to access PCI and ISA peripherals. * * Note that for a big endian machine, this implies that the following - * big endian mode connectivity is in place, as described by numerious + * big endian mode connectivity is in place, as described by numerous * ARM documents: * * PCI: D0-D7 D8-D15 D16-D23 D24-D31 @@ -136,9 +146,9 @@ extern void __readwrite_bug(const char *fn); /* * String version of IO memory access ops: */ -extern void _memcpy_fromio(void *, void __iomem *, size_t); -extern void _memcpy_toio(void __iomem *, const void *, size_t); -extern void _memset_io(void __iomem *, int, size_t); +extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t); +extern void _memcpy_toio(volatile void __iomem *, const void *, size_t); +extern void _memset_io(volatile void __iomem *, int, size_t); #define mmiowb() @@ -215,63 +225,54 @@ out: #endif /* __mem_pci */ -/* - * If this architecture has ISA IO, then define the isa_read/isa_write - * macros. - */ -#ifdef __mem_isa - -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) -#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) -#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) -#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) -#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - eth_copy_and_sum((a),__mem_isa(b),(c),(d)) - -#else /* __mem_isa */ - -#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) -#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) -#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) -#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") -#define isa_writew(val,addr) __readwrite_bug("isa_writew") -#define isa_writel(val,addr) __readwrite_bug("isa_writel") -#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") -#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") -#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - __readwrite_bug("isa_eth_io_copy_and_sum") - -#endif /* __mem_isa */ - /* * ioremap and friends. * * ioremap takes a PCI memory address, as specified in * Documentation/IO-mapping.txt. + * */ -extern void __iomem * __ioremap(unsigned long, size_t, unsigned long, unsigned long); -extern void __iounmap(void __iomem *addr); - #ifndef __arch_ioremap -#define ioremap(cookie,size) __ioremap(cookie,size,0,1) -#define ioremap_nocache(cookie,size) __ioremap(cookie,size,0,1) -#define ioremap_cached(cookie,size) __ioremap(cookie,size,L_PTE_CACHEABLE,1) +#define ioremap(cookie,size) __ioremap(cookie,size,0) +#define ioremap_nocache(cookie,size) __ioremap(cookie,size,0) +#define ioremap_cached(cookie,size) __ioremap(cookie,size,L_PTE_CACHEABLE) #define iounmap(cookie) __iounmap(cookie) #else -#define ioremap(cookie,size) __arch_ioremap((cookie),(size),0,1) -#define ioremap_nocache(cookie,size) __arch_ioremap((cookie),(size),0,1) -#define ioremap_cached(cookie,size) __arch_ioremap((cookie),(size),L_PTE_CACHEABLE,1) +#define ioremap(cookie,size) __arch_ioremap((cookie),(size),0) +#define ioremap_nocache(cookie,size) __arch_ioremap((cookie),(size),0) +#define ioremap_cached(cookie,size) __arch_ioremap((cookie),(size),L_PTE_CACHEABLE) #define iounmap(cookie) __arch_iounmap(cookie) #endif +/* + * io{read,write}{8,16,32} macros + */ +#ifndef ioread8 +#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; }) +#define ioread16(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; }) +#define ioread32(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; }) + +#define iowrite8(v,p) __raw_writeb(v, p) +#define iowrite16(v,p) __raw_writew(cpu_to_le16(v), p) +#define iowrite32(v,p) __raw_writel(cpu_to_le32(v), p) + +#define ioread8_rep(p,d,c) __raw_readsb(p,d,c) +#define ioread16_rep(p,d,c) __raw_readsw(p,d,c) +#define ioread32_rep(p,d,c) __raw_readsl(p,d,c) + +#define iowrite8_rep(p,s,c) __raw_writesb(p,s,c) +#define iowrite16_rep(p,s,c) __raw_writesw(p,s,c) +#define iowrite32_rep(p,s,c) __raw_writesl(p,s,c) + +extern void __iomem *ioport_map(unsigned long port, unsigned int nr); +extern void ioport_unmap(void __iomem *addr); +#endif + +struct pci_dev; + +extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen); +extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); + /* * can the hardware map this into one segment or not, given no other * constraints.