X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=include%2Fasm-ia64%2Fpci.h;h=5160233bbfac3a35f660174f01302f647e4cb55b;hb=refs%2Fheads%2Fvserver;hp=86f7e8ee139960fd4ab3f9eb9f116623bd712d5c;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h index 86f7e8ee1..5160233bb 100644 --- a/include/asm-ia64/pci.h +++ b/include/asm-ia64/pci.h @@ -26,16 +26,18 @@ void pcibios_config_init(void); struct pci_dev; /* - * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct correspondence - * between device bus addresses and CPU physical addresses. Platforms with a hardware I/O - * MMU _must_ turn this off to suppress the bounce buffer handling code in the block and - * network device layers. Platforms with separate bus address spaces _must_ turn this off - * and provide a device DMA mapping implementation that takes care of the necessary + * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct + * correspondence between device bus addresses and CPU physical addresses. + * Platforms with a hardware I/O MMU _must_ turn this off to suppress the + * bounce buffer handling code in the block and network device layers. + * Platforms with separate bus address spaces _must_ turn this off and provide + * a device DMA mapping implementation that takes care of the necessary * address translation. * - * For now, the ia64 platforms which may have separate/multiple bus address spaces all - * have I/O MMUs which support the merging of physically discontiguous buffers, so we can - * use that as the sole factor to determine the setting of PCI_DMA_BUS_IS_PHYS. + * For now, the ia64 platforms which may have separate/multiple bus address + * spaces all have I/O MMUs which support the merging of physically + * discontiguous buffers, so we can use that as the sole factor to determine + * the setting of PCI_DMA_BUS_IS_PHYS. */ extern unsigned long ia64_max_iommu_merge_mask; #define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL) @@ -47,14 +49,11 @@ pcibios_set_master (struct pci_dev *dev) } static inline void -pcibios_penalize_isa_irq (int irq) +pcibios_penalize_isa_irq (int irq, int active) { /* We don't do dynamic PCI IRQ allocation */ } -#define HAVE_ARCH_PCI_MWI 1 -extern int pcibios_prep_mwi (struct pci_dev *); - #include /* pci_unmap_{single,page} is not a nop, thus... */ @@ -79,12 +78,42 @@ extern int pcibios_prep_mwi (struct pci_dev *); #define pci_dac_dma_sync_single_for_cpu(dev,dma_addr,len,dir) do { } while (0) #define pci_dac_dma_sync_single_for_device(dev,dma_addr,len,dir) do { mb(); } while (0) -#define sg_dma_len(sg) ((sg)->dma_length) -#define sg_dma_address(sg) ((sg)->dma_address) +#ifdef CONFIG_PCI +static inline void pci_dma_burst_advice(struct pci_dev *pdev, + enum pci_dma_burst_strategy *strat, + unsigned long *strategy_parameter) +{ + unsigned long cacheline_size; + u8 byte; + + pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); + if (byte == 0) + cacheline_size = 1024; + else + cacheline_size = (int) byte * 4; + + *strat = PCI_DMA_BURST_MULTIPLE; + *strategy_parameter = cacheline_size; +} +#endif #define HAVE_PCI_MMAP extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); +#define HAVE_PCI_LEGACY +extern int pci_mmap_legacy_page_range(struct pci_bus *bus, + struct vm_area_struct *vma); +extern ssize_t pci_read_legacy_io(struct kobject *kobj, char *buf, loff_t off, + size_t count); +extern ssize_t pci_write_legacy_io(struct kobject *kobj, char *buf, loff_t off, + size_t count); +extern int pci_mmap_legacy_mem(struct kobject *kobj, + struct bin_attribute *attr, + struct vm_area_struct *vma); + +#define pci_get_legacy_mem platform_pci_get_legacy_mem +#define pci_legacy_read platform_pci_legacy_read +#define pci_legacy_write platform_pci_legacy_write struct pci_window { struct resource resource; @@ -95,6 +124,7 @@ struct pci_controller { void *acpi_handle; void *iommu; int segment; + int node; /* nearest node with memory or -1 for global allocation */ unsigned int windows; struct pci_window *window; @@ -105,21 +135,42 @@ struct pci_controller { #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata) #define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment) -static inline int pci_name_bus(char *name, struct pci_bus *bus) +extern struct pci_ops pci_root_ops; + +static inline int pci_proc_domain(struct pci_bus *bus) { - if (pci_domain_nr(bus) == 0) { - sprintf(name, "%02x", bus->number); - } else { - sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number); - } - return 0; + return (pci_domain_nr(bus) != 0); } static inline void pcibios_add_platform_entries(struct pci_dev *dev) { } -/* generic pci stuff */ -#include +extern void pcibios_resource_to_bus(struct pci_dev *dev, + struct pci_bus_region *region, struct resource *res); + +extern void pcibios_bus_to_resource(struct pci_dev *dev, + struct resource *res, struct pci_bus_region *region); + +static inline struct resource * +pcibios_select_root(struct pci_dev *pdev, struct resource *res) +{ + struct resource *root = NULL; + + if (res->flags & IORESOURCE_IO) + root = &ioport_resource; + if (res->flags & IORESOURCE_MEM) + root = &iomem_resource; + + return root; +} + +#define pcibios_scan_all_fns(a, b) 0 + +#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ +static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) +{ + return channel ? 15 : 14; +} #endif /* _ASM_IA64_PCI_H */