X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=include%2Fasm-mips%2Fhazards.h;h=dadc05188db717c288ab9ecd6a86d483e4731119;hb=43bc926fffd92024b46cafaf7350d669ba9ca884;hp=f524eaccd5f1d26a168a6a12cde8688b98a217fb;hpb=cee37fe97739d85991964371c1f3a745c00dd236;p=linux-2.6.git diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index f524eaccd..dadc05188 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -3,7 +3,9 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) MIPS Technologies, Inc. + * written by Ralf Baechle */ #ifndef _ASM_HAZARDS_H #define _ASM_HAZARDS_H @@ -98,15 +100,16 @@ #else /* __ASSEMBLY__ */ __asm__( - " .macro _ssnop \n\t" - " sll $0, $2, 1 \n\t" - " .endm \n\t" - " \n\t" - " .macro _ehb \n\t" - " sll $0, $0, 3 \n\t" - " .endm \n\t"); + " .macro _ssnop \n" + " sll $0, $0, 1 \n" + " .endm \n" + " \n" + " .macro _ehb \n" + " sll $0, $0, 3 \n" + " .endm \n"); #ifdef CONFIG_CPU_RM9000 + /* * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent * use of the JTLB for instructions should not occur for 4 cpu cycles and use @@ -115,15 +118,22 @@ __asm__( #define mtc0_tlbw_hazard() \ __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \ - ".set\tmips0") + " .set mips32 \n" \ + " _ssnop \n" \ + " _ssnop \n" \ + " _ssnop \n" \ + " _ssnop \n" \ + " .set mips0 \n") #define tlbw_use_hazard() \ __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \ - ".set\tmips0") + " .set mips32 \n" \ + " _ssnop \n" \ + " _ssnop \n" \ + " _ssnop \n" \ + " _ssnop \n" \ + " .set mips0 \n") + #else /* @@ -131,44 +141,43 @@ __asm__( */ #define mtc0_tlbw_hazard() \ __asm__ __volatile__( \ - ".set noreorder\n\t" \ - "nop; nop; nop; nop; nop; nop;\n\t" \ - ".set reorder\n\t") + " .set noreorder \n" \ + " nop \n" \ + " nop \n" \ + " nop \n" \ + " nop \n" \ + " nop \n" \ + " nop \n" \ + " .set reorder \n") #define tlbw_use_hazard() \ __asm__ __volatile__( \ - ".set noreorder\n\t" \ - "nop; nop; nop; nop; nop; nop;\n\t" \ - ".set reorder\n\t") + " .set noreorder \n" \ + " nop \n" \ + " nop \n" \ + " nop \n" \ + " nop \n" \ + " nop \n" \ + " nop \n" \ + " .set reorder \n") #endif /* - * mtc0->mfc0 hazard - * The 24K has a 2 cycle mtc0/mfc0 execution hazard. - * It is a MIPS32R2 processor so ehb will clear the hazard. + * Interrupt enable/disable hazards + * Some processors have hazards when modifying + * the status register to change the interrupt state */ #ifdef CONFIG_CPU_MIPSR2 -/* - * Use a macro for ehb unless explicit support for MIPSR2 is enabled - */ -__asm__( - " .macro\tirq_enable_hazard \n\t" - " _ehb \n\t" - " .endm \n\t" - " \n\t" - " .macro\tirq_disable_hazard \n\t" - " _ehb \n\t" - " .endm"); -#define irq_enable_hazard() \ - __asm__ __volatile__( \ - "_ehb\t\t\t\t# irq_enable_hazard") - -#define irq_disable_hazard() \ - __asm__ __volatile__( \ - "_ehb\t\t\t\t# irq_disable_hazard") +__asm__(" .macro irq_enable_hazard \n" + " _ehb \n" + " .endm \n" + " \n" + " .macro irq_disable_hazard \n" + " _ehb \n" + " .endm \n"); #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) @@ -177,14 +186,11 @@ __asm__( */ __asm__( - " .macro\tirq_enable_hazard \n\t" - " .endm \n\t" - " \n\t" - " .macro\tirq_disable_hazard \n\t" - " .endm"); - -#define irq_enable_hazard() do { } while (0) -#define irq_disable_hazard() do { } while (0) + " .macro irq_enable_hazard \n" + " .endm \n" + " \n" + " .macro irq_disable_hazard \n" + " .endm \n"); #else @@ -195,23 +201,91 @@ __asm__( */ __asm__( - " # \n\t" - " # There is a hazard but we do not care \n\t" - " # \n\t" - " .macro\tirq_enable_hazard \n\t" - " .endm \n\t" - " \n\t" - " .macro\tirq_disable_hazard \n\t" - " _ssnop; _ssnop; _ssnop \n\t" - " .endm"); + " # \n" + " # There is a hazard but we do not care \n" + " # \n" + " .macro\tirq_enable_hazard \n" + " .endm \n" + " \n" + " .macro\tirq_disable_hazard \n" + " _ssnop \n" + " _ssnop \n" + " _ssnop \n" + " .endm \n"); -#define irq_enable_hazard() do { } while (0) +#endif + +#define irq_enable_hazard() \ + __asm__ __volatile__("irq_enable_hazard") #define irq_disable_hazard() \ + __asm__ __volatile__("irq_disable_hazard") + + +/* + * Back-to-back hazards - + * + * What is needed to separate a move to cp0 from a subsequent read from the + * same cp0 register? + */ +#ifdef CONFIG_CPU_MIPSR2 + +__asm__(" .macro back_to_back_c0_hazard \n" + " _ehb \n" + " .endm \n"); + +#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \ + defined(CONFIG_CPU_SB1) + +__asm__(" .macro back_to_back_c0_hazard \n" + " .endm \n"); + +#else + +__asm__(" .macro back_to_back_c0_hazard \n" + " .set noreorder \n" + " _ssnop \n" + " _ssnop \n" + " _ssnop \n" + " .set reorder \n" + " .endm"); + +#endif + +#define back_to_back_c0_hazard() \ + __asm__ __volatile__("back_to_back_c0_hazard") + + +/* + * Instruction execution hazard + */ +#ifdef CONFIG_CPU_MIPSR2 +/* + * gcc has a tradition of misscompiling the previous construct using the + * address of a label as argument to inline assembler. Gas otoh has the + * annoying difference between la and dla which are only usable for 32-bit + * rsp. 64-bit code, so can't be used without conditional compilation. + * The alterantive is switching the assembler to 64-bit code which happens + * to work right even for 32-bit code ... + */ +#define instruction_hazard() \ +do { \ + unsigned long tmp; \ + \ __asm__ __volatile__( \ - "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard") + " .set mips64r2 \n" \ + " dla %0, 1f \n" \ + " jr.hb %0 \n" \ + " .set mips0 \n" \ + "1: \n" \ + : "=r" (tmp)); \ +} while (0) +#else +#define instruction_hazard() do { } while (0) #endif +extern void mips_ihb(void); + #endif /* __ASSEMBLY__ */ #endif /* _ASM_HAZARDS_H */