X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=include%2Fasm-mips%2Fstackframe.h;h=c4856a874965f3ad851808c9ec7886fd45bcd2a7;hb=9464c7cf61b9433057924c36e6e02f303a00e768;hp=158a4cd12e460a0dfb7a4a5ee56fc25ee28008f2;hpb=41689045f6a3cbe0550e1d34e9cc20d2e8c432ba;p=linux-2.6.git diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index 158a4cd12..c4856a874 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -10,6 +10,7 @@ #ifndef _ASM_STACKFRAME_H #define _ASM_STACKFRAME_H +#include #include #include @@ -304,7 +305,7 @@ mfc0 v0, CP0_TCSTATUS ori v0, TCSTATUS_IXMT mtc0 v0, CP0_TCSTATUS - _ehb + ehb DMT 5 # dmt a1 jal mips_ihb #endif /* CONFIG_MIPS_MT_SMTC */ @@ -325,14 +326,14 @@ * restore TCStatus.IXMT. */ LONG_L v1, PT_TCSTATUS(sp) - _ehb + ehb mfc0 v0, CP0_TCSTATUS andi v1, TCSTATUS_IXMT /* We know that TCStatua.IXMT should be set from above */ xori v0, v0, TCSTATUS_IXMT or v0, v0, v1 mtc0 v0, CP0_TCSTATUS - _ehb + ehb andi a1, a1, VPECONTROL_TE beqz a1, 1f emt @@ -411,7 +412,7 @@ /* Clear TKSU, leave IXMT */ xori t0, 0x00001800 mtc0 t0, CP0_TCSTATUS - _ehb + ehb /* We need to leave the global IE bit set, but clear EXL...*/ mfc0 t0, CP0_STATUS ori t0, ST0_EXL | ST0_ERL @@ -438,7 +439,7 @@ * and enable interrupts only for the * current TC, using the TCStatus register. */ - _ehb + ehb mfc0 t0,CP0_TCSTATUS /* Fortunately CU 0 is in the same place in both registers */ /* Set TCU0, TKSU (for later inversion) and IXMT */ @@ -447,7 +448,7 @@ /* Clear TKSU *and* IXMT */ xori t0, 0x00001c00 mtc0 t0, CP0_TCSTATUS - _ehb + ehb /* We need to leave the global IE bit set, but clear EXL...*/ mfc0 t0, CP0_STATUS ori t0, ST0_EXL @@ -479,7 +480,7 @@ andi v1, v0, TCSTATUS_IXMT ori v0, TCSTATUS_IXMT mtc0 v0, CP0_TCSTATUS - _ehb + ehb DMT 2 # dmt v0 /* * We don't know a priori if ra is "live" @@ -495,7 +496,7 @@ xori t0, 0x1e mtc0 t0, CP0_STATUS #ifdef CONFIG_MIPS_MT_SMTC - _ehb + ehb andi v0, v0, VPECONTROL_TE beqz v0, 2f nop /* delay slot */