X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=include%2Fasm-parisc%2Fatomic.h;h=48bf9b8ab8ff7fe0f22c049712993881d429c79f;hb=refs%2Fheads%2Fvserver;hp=4b04759ec6770e8efabc3975015500b2d41517ab;hpb=9213980e6a70d8473e0ffd4b39ab5b6caaba9ff5;p=linux-2.6.git diff --git a/include/asm-parisc/atomic.h b/include/asm-parisc/atomic.h index 4b04759ec..48bf9b8ab 100644 --- a/include/asm-parisc/atomic.h +++ b/include/asm-parisc/atomic.h @@ -1,9 +1,12 @@ +/* Copyright (C) 2000 Philipp Rumpf + * Copyright (C) 2006 Kyle McMartin + */ + #ifndef _ASM_PARISC_ATOMIC_H_ #define _ASM_PARISC_ATOMIC_H_ -#include +#include #include -/* Copyright (C) 2000 Philipp Rumpf . */ /* * Atomic operations that C can't guarantee us. Useful for @@ -14,10 +17,9 @@ */ #ifdef CONFIG_SMP +#include #include /* we use L1_CACHE_BYTES */ -typedef spinlock_t atomic_lock_t; - /* Use an array of spinlocks for our atomic_ts. * Hash function to index into a different SPINLOCK. * Since "a" is usually an address, use one spinlock per cacheline. @@ -25,46 +27,28 @@ typedef spinlock_t atomic_lock_t; # define ATOMIC_HASH_SIZE 4 # define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ])) -extern atomic_lock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; +extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; -static inline void atomic_spin_lock(atomic_lock_t *a) -{ - while (__ldcw(a) == 0) - while (a->lock[0] == 0); -} +/* Can't use raw_spin_lock_irq because of #include problems, so + * this is the substitute */ +#define _atomic_spin_lock_irqsave(l,f) do { \ + raw_spinlock_t *s = ATOMIC_HASH(l); \ + local_irq_save(f); \ + __raw_spin_lock(s); \ +} while(0) + +#define _atomic_spin_unlock_irqrestore(l,f) do { \ + raw_spinlock_t *s = ATOMIC_HASH(l); \ + __raw_spin_unlock(s); \ + local_irq_restore(f); \ +} while(0) -static inline void atomic_spin_unlock(atomic_lock_t *a) -{ - a->lock[0] = 1; -} #else -# define ATOMIC_HASH_SIZE 1 -# define ATOMIC_HASH(a) (0) -# define atomic_spin_lock(x) (void)(x) -# define atomic_spin_unlock(x) do { } while(0) +# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0) +# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0) #endif -/* copied from and modified */ -#define atomic_spin_lock_irqsave(lock, flags) do { \ - local_irq_save(flags); \ - atomic_spin_lock(lock); \ -} while (0) - -#define atomic_spin_unlock_irqrestore(lock, flags) do { \ - atomic_spin_unlock(lock); \ - local_irq_restore(flags); \ -} while (0) - -/* Note that we need not lock read accesses - aligned word writes/reads - * are atomic, so a reader never sees unconsistent values. - * - * Cache-line alignment would conflict with, for example, linux/module.h - */ - -typedef struct { volatile long counter; } atomic_t; - - /* This should get optimized out since it's never called. ** Or get a link error if xchg is used "wrong". */ @@ -79,10 +63,9 @@ extern unsigned long __xchg64(unsigned long, unsigned long *); #endif /* optimizer better get rid of switch since size is a constant */ -static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr, - int size) +static __inline__ unsigned long +__xchg(unsigned long x, __volatile__ void * ptr, int size) { - switch(size) { #ifdef __LP64__ case 8: return __xchg64(x,(unsigned long *) ptr); @@ -139,7 +122,13 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size) (unsigned long)_n_, sizeof(*(ptr))); \ }) +/* Note that we need not lock read accesses - aligned word writes/reads + * are atomic, so a reader never sees unconsistent values. + * + * Cache-line alignment would conflict with, for example, linux/module.h + */ +typedef struct { volatile int counter; } atomic_t; /* It's possible to reduce all atomic operations to either * __atomic_add_return, atomic_set and atomic_read (the latter @@ -150,22 +139,22 @@ static __inline__ int __atomic_add_return(int i, atomic_t *v) { int ret; unsigned long flags; - atomic_spin_lock_irqsave(ATOMIC_HASH(v), flags); + _atomic_spin_lock_irqsave(v, flags); ret = (v->counter += i); - atomic_spin_unlock_irqrestore(ATOMIC_HASH(v), flags); + _atomic_spin_unlock_irqrestore(v, flags); return ret; } static __inline__ void atomic_set(atomic_t *v, int i) { unsigned long flags; - atomic_spin_lock_irqsave(ATOMIC_HASH(v), flags); + _atomic_spin_lock_irqsave(v, flags); v->counter = i; - atomic_spin_unlock_irqrestore(ATOMIC_HASH(v), flags); + _atomic_spin_unlock_irqrestore(v, flags); } static __inline__ int atomic_read(const atomic_t *v) @@ -174,6 +163,27 @@ static __inline__ int atomic_read(const atomic_t *v) } /* exported interface */ +#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) + +/** + * atomic_add_unless - add unless the number is a given value + * @v: pointer of type atomic_t + * @a: the amount to add to v... + * @u: ...unless v is equal to u. + * + * Atomically adds @a to @v, so long as it was not @u. + * Returns non-zero if @v was not @u, and zero otherwise. + */ +#define atomic_add_unless(v, a, u) \ +({ \ + int c, old; \ + c = atomic_read(v); \ + while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \ + c = old; \ + c != (u); \ +}) +#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) #define atomic_add(i,v) ((void)(__atomic_add_return( ((int)i),(v)))) #define atomic_sub(i,v) ((void)(__atomic_add_return(-((int)i),(v)))) @@ -199,11 +209,69 @@ static __inline__ int atomic_read(const atomic_t *v) #define atomic_dec_and_test(v) (atomic_dec_return(v) == 0) -#define ATOMIC_INIT(i) { (i) } +#define atomic_sub_and_test(i,v) (atomic_sub_return((i),(v)) == 0) + +#define ATOMIC_INIT(i) ((atomic_t) { (i) }) #define smp_mb__before_atomic_dec() smp_mb() #define smp_mb__after_atomic_dec() smp_mb() #define smp_mb__before_atomic_inc() smp_mb() #define smp_mb__after_atomic_inc() smp_mb() -#endif +#ifdef __LP64__ + +typedef struct { volatile s64 counter; } atomic64_t; + +#define ATOMIC64_INIT(i) ((atomic64_t) { (i) }) + +static __inline__ int +__atomic64_add_return(s64 i, atomic64_t *v) +{ + int ret; + unsigned long flags; + _atomic_spin_lock_irqsave(v, flags); + + ret = (v->counter += i); + + _atomic_spin_unlock_irqrestore(v, flags); + return ret; +} + +static __inline__ void +atomic64_set(atomic64_t *v, s64 i) +{ + unsigned long flags; + _atomic_spin_lock_irqsave(v, flags); + + v->counter = i; + + _atomic_spin_unlock_irqrestore(v, flags); +} + +static __inline__ s64 +atomic64_read(const atomic64_t *v) +{ + return v->counter; +} + +#define atomic64_add(i,v) ((void)(__atomic64_add_return( ((s64)i),(v)))) +#define atomic64_sub(i,v) ((void)(__atomic64_add_return(-((s64)i),(v)))) +#define atomic64_inc(v) ((void)(__atomic64_add_return( 1,(v)))) +#define atomic64_dec(v) ((void)(__atomic64_add_return( -1,(v)))) + +#define atomic64_add_return(i,v) (__atomic64_add_return( ((s64)i),(v))) +#define atomic64_sub_return(i,v) (__atomic64_add_return(-((s64)i),(v))) +#define atomic64_inc_return(v) (__atomic64_add_return( 1,(v))) +#define atomic64_dec_return(v) (__atomic64_add_return( -1,(v))) + +#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0) + +#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0) +#define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0) +#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i),(v)) == 0) + +#endif /* __LP64__ */ + +#include + +#endif /* _ASM_PARISC_ATOMIC_H_ */