X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=include%2Fasm-ppc%2Fmpc52xx.h;h=76e4402f701f92321b023306ac4a6f073239e4ef;hb=c7b5ebbddf7bcd3651947760f423e3783bbe6573;hp=4fb6e572b841ca4206ef92b27cd6adf184ec59f1;hpb=a2c21200f1c81b08cb55e417b68150bba439b646;p=linux-2.6.git diff --git a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h index 4fb6e572b..76e4402f7 100644 --- a/include/asm-ppc/mpc52xx.h +++ b/include/asm-ppc/mpc52xx.h @@ -42,6 +42,7 @@ struct ocp_def; #define MPC52xx_MBAR_VIRT 0xf0000000 /* Virt address */ #define MPC52xx_MMAP_CTL (MPC52xx_MBAR + 0x0000) +#define MPC52xx_SDRAM (MPC52xx_MBAR + 0x0100) #define MPC52xx_CDM (MPC52xx_MBAR + 0x0200) #define MPC52xx_SFTRST (MPC52xx_MBAR + 0x0220) #define MPC52xx_SFTRST_BIT 0x01000000 @@ -51,6 +52,7 @@ struct ocp_def; #define MPC52xx_MSCAN1 (MPC52xx_MBAR + 0x0900) #define MPC52xx_MSCAN2 (MPC52xx_MBAR + 0x0980) #define MPC52xx_GPIO (MPC52xx_MBAR + 0x0b00) +#define MPC52xx_GPIO_WKUP (MPC52xx_MBAR + 0x0c00) #define MPC52xx_PCI (MPC52xx_MBAR + 0x0d00) #define MPC52xx_USB_OHCI (MPC52xx_MBAR + 0x1000) #define MPC52xx_SDMA (MPC52xx_MBAR + 0x1200) @@ -71,10 +73,6 @@ struct ocp_def; /* SRAM used for SDMA */ #define MPC52xx_SRAM (MPC52xx_MBAR + 0x8000) #define MPC52xx_SRAM_SIZE (16*1024) -#define MPC52xx_SDMA_MAX_TASKS 16 - - /* Memory allocation block size */ -#define MPC52xx_SDRAM_UNIT 0x8000 /* 32K byte */ /* ======================================================================== */ @@ -137,206 +135,240 @@ struct ocp_def; /* Memory Mapping Control */ struct mpc52xx_mmap_ctl { - volatile u32 mbar; /* MMAP_CTRL + 0x00 */ - - volatile u32 cs0_start; /* MMAP_CTRL + 0x04 */ - volatile u32 cs0_stop; /* MMAP_CTRL + 0x08 */ - volatile u32 cs1_start; /* MMAP_CTRL + 0x0c */ - volatile u32 cs1_stop; /* MMAP_CTRL + 0x10 */ - volatile u32 cs2_start; /* MMAP_CTRL + 0x14 */ - volatile u32 cs2_stop; /* MMAP_CTRL + 0x18 */ - volatile u32 cs3_start; /* MMAP_CTRL + 0x1c */ - volatile u32 cs3_stop; /* MMAP_CTRL + 0x20 */ - volatile u32 cs4_start; /* MMAP_CTRL + 0x24 */ - volatile u32 cs4_stop; /* MMAP_CTRL + 0x28 */ - volatile u32 cs5_start; /* MMAP_CTRL + 0x2c */ - volatile u32 cs5_stop; /* MMAP_CTRL + 0x30 */ - - volatile u32 sdram0; /* MMAP_CTRL + 0x34 */ - volatile u32 sdram1; /* MMAP_CTRL + 0X38 */ - - volatile u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */ - - volatile u32 boot_start; /* MMAP_CTRL + 0x4c */ - volatile u32 boot_stop; /* MMAP_CTRL + 0x50 */ - - volatile u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */ - - volatile u32 cs6_start; /* MMAP_CTRL + 0x58 */ - volatile u32 cs6_stop; /* MMAP_CTRL + 0x5c */ - volatile u32 cs7_start; /* MMAP_CTRL + 0x60 */ - volatile u32 cs7_stop; /* MMAP_CTRL + 0x60 */ + u32 mbar; /* MMAP_CTRL + 0x00 */ + + u32 cs0_start; /* MMAP_CTRL + 0x04 */ + u32 cs0_stop; /* MMAP_CTRL + 0x08 */ + u32 cs1_start; /* MMAP_CTRL + 0x0c */ + u32 cs1_stop; /* MMAP_CTRL + 0x10 */ + u32 cs2_start; /* MMAP_CTRL + 0x14 */ + u32 cs2_stop; /* MMAP_CTRL + 0x18 */ + u32 cs3_start; /* MMAP_CTRL + 0x1c */ + u32 cs3_stop; /* MMAP_CTRL + 0x20 */ + u32 cs4_start; /* MMAP_CTRL + 0x24 */ + u32 cs4_stop; /* MMAP_CTRL + 0x28 */ + u32 cs5_start; /* MMAP_CTRL + 0x2c */ + u32 cs5_stop; /* MMAP_CTRL + 0x30 */ + + u32 sdram0; /* MMAP_CTRL + 0x34 */ + u32 sdram1; /* MMAP_CTRL + 0X38 */ + + u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */ + + u32 boot_start; /* MMAP_CTRL + 0x4c */ + u32 boot_stop; /* MMAP_CTRL + 0x50 */ + + u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */ + + u32 cs6_start; /* MMAP_CTRL + 0x58 */ + u32 cs6_stop; /* MMAP_CTRL + 0x5c */ + u32 cs7_start; /* MMAP_CTRL + 0x60 */ + u32 cs7_stop; /* MMAP_CTRL + 0x60 */ +}; + +/* SDRAM control */ +struct mpc52xx_sdram { + u32 mode; /* SDRAM + 0x00 */ + u32 ctrl; /* SDRAM + 0x04 */ + u32 config1; /* SDRAM + 0x08 */ + u32 config2; /* SDRAM + 0x0c */ }; /* Interrupt controller */ struct mpc52xx_intr { - volatile u32 per_mask; /* INTR + 0x00 */ - volatile u32 per_pri1; /* INTR + 0x04 */ - volatile u32 per_pri2; /* INTR + 0x08 */ - volatile u32 per_pri3; /* INTR + 0x0c */ - volatile u32 ctrl; /* INTR + 0x10 */ - volatile u32 main_mask; /* INTR + 0x14 */ - volatile u32 main_pri1; /* INTR + 0x18 */ - volatile u32 main_pri2; /* INTR + 0x1c */ - volatile u32 reserved1; /* INTR + 0x20 */ - volatile u32 enc_status; /* INTR + 0x24 */ - volatile u32 crit_status; /* INTR + 0x28 */ - volatile u32 main_status; /* INTR + 0x2c */ - volatile u32 per_status; /* INTR + 0x30 */ - volatile u32 reserved2; /* INTR + 0x34 */ - volatile u32 per_error; /* INTR + 0x38 */ + u32 per_mask; /* INTR + 0x00 */ + u32 per_pri1; /* INTR + 0x04 */ + u32 per_pri2; /* INTR + 0x08 */ + u32 per_pri3; /* INTR + 0x0c */ + u32 ctrl; /* INTR + 0x10 */ + u32 main_mask; /* INTR + 0x14 */ + u32 main_pri1; /* INTR + 0x18 */ + u32 main_pri2; /* INTR + 0x1c */ + u32 reserved1; /* INTR + 0x20 */ + u32 enc_status; /* INTR + 0x24 */ + u32 crit_status; /* INTR + 0x28 */ + u32 main_status; /* INTR + 0x2c */ + u32 per_status; /* INTR + 0x30 */ + u32 reserved2; /* INTR + 0x34 */ + u32 per_error; /* INTR + 0x38 */ }; /* SDMA */ struct mpc52xx_sdma { - volatile u32 taskBar; /* SDMA + 0x00 */ - volatile u32 currentPointer; /* SDMA + 0x04 */ - volatile u32 endPointer; /* SDMA + 0x08 */ - volatile u32 variablePointer;/* SDMA + 0x0c */ - - volatile u8 IntVect1; /* SDMA + 0x10 */ - volatile u8 IntVect2; /* SDMA + 0x11 */ - volatile u16 PtdCntrl; /* SDMA + 0x12 */ - - volatile u32 IntPend; /* SDMA + 0x14 */ - volatile u32 IntMask; /* SDMA + 0x18 */ - - volatile u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */ - - volatile u8 ipr[31]; /* SDMA + 0x3c .. 5b */ - - volatile u32 res1; /* SDMA + 0x5c */ - volatile u32 task_size0; /* SDMA + 0x60 */ - volatile u32 task_size1; /* SDMA + 0x64 */ - volatile u32 MDEDebug; /* SDMA + 0x68 */ - volatile u32 ADSDebug; /* SDMA + 0x6c */ - volatile u32 Value1; /* SDMA + 0x70 */ - volatile u32 Value2; /* SDMA + 0x74 */ - volatile u32 Control; /* SDMA + 0x78 */ - volatile u32 Status; /* SDMA + 0x7c */ + u32 taskBar; /* SDMA + 0x00 */ + u32 currentPointer; /* SDMA + 0x04 */ + u32 endPointer; /* SDMA + 0x08 */ + u32 variablePointer;/* SDMA + 0x0c */ + + u8 IntVect1; /* SDMA + 0x10 */ + u8 IntVect2; /* SDMA + 0x11 */ + u16 PtdCntrl; /* SDMA + 0x12 */ + + u32 IntPend; /* SDMA + 0x14 */ + u32 IntMask; /* SDMA + 0x18 */ + + u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */ + + u8 ipr[32]; /* SDMA + 0x3c .. 5b */ + + u32 cReqSelect; /* SDMA + 0x5c */ + u32 task_size0; /* SDMA + 0x60 */ + u32 task_size1; /* SDMA + 0x64 */ + u32 MDEDebug; /* SDMA + 0x68 */ + u32 ADSDebug; /* SDMA + 0x6c */ + u32 Value1; /* SDMA + 0x70 */ + u32 Value2; /* SDMA + 0x74 */ + u32 Control; /* SDMA + 0x78 */ + u32 Status; /* SDMA + 0x7c */ + u32 PTDDebug; /* SDMA + 0x80 */ }; /* GPT */ struct mpc52xx_gpt { - volatile u32 mode; /* GPTx + 0x00 */ - volatile u32 count; /* GPTx + 0x04 */ - volatile u32 pwm; /* GPTx + 0x08 */ - volatile u32 status; /* GPTx + 0X0c */ + u32 mode; /* GPTx + 0x00 */ + u32 count; /* GPTx + 0x04 */ + u32 pwm; /* GPTx + 0x08 */ + u32 status; /* GPTx + 0X0c */ }; /* RTC */ struct mpc52xx_rtc { - volatile u32 time_set; /* RTC + 0x00 */ - volatile u32 date_set; /* RTC + 0x04 */ - volatile u32 stopwatch; /* RTC + 0x08 */ - volatile u32 int_enable; /* RTC + 0x0c */ - volatile u32 time; /* RTC + 0x10 */ - volatile u32 date; /* RTC + 0x14 */ - volatile u32 stopwatch_intr; /* RTC + 0x18 */ - volatile u32 bus_error; /* RTC + 0x1c */ - volatile u32 dividers; /* RTC + 0x20 */ + u32 time_set; /* RTC + 0x00 */ + u32 date_set; /* RTC + 0x04 */ + u32 stopwatch; /* RTC + 0x08 */ + u32 int_enable; /* RTC + 0x0c */ + u32 time; /* RTC + 0x10 */ + u32 date; /* RTC + 0x14 */ + u32 stopwatch_intr; /* RTC + 0x18 */ + u32 bus_error; /* RTC + 0x1c */ + u32 dividers; /* RTC + 0x20 */ }; /* GPIO */ struct mpc52xx_gpio { - volatile u32 port_config; /* GPIO + 0x00 */ - volatile u32 simple_gpioe; /* GPIO + 0x04 */ - volatile u32 simple_ode; /* GPIO + 0x08 */ - volatile u32 simple_ddr; /* GPIO + 0x0c */ - volatile u32 simple_dvo; /* GPIO + 0x10 */ - volatile u32 simple_ival; /* GPIO + 0x14 */ - volatile u8 outo_gpioe; /* GPIO + 0x18 */ - volatile u8 reserved1[3]; /* GPIO + 0x19 */ - volatile u8 outo_dvo; /* GPIO + 0x1c */ - volatile u8 reserved2[3]; /* GPIO + 0x1d */ - volatile u8 sint_gpioe; /* GPIO + 0x20 */ - volatile u8 reserved3[3]; /* GPIO + 0x21 */ - volatile u8 sint_ode; /* GPIO + 0x24 */ - volatile u8 reserved4[3]; /* GPIO + 0x25 */ - volatile u8 sint_ddr; /* GPIO + 0x28 */ - volatile u8 reserved5[3]; /* GPIO + 0x29 */ - volatile u8 sint_dvo; /* GPIO + 0x2c */ - volatile u8 reserved6[3]; /* GPIO + 0x2d */ - volatile u8 sint_inten; /* GPIO + 0x30 */ - volatile u8 reserved7[3]; /* GPIO + 0x31 */ - volatile u16 sint_itype; /* GPIO + 0x34 */ - volatile u16 reserved8; /* GPIO + 0x36 */ - volatile u8 gpio_control; /* GPIO + 0x38 */ - volatile u8 reserved9[3]; /* GPIO + 0x39 */ - volatile u8 sint_istat; /* GPIO + 0x3c */ - volatile u8 sint_ival; /* GPIO + 0x3d */ - volatile u8 bus_errs; /* GPIO + 0x3e */ - volatile u8 reserved10; /* GPIO + 0x3f */ + u32 port_config; /* GPIO + 0x00 */ + u32 simple_gpioe; /* GPIO + 0x04 */ + u32 simple_ode; /* GPIO + 0x08 */ + u32 simple_ddr; /* GPIO + 0x0c */ + u32 simple_dvo; /* GPIO + 0x10 */ + u32 simple_ival; /* GPIO + 0x14 */ + u8 outo_gpioe; /* GPIO + 0x18 */ + u8 reserved1[3]; /* GPIO + 0x19 */ + u8 outo_dvo; /* GPIO + 0x1c */ + u8 reserved2[3]; /* GPIO + 0x1d */ + u8 sint_gpioe; /* GPIO + 0x20 */ + u8 reserved3[3]; /* GPIO + 0x21 */ + u8 sint_ode; /* GPIO + 0x24 */ + u8 reserved4[3]; /* GPIO + 0x25 */ + u8 sint_ddr; /* GPIO + 0x28 */ + u8 reserved5[3]; /* GPIO + 0x29 */ + u8 sint_dvo; /* GPIO + 0x2c */ + u8 reserved6[3]; /* GPIO + 0x2d */ + u8 sint_inten; /* GPIO + 0x30 */ + u8 reserved7[3]; /* GPIO + 0x31 */ + u16 sint_itype; /* GPIO + 0x34 */ + u16 reserved8; /* GPIO + 0x36 */ + u8 gpio_control; /* GPIO + 0x38 */ + u8 reserved9[3]; /* GPIO + 0x39 */ + u8 sint_istat; /* GPIO + 0x3c */ + u8 sint_ival; /* GPIO + 0x3d */ + u8 bus_errs; /* GPIO + 0x3e */ + u8 reserved10; /* GPIO + 0x3f */ }; #define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5 #define MPC52xx_GPIO_PCI_DIS (1<<15) +/* GPIO with WakeUp*/ +struct mpc52xx_gpio_wkup { + u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */ + u8 reserved1[3]; /* GPIO_WKUP + 0x03 */ + u8 wkup_ode; /* GPIO_WKUP + 0x04 */ + u8 reserved2[3]; /* GPIO_WKUP + 0x05 */ + u8 wkup_ddr; /* GPIO_WKUP + 0x08 */ + u8 reserved3[3]; /* GPIO_WKUP + 0x09 */ + u8 wkup_dvo; /* GPIO_WKUP + 0x0C */ + u8 reserved4[3]; /* GPIO_WKUP + 0x0D */ + u8 wkup_inten; /* GPIO_WKUP + 0x10 */ + u8 reserved5[3]; /* GPIO_WKUP + 0x11 */ + u8 wkup_iinten; /* GPIO_WKUP + 0x14 */ + u8 reserved6[3]; /* GPIO_WKUP + 0x15 */ + u16 wkup_itype; /* GPIO_WKUP + 0x18 */ + u8 reserved7[2]; /* GPIO_WKUP + 0x1A */ + u8 wkup_maste; /* GPIO_WKUP + 0x1C */ + u8 reserved8[3]; /* GPIO_WKUP + 0x1D */ + u8 wkup_ival; /* GPIO_WKUP + 0x20 */ + u8 reserved9[3]; /* GPIO_WKUP + 0x21 */ + u8 wkup_istat; /* GPIO_WKUP + 0x24 */ + u8 reserved10[3]; /* GPIO_WKUP + 0x25 */ +}; + /* XLB Bus control */ struct mpc52xx_xlb { - volatile u8 reserved[0x40]; - volatile u32 config; /* XLB + 0x40 */ - volatile u32 version; /* XLB + 0x44 */ - volatile u32 status; /* XLB + 0x48 */ - volatile u32 int_enable; /* XLB + 0x4c */ - volatile u32 addr_capture; /* XLB + 0x50 */ - volatile u32 bus_sig_capture; /* XLB + 0x54 */ - volatile u32 addr_timeout; /* XLB + 0x58 */ - volatile u32 data_timeout; /* XLB + 0x5c */ - volatile u32 bus_act_timeout; /* XLB + 0x60 */ - volatile u32 master_pri_enable; /* XLB + 0x64 */ - volatile u32 master_priority; /* XLB + 0x68 */ - volatile u32 base_address; /* XLB + 0x6c */ - volatile u32 snoop_window; /* XLB + 0x70 */ + u8 reserved[0x40]; + u32 config; /* XLB + 0x40 */ + u32 version; /* XLB + 0x44 */ + u32 status; /* XLB + 0x48 */ + u32 int_enable; /* XLB + 0x4c */ + u32 addr_capture; /* XLB + 0x50 */ + u32 bus_sig_capture; /* XLB + 0x54 */ + u32 addr_timeout; /* XLB + 0x58 */ + u32 data_timeout; /* XLB + 0x5c */ + u32 bus_act_timeout; /* XLB + 0x60 */ + u32 master_pri_enable; /* XLB + 0x64 */ + u32 master_priority; /* XLB + 0x68 */ + u32 base_address; /* XLB + 0x6c */ + u32 snoop_window; /* XLB + 0x70 */ }; +#define MPC52xx_XLB_CFG_SNOOP (1 << 15) /* Clock Distribution control */ struct mpc52xx_cdm { - volatile u32 jtag_id; /* MBAR_CDM + 0x00 reg0 read only */ - volatile u32 rstcfg; /* MBAR_CDM + 0x04 reg1 read only */ - volatile u32 breadcrumb; /* MBAR_CDM + 0x08 reg2 */ - - volatile u8 mem_clk_sel; /* MBAR_CDM + 0x0c reg3 byte0 */ - volatile u8 xlb_clk_sel; /* MBAR_CDM + 0x0d reg3 byte1 read only */ - volatile u8 ipb_clk_sel; /* MBAR_CDM + 0x0e reg3 byte2 */ - volatile u8 pci_clk_sel; /* MBAR_CDM + 0x0f reg3 byte3 */ - - volatile u8 ext_48mhz_en; /* MBAR_CDM + 0x10 reg4 byte0 */ - volatile u8 fd_enable; /* MBAR_CDM + 0x11 reg4 byte1 */ - volatile u16 fd_counters; /* MBAR_CDM + 0x12 reg4 byte2,3 */ - - volatile u32 clk_enables; /* MBAR_CDM + 0x14 reg5 */ - - volatile u8 osc_disable; /* MBAR_CDM + 0x18 reg6 byte0 */ - volatile u8 reserved0[3]; /* MBAR_CDM + 0x19 reg6 byte1,2,3 */ - - volatile u8 ccs_sleep_enable;/* MBAR_CDM + 0x1c reg7 byte0 */ - volatile u8 osc_sleep_enable;/* MBAR_CDM + 0x1d reg7 byte1 */ - volatile u8 reserved1; /* MBAR_CDM + 0x1e reg7 byte2 */ - volatile u8 ccs_qreq_test; /* MBAR_CDM + 0x1f reg7 byte3 */ - - volatile u8 soft_reset; /* MBAR_CDM + 0x20 u8 byte0 */ - volatile u8 no_ckstp; /* MBAR_CDM + 0x21 u8 byte0 */ - volatile u8 reserved2[2]; /* MBAR_CDM + 0x22 u8 byte1,2,3 */ - - volatile u8 pll_lock; /* MBAR_CDM + 0x24 reg9 byte0 */ - volatile u8 pll_looselock; /* MBAR_CDM + 0x25 reg9 byte1 */ - volatile u8 pll_sm_lockwin; /* MBAR_CDM + 0x26 reg9 byte2 */ - volatile u8 reserved3; /* MBAR_CDM + 0x27 reg9 byte3 */ - - volatile u16 reserved4; /* MBAR_CDM + 0x28 reg10 byte0,1 */ - volatile u16 mclken_div_psc1;/* MBAR_CDM + 0x2a reg10 byte2,3 */ - - volatile u16 reserved5; /* MBAR_CDM + 0x2c reg11 byte0,1 */ - volatile u16 mclken_div_psc2;/* MBAR_CDM + 0x2e reg11 byte2,3 */ - - volatile u16 reserved6; /* MBAR_CDM + 0x30 reg12 byte0,1 */ - volatile u16 mclken_div_psc3;/* MBAR_CDM + 0x32 reg12 byte2,3 */ - - volatile u16 reserved7; /* MBAR_CDM + 0x34 reg13 byte0,1 */ - volatile u16 mclken_div_psc6;/* MBAR_CDM + 0x36 reg13 byte2,3 */ + u32 jtag_id; /* CDM + 0x00 reg0 read only */ + u32 rstcfg; /* CDM + 0x04 reg1 read only */ + u32 breadcrumb; /* CDM + 0x08 reg2 */ + + u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */ + u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */ + u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */ + u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */ + + u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */ + u8 fd_enable; /* CDM + 0x11 reg4 byte1 */ + u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */ + + u32 clk_enables; /* CDM + 0x14 reg5 */ + + u8 osc_disable; /* CDM + 0x18 reg6 byte0 */ + u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */ + + u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */ + u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */ + u8 reserved1; /* CDM + 0x1e reg7 byte2 */ + u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */ + + u8 soft_reset; /* CDM + 0x20 u8 byte0 */ + u8 no_ckstp; /* CDM + 0x21 u8 byte0 */ + u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */ + + u8 pll_lock; /* CDM + 0x24 reg9 byte0 */ + u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */ + u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */ + u8 reserved3; /* CDM + 0x27 reg9 byte3 */ + + u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */ + u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */ + + u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */ + u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */ + + u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */ + u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */ + + u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */ + u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */ }; #endif /* __ASSEMBLY__ */