X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=include%2Fasm-ppc%2Fmv64x60.h;h=cc25b921ad4fa643ccf62c7e88a4e2ab36342a3a;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=0aa548226796435d30a05b5058cf458ecf217e01;hpb=87fc8d1bb10cd459024a742c6a10961fefcef18f;p=linux-2.6.git diff --git a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h index 0aa548226..cc25b921a 100644 --- a/include/asm-ppc/mv64x60.h +++ b/include/asm-ppc/mv64x60.h @@ -1,6 +1,6 @@ /* * include/asm-ppc/mv64x60.h - * + * * Prototypes, etc. for the Marvell/Galileo MV64x60 host bridge routines. * * Author: Mark A. Greer @@ -27,18 +27,9 @@ #include #include -extern u8 mv64x60_pci_exclude_bridge; +extern u8 mv64x60_pci_exclude_bridge; extern spinlock_t mv64x60_lock; -extern spinlock_t mv64x60_rmw_lock; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif /* 32-bit Window table entry defines */ #define MV64x60_CPU2MEM_0_WIN 0 @@ -79,8 +70,26 @@ extern spinlock_t mv64x60_rmw_lock; #define MV64x60_PCI12MEM_REMAP_1_WIN 35 #define MV64x60_PCI12MEM_REMAP_2_WIN 36 #define MV64x60_PCI12MEM_REMAP_3_WIN 37 - -#define MV64x60_32BIT_WIN_COUNT 38 +#define MV64x60_ENET2MEM_0_WIN 38 +#define MV64x60_ENET2MEM_1_WIN 39 +#define MV64x60_ENET2MEM_2_WIN 40 +#define MV64x60_ENET2MEM_3_WIN 41 +#define MV64x60_ENET2MEM_4_WIN 42 +#define MV64x60_ENET2MEM_5_WIN 43 +#define MV64x60_MPSC2MEM_0_WIN 44 +#define MV64x60_MPSC2MEM_1_WIN 45 +#define MV64x60_MPSC2MEM_2_WIN 46 +#define MV64x60_MPSC2MEM_3_WIN 47 +#define MV64x60_IDMA2MEM_0_WIN 48 +#define MV64x60_IDMA2MEM_1_WIN 49 +#define MV64x60_IDMA2MEM_2_WIN 50 +#define MV64x60_IDMA2MEM_3_WIN 51 +#define MV64x60_IDMA2MEM_4_WIN 52 +#define MV64x60_IDMA2MEM_5_WIN 53 +#define MV64x60_IDMA2MEM_6_WIN 54 +#define MV64x60_IDMA2MEM_7_WIN 55 + +#define MV64x60_32BIT_WIN_COUNT 56 /* 64-bit Window table entry defines */ #define MV64x60_CPU2PCI0_MEM_0_REMAP_WIN 0 @@ -110,54 +119,63 @@ extern spinlock_t mv64x60_rmw_lock; #define MV64x60_64BIT_WIN_COUNT 24 - /* * Define a structure that's used to pass in config information to the * core routines. */ -typedef struct { +struct mv64x60_pci_window { u32 cpu_base; u32 pci_base_hi; u32 pci_base_lo; u32 size; u32 swap; -} mv64x60_pci_window_t; +}; -typedef struct { +struct mv64x60_pci_info { u8 enable_bus; /* allow access to this PCI bus? */ - u8 enumerate_bus; /* enumerate devices on this bus? */ - mv64x60_pci_window_t pci_io; - mv64x60_pci_window_t pci_mem[3]; + struct mv64x60_pci_window pci_io; + struct mv64x60_pci_window pci_mem[3]; u32 acc_cntl_options[MV64x60_CPU2MEM_WINDOWS]; u32 snoop_options[MV64x60_CPU2MEM_WINDOWS]; u16 pci_cmd_bits; u16 latency_timer; -} mv64x60_pci_info_t; +}; -typedef struct { +struct mv64x60_setup_info { u32 phys_reg_base; - - u32 window_preserve_mask_32; + u32 window_preserve_mask_32_hi; + u32 window_preserve_mask_32_lo; u32 window_preserve_mask_64; - u32 base_irq; /* Starting irq # for this intr ctlr */ - int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char)); - u32 cpu_prot_options[MV64x60_CPU2MEM_WINDOWS]; u32 cpu_snoop_options[MV64x60_CPU2MEM_WINDOWS]; + u32 enet_options[MV64x60_CPU2MEM_WINDOWS]; + u32 mpsc_options[MV64x60_CPU2MEM_WINDOWS]; + u32 idma_options[MV64x60_CPU2MEM_WINDOWS]; + + struct mv64x60_pci_info pci_0; + struct mv64x60_pci_info pci_1; +}; - mv64x60_pci_info_t pci_0; - mv64x60_pci_info_t pci_1; -} mv64x60_setup_info_t; +/* Define what the top bits in the extra member of a window entry means. */ +#define MV64x60_EXTRA_INVALID 0x00000000 +#define MV64x60_EXTRA_CPUWIN_ENAB 0x10000000 +#define MV64x60_EXTRA_CPUPROT_ENAB 0x20000000 +#define MV64x60_EXTRA_ENET_ENAB 0x30000000 +#define MV64x60_EXTRA_MPSC_ENAB 0x40000000 +#define MV64x60_EXTRA_IDMA_ENAB 0x50000000 +#define MV64x60_EXTRA_PCIACC_ENAB 0x60000000 + +#define MV64x60_EXTRA_MASK 0xf0000000 /* * Define the 'handle' struct that will be passed between the 64x60 core * code and the platform-specific code that will use it. The handle * will contain pointers to chip-specific routines & information. */ -typedef struct { +struct mv64x60_32bit_window { u32 base_reg; u32 size_reg; u8 base_bits; @@ -165,9 +183,9 @@ typedef struct { u32 (*get_from_field)(u32 val, u32 num_bits); u32 (*map_to_field)(u32 val, u32 num_bits); u32 extra; -} mv64x60_32bit_window_t; +}; -typedef struct { +struct mv64x60_64bit_window { u32 base_hi_reg; u32 base_lo_reg; u32 size_reg; @@ -176,160 +194,152 @@ typedef struct { u32 (*get_from_field)(u32 val, u32 num_bits); u32 (*map_to_field)(u32 val, u32 num_bits); u32 extra; -} mv64x60_64bit_window_t; - -typedef struct mv64x60_handle mv64x60_handle_t; +}; -typedef struct { +typedef struct mv64x60_handle mv64x60_handle_t; +struct mv64x60_chip_info { u32 (*translate_size)(u32 base, u32 size, u32 num_bits); u32 (*untranslate_size)(u32 base, u32 size, u32 num_bits); - void (*set_pci2mem_window)(struct pci_controller *hose, u32 window, - u32 base); + void (*set_pci2mem_window)(struct pci_controller *hose, u32 bus, + u32 window, u32 base); + void (*set_pci2regs_window)(struct mv64x60_handle *bh, + struct pci_controller *hose, u32 bus, u32 base); u32 (*is_enabled_32bit)(mv64x60_handle_t *bh, u32 window); void (*enable_window_32bit)(mv64x60_handle_t *bh, u32 window); void (*disable_window_32bit)(mv64x60_handle_t *bh, u32 window); void (*enable_window_64bit)(mv64x60_handle_t *bh, u32 window); void (*disable_window_64bit)(mv64x60_handle_t *bh, u32 window); void (*disable_all_windows)(mv64x60_handle_t *bh, - mv64x60_setup_info_t *si); + struct mv64x60_setup_info *si); + void (*config_io2mem_windows)(mv64x60_handle_t *bh, + struct mv64x60_setup_info *si, + u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); + void (*set_mpsc2regs_window)(struct mv64x60_handle *bh, u32 base); void (*chip_specific_init)(mv64x60_handle_t *bh, - mv64x60_setup_info_t *si); + struct mv64x60_setup_info *si); - mv64x60_32bit_window_t *window_tab_32bit; - mv64x60_64bit_window_t *window_tab_64bit; -} mv64x60_chip_info_t; + struct mv64x60_32bit_window *window_tab_32bit; + struct mv64x60_64bit_window *window_tab_64bit; +}; struct mv64x60_handle { - u32 type; /* type of bridge */ - u32 v_base; /* virtual base addr of bridge regs */ - u32 p_base; /* physical base addr of bridge regs */ - u32 base_irq; /* Base irq # for intrs on this intr cltr */ + u32 type; /* type of bridge */ + u32 rev; /* revision of bridge */ + void *v_base; /* virtual base addr of bridge regs */ + phys_addr_t p_base; /* physical base addr of bridge regs */ + + u32 pci_mode_a; /* pci 0 mode: conventional pci, pci-x*/ + u32 pci_mode_b; /* pci 1 mode: conventional pci, pci-x*/ - u32 io_base_a; /* vaddr of pci 0's I/O space */ - u32 io_base_b; /* vaddr of pci 1's I/O space */ + u32 io_base_a; /* vaddr of pci 0's I/O space */ + u32 io_base_b; /* vaddr of pci 1's I/O space */ struct pci_controller *hose_a; struct pci_controller *hose_b; - mv64x60_chip_info_t *ci; /* chip/bridge-specific info */ + struct mv64x60_chip_info *ci; /* chip/bridge-specific info */ }; /* Define I/O routines for accessing registers on the 64x60 bridge. */ extern inline void -mv64x60_write(mv64x60_handle_t *bh, u32 offset, u32 val) { - out_le32((volatile u32 *)(bh->v_base + offset), val); +mv64x60_write(struct mv64x60_handle *bh, u32 offset, u32 val) { + ulong flags; + + spin_lock_irqsave(&mv64x60_lock, flags); + out_le32(bh->v_base + offset, val); + spin_unlock_irqrestore(&mv64x60_lock, flags); } extern inline u32 -mv64x60_read(mv64x60_handle_t *bh, u32 offset) { - return in_le32((volatile u32 *)(bh->v_base + offset)); +mv64x60_read(struct mv64x60_handle *bh, u32 offset) { + ulong flags; + u32 reg; + + spin_lock_irqsave(&mv64x60_lock, flags); + reg = in_le32(bh->v_base + offset); + spin_unlock_irqrestore(&mv64x60_lock, flags); + return reg; } extern inline void -mv64x60_modify(mv64x60_handle_t *bh, u32 offs, u32 data, u32 mask) +mv64x60_modify(struct mv64x60_handle *bh, u32 offs, u32 data, u32 mask) { - uint32_t reg; - unsigned long flags; - - spin_lock_irqsave(&mv64x60_rmw_lock, flags); - reg = mv64x60_read(bh, offs) & (~mask); /* zero any bits we care about*/ - reg |= data & mask; /* set bits from the data */ - mv64x60_write(bh, offs, reg); - spin_unlock_irqrestore(&mv64x60_rmw_lock, flags); + u32 reg; + ulong flags; + + spin_lock_irqsave(&mv64x60_lock, flags); + reg = in_le32(bh->v_base + offs) & (~mask); + reg |= data & mask; + out_le32(bh->v_base + offs, reg); + spin_unlock_irqrestore(&mv64x60_lock, flags); } -#define mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits) +#define mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits) #define mv64x60_clr_bits(bh, offs, bits) mv64x60_modify(bh, offs, 0, bits) /* Externally visible function prototypes */ -int mv64x60_init(mv64x60_handle_t *bh, mv64x60_setup_info_t *si); +int mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si); u32 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type); -void mv64x60_get_32bit_window(mv64x60_handle_t *bh, u32 window, - u32 *base, u32 *size); -void mv64x60_set_32bit_window(mv64x60_handle_t *bh, u32 window, u32 base, - u32 size, u32 other_bits); -void mv64x60_get_64bit_window(mv64x60_handle_t *bh, u32 window, u32 *base_hi, - u32 *base_lo, u32 *size); -void mv64x60_set_64bit_window(mv64x60_handle_t *bh, u32 window, u32 base_hi, - u32 base_lo, u32 size, u32 other_bits); +void mv64x60_early_init(struct mv64x60_handle *bh, + struct mv64x60_setup_info *si); +void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, + u32 cfg_data, struct pci_controller **hose); +int mv64x60_get_type(struct mv64x60_handle *bh); +int mv64x60_setup_for_chip(struct mv64x60_handle *bh); +void *mv64x60_get_bridge_vbase(void); +u32 mv64x60_get_bridge_type(void); +u32 mv64x60_get_bridge_rev(void); +void mv64x60_get_mem_windows(struct mv64x60_handle *bh, + u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); +void mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh, + struct mv64x60_setup_info *si, + u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); +void mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh, + struct mv64x60_pci_info *pi, u32 bus); +void mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh, + struct pci_controller *hose, struct mv64x60_pci_info *pi, u32 bus, + u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); +void mv64x60_config_resources(struct pci_controller *hose, + struct mv64x60_pci_info *pi, u32 io_base); +void mv64x60_config_pci_params(struct pci_controller *hose, + struct mv64x60_pci_info *pi); +void mv64x60_pd_fixup(struct mv64x60_handle *bh, + struct platform_device *pd_devs[], u32 entries); +void mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window, + u32 *base, u32 *size); +void mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, u32 base, + u32 size, u32 other_bits); +void mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window, + u32 *base_hi, u32 *base_lo, u32 *size); +void mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window, + u32 base_hi, u32 base_lo, u32 size, u32 other_bits); +void mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus); +int mv64x60_pci_exclude_device(u8 bus, u8 devfn); void gt64260_init_irq(void); int gt64260_get_irq(struct pt_regs *regs); - -/* - * OCP Related Definitions - */ -typedef struct { - u8 mirror_regs; - u8 cache_mgmt; - u8 max_idle; - int default_baud; - int default_bits; - int default_parity; - int default_flow; - u32 chr_1_val; - u32 chr_2_val; - u32 chr_10_val; - u32 mpcr_val; - u32 mrr_val; - u32 rcrr_val; - u32 tcrr_val; - u32 intr_mask_val; - u32 bcr_val; - u32 sdma_irq; - u8 brg_can_tune; - u8 brg_clk_src; - u32 brg_clk_freq; -} mv64x60_ocp_mpsc_data_t; - -#define MV64x60_OCP_SYSFS_MPSC_DATA() \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "%d\n", mpsc, mirror_regs) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "%d\n", mpsc, cache_mgmt) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "%d\n", mpsc, max_idle) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "%d\n", mpsc, default_baud) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "%d\n", mpsc, default_bits) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "%c\n", mpsc, default_parity) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "%c\n", mpsc, default_flow) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "0x%x\n", mpsc, chr_1_val) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "0x%x\n", mpsc, chr_2_val) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "0x%x\n", mpsc, chr_10_val) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "0x%x\n", mpsc, mpcr_val) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "0x%x\n", mpsc, mrr_val) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "0x%x\n", mpsc, rcrr_val) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "0x%x\n", mpsc, tcrr_val) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "0x%x\n", mpsc, intr_mask_val) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "0x%x\n", mpsc, bcr_val) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "%d\n", mpsc, sdma_irq) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "%d\n", mpsc, brg_can_tune) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "%d\n", mpsc, brg_clk_src) \ -OCP_SYSFS_ADDTL(mv64x60_ocp_mpsc_data_t, "%d\n", mpsc, brg_clk_freq) \ - \ -void \ -mv64x60_ocp_show_mpsc(struct device *dev) \ -{ \ - device_create_file(dev, &dev_attr_mpsc_mirror_regs); \ - device_create_file(dev, &dev_attr_mpsc_cache_mgmt); \ - device_create_file(dev, &dev_attr_mpsc_max_idle); \ - device_create_file(dev, &dev_attr_mpsc_default_baud); \ - device_create_file(dev, &dev_attr_mpsc_default_bits); \ - device_create_file(dev, &dev_attr_mpsc_default_parity); \ - device_create_file(dev, &dev_attr_mpsc_default_flow); \ - device_create_file(dev, &dev_attr_mpsc_chr_1_val); \ - device_create_file(dev, &dev_attr_mpsc_chr_2_val); \ - device_create_file(dev, &dev_attr_mpsc_chr_10_val); \ - device_create_file(dev, &dev_attr_mpsc_mpcr_val); \ - device_create_file(dev, &dev_attr_mpsc_mrr_val); \ - device_create_file(dev, &dev_attr_mpsc_rcrr_val); \ - device_create_file(dev, &dev_attr_mpsc_tcrr_val); \ - device_create_file(dev, &dev_attr_mpsc_intr_mask_val); \ - device_create_file(dev, &dev_attr_mpsc_bcr_val); \ - device_create_file(dev, &dev_attr_mpsc_sdma_irq); \ - device_create_file(dev, &dev_attr_mpsc_brg_can_tune); \ - device_create_file(dev, &dev_attr_mpsc_brg_clk_src); \ - device_create_file(dev, &dev_attr_mpsc_brg_clk_freq); \ -} +void mv64360_init_irq(void); +int mv64360_get_irq(struct pt_regs *regs); + +u32 mv64x60_mask(u32 val, u32 num_bits); +u32 mv64x60_shift_left(u32 val, u32 num_bits); +u32 mv64x60_shift_right(u32 val, u32 num_bits); +u32 mv64x60_calc_mem_size(struct mv64x60_handle *bh, + u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); + +void mv64x60_progress_init(u32 base); +void mv64x60_mpsc_progress(char *s, unsigned short hex); + +extern struct mv64x60_32bit_window + gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT]; +extern struct mv64x60_64bit_window + gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT]; +extern struct mv64x60_32bit_window + mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT]; +extern struct mv64x60_64bit_window + mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT]; #endif /* __ASMPPC_MV64x60_H */