X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=include%2Fasm-ppc%2Freg.h;h=43d865b974439362dc76706b528c8d17f1abb40c;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=4c29516b836096fdd48311d37c8e5046015a0474;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git

diff --git a/include/asm-ppc/reg.h b/include/asm-ppc/reg.h
index 4c29516b8..43d865b97 100644
--- a/include/asm-ppc/reg.h
+++ b/include/asm-ppc/reg.h
@@ -174,6 +174,7 @@
 
 #define SPRN_HID1	0x3F1		/* Hardware Implementation Register 1 */
 #define HID1_EMCP	(1<<31)		/* 7450 Machine Check Pin Enable */
+#define HID1_DFS	(1<<22)		/* 7447A Dynamic Frequency Scaling */
 #define HID1_PC0	(1<<16)		/* 7450 PLL_CFG[0] */
 #define HID1_PC1	(1<<15)		/* 7450 PLL_CFG[1] */
 #define HID1_PC2	(1<<14)		/* 7450 PLL_CFG[2] */
@@ -243,6 +244,10 @@
 #define L2CR_L2DF		0x00004000	/* L2 differential clock */
 #define L2CR_L2BYP		0x00002000	/* L2 DLL bypass */
 #define L2CR_L2IP		0x00000001	/* L2 GI in progress */
+#define L2CR_L2IO_745x		0x00100000	/* L2 instr. only (745x) */
+#define L2CR_L2DO_745x		0x00010000	/* L2 data only (745x) */
+#define L2CR_L2REP_745x		0x00001000	/* L2 repl. algorithm (745x) */
+#define L2CR_L2HWF_745x		0x00000800	/* L2 hardware flush (745x) */
 #define SPRN_L3CR		0x3FA	/* Level 3 Cache Control Regsiter */
 #define L3CR_L3E		0x80000000	/* L3 enable */
 #define L3CR_L3PE		0x40000000	/* L3 data parity enable */
@@ -294,6 +299,9 @@
 #define SPRN_SPRG7	0x117	/* Special Purpose Register General 7 */
 #define SPRN_SRR0	0x01A	/* Save/Restore Register 0 */
 #define SPRN_SRR1	0x01B	/* Save/Restore Register 1 */
+#ifndef SPRN_SVR
+#define SPRN_SVR	0x11E	/* System Version Register */
+#endif
 #define SPRN_THRM1	0x3FC		/* Thermal Management Register 1 */
 /* these bits were defined in inverted endian sense originally, ugh, confusing */
 #define THRM1_TIN	(1 << 31)
@@ -325,6 +333,7 @@
 #define MMCR0_PMC2_CYCLES	0x1
 #define MMCR0_PMC2_ITLB		0x7
 #define MMCR0_PMC2_LOADMISSTIME	0x5
+#define MMCR0_PMXE	(1 << 26)
 
 /* Short-hand versions for a number of the above SPRNs */
 #define CTR	SPRN_CTR	/* Counter Register */
@@ -346,7 +355,7 @@
 #define DBAT6U	SPRN_DBAT6U	/* Data BAT 6 Upper Register */
 #define DBAT7L	SPRN_DBAT7L	/* Data BAT 7 Lower Register */
 #define DBAT7U	SPRN_DBAT7U	/* Data BAT 7 Upper Register */
-#define DEC	SPRN_DEC	/* Decrement Register */
+//#define DEC	SPRN_DEC	/* Decrement Register */
 #define DMISS	SPRN_DMISS	/* Data TLB Miss Register */
 #define DSISR	SPRN_DSISR	/* Data Storage Interrupt Status Register */
 #define EAR	SPRN_EAR	/* External Address Register */
@@ -376,9 +385,9 @@
 #define IMMR	SPRN_IMMR	/* PPC 860/821 Internal Memory Map Register */
 #define L2CR	SPRN_L2CR	/* Classic PPC L2 cache control register */
 #define L3CR	SPRN_L3CR	/* PPC 745x L3 cache control register */
-#define LR	SPRN_LR
+//#define LR	SPRN_LR
 #define PVR	SPRN_PVR	/* Processor Version */
-#define RPA	SPRN_RPA	/* Required Physical Address Register */
+//#define RPA	SPRN_RPA	/* Required Physical Address Register */
 #define SDR1	SPRN_SDR1	/* MMU hash base register */
 #define SPR0	SPRN_SPRG0	/* Supervisor Private Registers */
 #define SPR1	SPRN_SPRG1
@@ -400,6 +409,7 @@
 #define SRR1	SPRN_SRR1	/* Save and Restore Register 1 */
 #define SRR2	SPRN_SRR2	/* Save and Restore Register 2 */
 #define SRR3	SPRN_SRR3	/* Save and Restore Register 3 */
+#define SVR	SPRN_SVR	/* System Version Register */
 #define ICTC	SPRN_ICTC	/* Instruction Cache Throttling Control Reg */
 #define THRM1	SPRN_THRM1	/* Thermal Management Register 1 */
 #define THRM2	SPRN_THRM2	/* Thermal Management Register 2 */
@@ -444,7 +454,7 @@
 #define PVR_440GP_RC2	0x40200481
 #define PVR_440GX_RA	0x51b21850
 #define PVR_440GX_RB	0x51b21851
-#define PVR_440GX_RB1	0x51b21852
+#define PVR_440GX_RC	0x51b21892
 #define PVR_601		0x00010000
 #define PVR_602		0x00050000
 #define PVR_603		0x00030000
@@ -462,6 +472,8 @@
 #define PVR_7400	0x000C0000
 #define PVR_7410	0x800C0000
 #define PVR_7450	0x80000000
+#define PVR_8540	0x80200000
+#define PVR_8560	0x80200000
 /*
  * For the 8xx processors, all of them report the same PVR family for
  * the PowerPC core. The various versions of these processors must be
@@ -476,6 +488,13 @@
 #define PVR_8245	0x80811014
 #define PVR_8260	PVR_8240
 
+/* System Version Numbers */
+#define SVR_8540	0x80300000
+#define SVR_8541E	0x807A0000
+#define SVR_8555E	0x80790000
+#define SVR_8560	0x80700000
+
+#if 0
 /* Segment Registers */
 #define SR0	0
 #define SR1	1
@@ -493,6 +512,7 @@
 #define SR13	13
 #define SR14	14
 #define SR15	15
+#endif
 
 /* Macros for setting and retrieving special purpose registers */
 #ifndef __ASSEMBLY__