X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=include%2Fasm-ppc64%2Fpaca.h;h=f893406eec1322ad73aab2a6a66b7fbf5496eb4f;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=d368afedd7355865cebbfc045391e221577a2dd0;hpb=5273a3df6485dc2ad6aa7ddd441b9a21970f003b;p=linux-2.6.git diff --git a/include/asm-ppc64/paca.h b/include/asm-ppc64/paca.h index d368afedd..f893406ee 100644 --- a/include/asm-ppc64/paca.h +++ b/include/asm-ppc64/paca.h @@ -1,11 +1,8 @@ #ifndef _PPC64_PACA_H #define _PPC64_PACA_H -/*============================================================================ - * Header File Id - * Name______________: paca.h - * - * Description_______: +/* + * include/asm-ppc64/paca.h * * This control block defines the PACA which defines the processor * specific data for each logical processor on the system. @@ -18,135 +15,104 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ -#include - -#define N_EXC_STACK 2 -/*----------------------------------------------------------------------------- - * Other Includes - *----------------------------------------------------------------------------- - */ -#include +#include +#include +#include #include -#include -#include #include -#include extern struct paca_struct paca[]; register struct paca_struct *local_paca asm("r13"); #define get_paca() local_paca -/*============================================================================ - * Name_______: paca - * - * Description: - * - * Defines the layout of the paca. - * - * This structure is not directly accessed by PLIC or the SP except - * for the first two pointers that point to the ItLpPaca area and the - * ItLpRegSave area for this processor. Both the ItLpPaca and - * ItLpRegSave objects are currently contained within the - * PACA but they do not need to be. +struct task_struct; +struct ItLpQueue; + +/* + * Defines the layout of the paca. * - *============================================================================ + * This structure is not directly accessed by firmware or the service + * processor except for the first two pointers that point to the + * lppaca area and the ItLpRegSave area for this CPU. Both the + * lppaca and ItLpRegSave objects are currently contained within the + * PACA but they do not need to be. */ struct paca_struct { -/*===================================================================================== - * CACHE_LINE_1 0x0000 - 0x007F - *===================================================================================== - */ - struct ItLpPaca *xLpPacaPtr; /* Pointer to LpPaca for PLIC 0x00 */ - struct ItLpRegSave *xLpRegSavePtr; /* Pointer to LpRegSave for PLIC 0x08 */ - u64 xCurrent; /* Pointer to current 0x10 */ - u16 xPacaIndex; /* Logical processor number 0x18 */ - u16 xHwProcNum; /* Physical processor number 0x1A */ - u32 default_decr; /* Default decrementer value 0x1c */ - u64 xKsave; /* Saved Kernel stack addr or zero 0x20 */ - struct ItLpQueue *lpQueuePtr; /* LpQueue handled by this processor 0x28 */ - u64 xTOC; /* Kernel TOC address 0x30 */ - STAB xStab_data; /* Segment table information 0x38,0x40,0x48 */ - u8 *exception_sp; /* 0x50 */ - u8 xProcEnabled; /* 0x58 */ - u8 prof_enabled; /* 1=iSeries profiling enabled 0x59 */ - u8 resv1[38]; /* 0x5a-0x7f*/ + /* + * Because hw_cpu_id, unlike other paca fields, is accessed + * routinely from other CPUs (from the IRQ code), we stick to + * read-only (after boot) fields in the first cacheline to + * avoid cacheline bouncing. + */ -/*===================================================================================== - * CACHE_LINE_2 0x0080 - 0x00FF - *===================================================================================== - */ - u64 spare1; /* 0x00 */ - u64 spare2; /* 0x08 */ - u64 spare3; /* 0x10 */ - u64 spare4; /* 0x18 */ - u64 next_jiffy_update_tb; /* TB value for next jiffy update 0x20 */ - u32 lpEvent_count; /* lpEvents processed 0x28 */ - u32 prof_multiplier; /* 0x2C */ - u32 prof_counter; /* 0x30 */ - u32 prof_shift; /* iSeries shift for profile bucket size0x34 */ - u32 *prof_buffer; /* iSeries profiling buffer 0x38 */ - u32 *prof_stext; /* iSeries start of kernel text 0x40 */ - u32 prof_len; /* iSeries length of profile buffer -1 0x48 */ - u8 yielded; /* 0 = this processor is running 0x4c */ - /* 1 = this processor is yielded */ - u8 rsvd2[128-77]; /* 0x49 */ + /* + * MAGIC: These first two pointers can't be moved - they're + * accessed by the firmware + */ + struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */ + struct ItLpRegSave *reg_save_ptr; /* Pointer to LpRegSave for PLIC */ -/*===================================================================================== - * CACHE_LINE_3 0x0100 - 0x017F - *===================================================================================== - */ - u8 xProcStart; /* At startup, processor spins until 0x100 */ - /* xProcStart becomes non-zero. */ - u8 rsvd3[127]; - -/*===================================================================================== - * CACHE_LINE_4-8 0x0180 - 0x03FF Contains ItLpPaca - *===================================================================================== - */ - struct ItLpPaca xLpPaca; /* Space for ItLpPaca */ - -/*===================================================================================== - * CACHE_LINE_9-16 0x0400 - 0x07FF Contains ItLpRegSave - *===================================================================================== - */ - struct ItLpRegSave xRegSav; /* Register save for proc */ + /* + * MAGIC: the spinlock functions in arch/ppc64/lib/locks.c + * load lock_token and paca_index with a single lwz + * instruction. They must travel together and be properly + * aligned. + */ + u16 lock_token; /* Constant 0x8000, used in locks */ + u16 paca_index; /* Logical processor number */ -/*===================================================================================== - * CACHE_LINE_17-18 0x0800 - 0x08FF Reserved - *===================================================================================== - */ - struct rtas_args xRtas; /* Per processor RTAS struct */ - u64 xR1; /* r1 save for RTAS calls */ - u64 xSavedMsr; /* Old msr saved here by HvCall */ - u8 rsvd5[256-16-sizeof(struct rtas_args)]; + u32 default_decr; /* Default decrementer value */ + struct ItLpQueue *lpqueue_ptr; /* LpQueue handled by this CPU */ + u64 kernel_toc; /* Kernel TOC address */ + u64 stab_real; /* Absolute address of segment table */ + u64 stab_addr; /* Virtual address of segment table */ + void *emergency_sp; /* pointer to emergency stack */ + s16 hw_cpu_id; /* Physical processor number */ + u8 cpu_start; /* At startup, processor spins until */ + /* this becomes non-zero. */ -/*===================================================================================== - * CACHE_LINE_19-30 0x0900 - 0x0EFF Reserved - *===================================================================================== - */ - u64 slb_shadow[0x20]; - u64 dispatch_log; - u8 rsvd6[0x500 - 0x8]; + /* + * Now, starting in cacheline 2, the exception save areas + */ + u64 exgen[8] __attribute__((aligned(0x80))); /* used for most interrupts/exceptions */ + u64 exmc[8]; /* used for machine checks */ + u64 exslb[8]; /* used for SLB/segment table misses + * on the linear mapping */ + mm_context_t context; + u16 slb_cache[SLB_CACHE_ENTRIES]; + u16 slb_cache_ptr; -/*===================================================================================== - * CACHE_LINE_31 0x0F00 - 0x0F7F Exception stack - *===================================================================================== - */ - u8 exception_stack[N_EXC_STACK*EXC_FRAME_SIZE]; + /* + * then miscellaneous read-write fields + */ + struct task_struct *__current; /* Pointer to current */ + u64 kstack; /* Saved Kernel stack addr */ + u64 stab_rr; /* stab/slb round-robin counter */ + u64 next_jiffy_update_tb; /* TB value for next jiffy update */ + u64 saved_r1; /* r1 save for RTAS calls */ + u64 saved_msr; /* MSR saved here by enter_rtas */ + u32 lpevent_count; /* lpevents processed */ + u8 proc_enabled; /* irq soft-enable flag */ -/*===================================================================================== - * CACHE_LINE_32 0x0F80 - 0x0FFF Reserved - *===================================================================================== - */ - u8 rsvd7[0x80]; /* Give the stack some rope ... */ + /* not yet used */ + u64 exdsi[8]; /* used for linear mapping hash table misses */ -/*===================================================================================== - * Page 2 Reserved for guard page. Also used as a stack early in SMP boots before - * relocation is enabled. - *===================================================================================== - */ - u8 guard[0x1000]; /* ... and then hang 'em */ + /* + * iSeries structure which the hypervisor knows about - + * this structure should not cross a page boundary. + * The vpa_init/register_vpa call is now known to fail if the + * lppaca structure crosses a page boundary. + * The lppaca is also used on POWER5 pSeries boxes. + * The lppaca is 640 bytes long, and cannot readily change + * since the hypervisor knows its layout, so a 1kB + * alignment will suffice to ensure that it doesn't + * cross a page boundary. + */ + struct lppaca lppaca __attribute__((__aligned__(0x400))); +#ifdef CONFIG_PPC_ISERIES + struct ItLpRegSave reg_save; +#endif }; #endif /* _PPC64_PACA_H */