X-Git-Url: http://git.onelab.eu/?a=blobdiff_plain;f=include%2Fasm-sparc64%2Fio.h;h=6661a23b6883a45cad149a1b8f8e3dace9a037c7;hb=6a77f38946aaee1cd85eeec6cf4229b204c15071;hp=7861627d9a924efd70de0b63c8f3668c9cccc0be;hpb=87fc8d1bb10cd459024a742c6a10961fefcef18f;p=linux-2.6.git diff --git a/include/asm-sparc64/io.h b/include/asm-sparc64/io.h index 7861627d9..6661a23b6 100644 --- a/include/asm-sparc64/io.h +++ b/include/asm-sparc64/io.h @@ -114,7 +114,7 @@ extern void insl(void __iomem *addr, void *dst, unsigned long count); #define iowrite32_rep(a,s,c) outsl(a,s,c) /* Memory functions, same as I/O accesses on Ultra. */ -static inline u8 _readb(void __iomem *addr) +static inline u8 _readb(const volatile void __iomem *addr) { u8 ret; __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */" @@ -123,7 +123,7 @@ static inline u8 _readb(void __iomem *addr) return ret; } -static inline u16 _readw(void __iomem *addr) +static inline u16 _readw(const volatile void __iomem *addr) { u16 ret; __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */" @@ -133,7 +133,7 @@ static inline u16 _readw(void __iomem *addr) return ret; } -static inline u32 _readl(void __iomem *addr) +static inline u32 _readl(const volatile void __iomem *addr) { u32 ret; __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */" @@ -143,7 +143,7 @@ static inline u32 _readl(void __iomem *addr) return ret; } -static inline u64 _readq(void __iomem *addr) +static inline u64 _readq(const volatile void __iomem *addr) { u64 ret; __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */" @@ -153,28 +153,28 @@ static inline u64 _readq(void __iomem *addr) return ret; } -static inline void _writeb(u8 b, void __iomem *addr) +static inline void _writeb(u8 b, volatile void __iomem *addr) { __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */" : /* no outputs */ : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); } -static inline void _writew(u16 w, void __iomem *addr) +static inline void _writew(u16 w, volatile void __iomem *addr) { __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */" : /* no outputs */ : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); } -static inline void _writel(u32 l, void __iomem *addr) +static inline void _writel(u32 l, volatile void __iomem *addr) { __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */" : /* no outputs */ : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); } -static inline void _writeq(u64 q, void __iomem *addr) +static inline void _writeq(u64 q, volatile void __iomem *addr) { __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */" : /* no outputs */ @@ -284,7 +284,7 @@ static __inline__ void _raw_writeq(u64 q, unsigned long addr) /* Now, SBUS variants, only difference from PCI is that we do * not use little-endian ASIs. */ -static inline u8 _sbus_readb(void __iomem *addr) +static inline u8 _sbus_readb(const volatile void __iomem *addr) { u8 ret; @@ -295,7 +295,7 @@ static inline u8 _sbus_readb(void __iomem *addr) return ret; } -static inline u16 _sbus_readw(void __iomem *addr) +static inline u16 _sbus_readw(const volatile void __iomem *addr) { u16 ret; @@ -306,7 +306,7 @@ static inline u16 _sbus_readw(void __iomem *addr) return ret; } -static inline u32 _sbus_readl(void __iomem *addr) +static inline u32 _sbus_readl(const volatile void __iomem *addr) { u32 ret; @@ -317,7 +317,7 @@ static inline u32 _sbus_readl(void __iomem *addr) return ret; } -static inline u64 _sbus_readq(void __iomem *addr) +static inline u64 _sbus_readq(const volatile void __iomem *addr) { u64 ret; @@ -328,28 +328,28 @@ static inline u64 _sbus_readq(void __iomem *addr) return ret; } -static inline void _sbus_writeb(u8 b, void __iomem *addr) +static inline void _sbus_writeb(u8 b, volatile void __iomem *addr) { __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */" : /* no outputs */ : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); } -static inline void _sbus_writew(u16 w, void __iomem *addr) +static inline void _sbus_writew(u16 w, volatile void __iomem *addr) { __asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */" : /* no outputs */ : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); } -static inline void _sbus_writel(u32 l, void __iomem *addr) +static inline void _sbus_writel(u32 l, volatile void __iomem *addr) { __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */" : /* no outputs */ : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); } -static inline void _sbus_writeq(u64 l, void __iomem *addr) +static inline void _sbus_writeq(u64 l, volatile void __iomem *addr) { __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */" : /* no outputs */ @@ -365,35 +365,31 @@ static inline void _sbus_writeq(u64 l, void __iomem *addr) #define sbus_writel(__l, __addr) _sbus_writel(__l, __addr) #define sbus_writeq(__l, __addr) _sbus_writeq(__l, __addr) -static inline void __iomem*_sbus_memset_io(void __iomem *dst, int c, - __kernel_size_t n) +static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n) { while(n--) { sbus_writeb(c, dst); dst++; } - return (void *) dst; } #define sbus_memset_io(d,c,sz) _sbus_memset_io(d,c,sz) -static inline void __iomem * -_memset_io(void __iomem *dst, int c, __kernel_size_t n) +static inline void +_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n) { - void __iomem *d = dst; + volatile void __iomem *d = dst; while (n--) { writeb(c, d); d++; } - - return dst; } #define memset_io(d,c,sz) _memset_io(d,c,sz) -static inline void __iomem * -_memcpy_fromio(void *dst, void __iomem *src, __kernel_size_t n) +static inline void +_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n) { char *d = dst; @@ -402,35 +398,32 @@ _memcpy_fromio(void *dst, void __iomem *src, __kernel_size_t n) *d++ = tmp; src++; } - - return dst; } #define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz) -static inline void __iomem * -_memcpy_toio(void __iomem *dst, const void *src, __kernel_size_t n) +static inline void +_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n) { const char *s = src; - void __iomem *d = dst; + volatile void __iomem *d = dst; while (n--) { char tmp = *s++; writeb(tmp, d); d++; } - return dst; } #define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz) -static inline int check_signature(unsigned long io_addr, +static inline int check_signature(void __iomem *io_addr, const unsigned char *signature, int length) { int retval = 0; do { - if (readb((void __iomem *)io_addr) != *signature++) + if (readb(io_addr) != *signature++) goto out; io_addr++; } while (--length); @@ -439,14 +432,23 @@ out: return retval; } +#define mmiowb() + #ifdef __KERNEL__ /* On sparc64 we have the whole physical IO address space accessible * using physically addressed loads and stores, so this does nothing. */ -#define ioremap(__offset, __size) ((void __iomem *)(__offset)) +static inline void __iomem *ioremap(unsigned long offset, unsigned long size) +{ + return (void __iomem *)offset; +} + #define ioremap_nocache(X,Y) ioremap((X),(Y)) -#define iounmap(__addr) do { (void)(__addr); } while(0) + +static inline void iounmap(volatile void __iomem *addr) +{ +} #define ioread8(X) readb(X) #define ioread16(X) readw(X)