This commit was generated by cvs2svn to compensate for changes in r716,

which included commits to RCS files with non-trunk default branches.

diff --git a/Documentation/aoe/aoe.txt b/Documentation/aoe/aoe.txt
index 7af899f..3a4dbe4 100644 (file)
--- a/Documentation/aoe/aoe.txt
+++ b/Documentation/aoe/aoe.txt
@@ -4,11 +4,28 @@ The EtherDrive (R) HOWTO for users of 2.6 kernels is found at ...
 
   It has many tips and hints!
 
 
   It has many tips and hints!
 

+The aoetools are userland programs that are designed to work with this
+driver.  The aoetools are on sourceforge.
+
+  http://aoetools.sourceforge.net/
+
+The scripts in this Documentation/aoe directory are intended to
+document the use of the driver and are not necessary if you install
+the aoetools.
+
+

 CREATING DEVICE NODES
 
 CREATING DEVICE NODES
 

-  Users of udev should find device nodes created automatically.  Two
-  scripts are provided in Documentation/aoe as examples of static
-  device node creation for using the aoe driver.
+  Users of udev should find the block device nodes created
+  automatically, but to create all the necessary device nodes, use the
+  udev configuration rules provided in udev.txt (in this directory).
+
+  There is a udev-install.sh script that shows how to install these
+  rules on your system.
+
+  If you are not using udev, two scripts are provided in
+  Documentation/aoe as examples of static device node creation for
+  using the aoe driver.

 
     rm -rf /dev/etherd
     sh Documentation/aoe/mkdevs.sh /dev/etherd
 
     rm -rf /dev/etherd
     sh Documentation/aoe/mkdevs.sh /dev/etherd


@@ -28,14 +45,15 @@ USING DEVICE NODES
 
   "echo eth2 eth4 > /dev/etherd/interfaces" tells the aoe driver to
   limit ATA over Ethernet traffic to eth2 and eth4.  AoE traffic from
 
   "echo eth2 eth4 > /dev/etherd/interfaces" tells the aoe driver to
   limit ATA over Ethernet traffic to eth2 and eth4.  AoE traffic from

-  untrusted networks should be ignored as a matter of security.
+  untrusted networks should be ignored as a matter of security.  See
+  also the aoe_iflist driver option described below.

 
   "echo > /dev/etherd/discover" tells the driver to find out what AoE
   devices are available.
 
   These character devices may disappear and be replaced by sysfs
 
   "echo > /dev/etherd/discover" tells the driver to find out what AoE
   devices are available.
 
   These character devices may disappear and be replaced by sysfs

-  counterparts, so distribution maintainers are encouraged to create
-  scripts that use these devices.
+  counterparts.  Using the commands in aoetools insulates users from
+  these implementation details.

 
   The block devices are named like this:
 
 
   The block devices are named like this:
 


@@ -59,7 +77,8 @@ USING SYSFS
   through which we are communicating with the remote AoE device.
 
   There is a script in this directory that formats this information
   through which we are communicating with the remote AoE device.
 
   There is a script in this directory that formats this information

-  in a convenient way.
+  in a convenient way.  Users with aoetools can use the aoe-stat
+  command.

 
   root@makki root# sh Documentation/aoe/status.sh 
      e10.0            eth3              up
 
   root@makki root# sh Documentation/aoe/status.sh 
      e10.0            eth3              up


@@ -82,3 +101,23 @@ USING SYSFS
       e4.7            eth1              up
       e4.8            eth1              up
       e4.9            eth1              up
       e4.7            eth1              up
       e4.8            eth1              up
       e4.9            eth1              up

+
+  Use /sys/module/aoe/parameters/aoe_iflist (or better, the driver
+  option discussed below) instead of /dev/etherd/interfaces to limit
+  AoE traffic to the network interfaces in the given
+  whitespace-separated list.  Unlike the old character device, the
+  sysfs entry can be read from as well as written to.
+
+  It's helpful to trigger discovery after setting the list of allowed
+  interfaces.  The aoetools package provides an aoe-discover script
+  for this purpose.  You can also directly use the
+  /dev/etherd/discover special file described above.
+
+DRIVER OPTIONS
+
+  There is a boot option for the built-in aoe driver and a
+  corresponding module parameter, aoe_iflist.  Without this option,
+  all network interfaces may be used for ATA over Ethernet.  Here is a
+  usage example for the module parameter.
+
+    modprobe aoe_iflist="eth1 eth3"

diff --git a/Documentation/aoe/mkshelf.sh b/Documentation/aoe/mkshelf.sh
index 4093283..8bacf9f 100644 (file)
--- a/Documentation/aoe/mkshelf.sh
+++ b/Documentation/aoe/mkshelf.sh
@@ -2,6 +2,7 @@
 
 if test "$#" != "2"; then
        echo "Usage: sh `basename $0` {dir} {shelfaddress}" 1>&2
 
 if test "$#" != "2"; then
        echo "Usage: sh `basename $0` {dir} {shelfaddress}" 1>&2

+       echo "       n_partitions=16 sh `basename $0` {dir} {shelfaddress}" 1>&2

        exit 1
 fi
 n_partitions=${n_partitions:-16}
        exit 1
 fi
 n_partitions=${n_partitions:-16}

diff --git a/Documentation/aoe/status.sh b/Documentation/aoe/status.sh
index 8934ccc..751f3be 100644 (file)
--- a/Documentation/aoe/status.sh
+++ b/Documentation/aoe/status.sh
@@ -4,19 +4,18 @@
 set -e
 format="%8s\t%8s\t%8s\n"
 me=`basename $0`
 set -e
 format="%8s\t%8s\t%8s\n"
 me=`basename $0`

+sysd=${sysfs_dir:-/sys}

 
 # printf "$format" device mac netif state
 
 
 # printf "$format" device mac netif state
 

-test -z "`mount | grep sysfs`" && {
+# Suse 9.1 Pro doesn't put /sys in /etc/mtab
+#test -z "`mount | grep sysfs`" && {
+test ! -d "$sysd/block" && {

        echo "$me Error: sysfs is not mounted" 1>&2
        exit 1
 }
        echo "$me Error: sysfs is not mounted" 1>&2
        exit 1
 }

-test -z "`lsmod | grep '^aoe'`" && {
-       echo  "$me Error: aoe module is not loaded" 1>&2
-       exit 1
-}

 
 

-for d in `ls -d /sys/block/etherd* 2>/dev/null | grep -v p` end; do
+for d in `ls -d $sysd/block/etherd* 2>/dev/null | grep -v p` end; do

        # maybe ls comes up empty, so we use "end"
        test $d = end && continue
 
        # maybe ls comes up empty, so we use "end"
        test $d = end && continue
 

diff --git a/Documentation/filesystems/sysfs-pci.txt b/Documentation/filesystems/sysfs-pci.txt
index e97d024..988a62f 100644 (file)
--- a/Documentation/filesystems/sysfs-pci.txt
+++ b/Documentation/filesystems/sysfs-pci.txt
@@ -7,7 +7,6 @@ that support it.  For example, a given bus might look like this:
      |-- 0000:17:00.0
      |   |-- class
      |   |-- config
      |-- 0000:17:00.0
      |   |-- class
      |   |-- config

-     |   |-- detach_state

      |   |-- device
      |   |-- irq
      |   |-- local_cpus
      |   |-- device
      |   |-- irq
      |   |-- local_cpus


@@ -19,7 +18,7 @@ that support it.  For example, a given bus might look like this:
      |   |-- subsystem_device
      |   |-- subsystem_vendor
      |   `-- vendor
      |   |-- subsystem_device
      |   |-- subsystem_vendor
      |   `-- vendor

-     `-- detach_state
+     `-- ...

 
 The topmost element describes the PCI domain and bus number.  In this case,
 the domain number is 0000 and the bus number is 17 (both values are in hex).
 
 The topmost element describes the PCI domain and bus number.  In this case,
 the domain number is 0000 and the bus number is 17 (both values are in hex).


@@ -31,7 +30,6 @@ files, each with their own function.
        ----               --------
        class              PCI class (ascii, ro)
        config             PCI config space (binary, rw)
        ----               --------
        class              PCI class (ascii, ro)
        config             PCI config space (binary, rw)

-       detach_state       connection status (bool, rw)

        device             PCI device (ascii, ro)
        irq                IRQ number (ascii, ro)
        local_cpus         nearby CPU mask (cpumask, ro)
        device             PCI device (ascii, ro)
        irq                IRQ number (ascii, ro)
        local_cpus         nearby CPU mask (cpumask, ro)


@@ -85,4 +83,4 @@ useful return codes should be provided.
 
 Legacy resources are protected by the HAVE_PCI_LEGACY define.  Platforms
 wishing to support legacy functionality should define it and provide
 
 Legacy resources are protected by the HAVE_PCI_LEGACY define.  Platforms
 wishing to support legacy functionality should define it and provide

-pci_legacy_read, pci_legacy_write and pci_mmap_legacy_page_range functions.
\ No newline at end of file
+pci_legacy_read, pci_legacy_write and pci_mmap_legacy_page_range functions.

diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index 1d06d36..8a05a12 100644 (file)
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -3,7 +3,7 @@
  *
  * Board setup for ADI Engineering and IXDGP425 boards
  *
  *
  * Board setup for ADI Engineering and IXDGP425 boards
  *

- * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ * Copyright (C) 2003-2005 MontaVista Software, Inc.

  *
  * Author: Deepak Saxena <dsaxena@plexity.net>
  */
  *
  * Author: Deepak Saxena <dsaxena@plexity.net>
  */


@@ -13,7 +13,7 @@
 #include <linux/device.h>
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/device.h>
 #include <linux/serial.h>
 #include <linux/tty.h>

-#include <linux/serial_core.h>
+#include <linux/serial_8250.h>

 
 #include <asm/types.h>
 #include <asm/setup.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>


@@ -24,39 +24,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 

-#ifdef __ARMEB__
-#define        REG_OFFSET      3
-#else
-#define        REG_OFFSET      0
-#endif
-
-/*
- * Only one serial port is connected on the Coyote & IXDPG425
- */
-static struct uart_port coyote_serial_port = {
-       .membase        = (char*)(IXP4XX_UART2_BASE_VIRT + REG_OFFSET),
-       .mapbase        = (IXP4XX_UART2_BASE_PHYS),
-       .irq            = IRQ_IXP4XX_UART2,
-       .flags          = UPF_SKIP_TEST,
-       .iotype         = UPIO_MEM,     
-       .regshift       = 2,
-       .uartclk        = IXP4XX_UART_XTAL,
-       .line           = 0,
-       .type           = PORT_XSCALE,
-       .fifosize       = 32
-};
-

 void __init coyote_map_io(void)
 {
 void __init coyote_map_io(void)
 {

-       if (machine_is_ixdpg425()) {
-               coyote_serial_port.membase =
-                       (char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET);
-               coyote_serial_port.mapbase = IXP4XX_UART1_BASE_PHYS;
-               coyote_serial_port.irq = IRQ_IXP4XX_UART1;
-       }
-
-       early_serial_setup(&coyote_serial_port);
-

        ixp4xx_map_io();
 }
 
        ixp4xx_map_io();
 }
 


@@ -81,8 +50,35 @@ static struct platform_device coyote_flash = {
        .resource       = &coyote_flash_resource,
 };
 
        .resource       = &coyote_flash_resource,
 };
 

+static struct resource coyote_uart_resource = {
+       .start  = IXP4XX_UART2_BASE_PHYS,
+       .end    = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+       .flags  = IORESOURCE_MEM,
+};
+
+static struct plat_serial8250_port coyote_uart_data = {
+       .mapbase        = IXP4XX_UART2_BASE_PHYS,
+       .membase        = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+       .irq            = IRQ_IXP4XX_UART2,
+       .flags          = UPF_BOOT_AUTOCONF,
+       .iotype         = UPIO_MEM,
+       .regshift       = 2,
+       .uartclk        = IXP4XX_UART_XTAL,
+};
+
+static struct platform_device coyote_uart = {
+       .name           = "serial8250",
+       .id             = 0,
+       .dev                    = {
+               .platform_data  = &coyote_uart_data,
+       },
+       .num_resources  = 1,
+       .resource       = &coyote_uart_resource,
+};
+

 static struct platform_device *coyote_devices[] __initdata = {
 static struct platform_device *coyote_devices[] __initdata = {

-       &coyote_flash
+       &coyote_flash,
+       &coyote_uart

 };
 
 static void __init coyote_init(void)
 };
 
 static void __init coyote_init(void)


@@ -90,6 +86,14 @@ static void __init coyote_init(void)
        *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
        *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
 
        *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
        *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
 

+       if (machine_is_ixdpg425()) {
+               coyote_uart_data.membase =
+                       (char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET);
+               coyote_uart_data.mapbase = IXP4XX_UART1_BASE_PHYS;
+               coyote_uart_data.irq = IRQ_IXP4XX_UART1;
+       }
+
+

        ixp4xx_sys_init();
        platform_add_devices(coyote_devices, ARRAY_SIZE(coyote_devices));
 }
        ixp4xx_sys_init();
        platform_add_devices(coyote_devices, ARRAY_SIZE(coyote_devices));
 }

diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 77006d9..77346c1 100644 (file)
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -3,7 +3,7 @@
  *
  * IXDP425/IXCDP1100 board-setup 
  *
  *
  * IXDP425/IXCDP1100 board-setup 
  *

- * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ * Copyright (C) 2003-2005 MontaVista Software, Inc.

  *
  * Author: Deepak Saxena <dsaxena@plexity.net>
  */
  *
  * Author: Deepak Saxena <dsaxena@plexity.net>
  */


@@ -13,7 +13,7 @@
 #include <linux/device.h>
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/device.h>
 #include <linux/serial.h>
 #include <linux/tty.h>

-#include <linux/serial_core.h>
+#include <linux/serial_8250.h>

 
 #include <asm/types.h>
 #include <asm/setup.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>


@@ -24,46 +24,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 

-#ifdef __ARMEB__
-#define        REG_OFFSET      3
-#else
-#define        REG_OFFSET      0
-#endif
-
-/*
- * IXDP425 uses both chipset serial ports
- */
-static struct uart_port ixdp425_serial_ports[] = {
-       {
-               .membase        = (char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET),
-               .mapbase        = (IXP4XX_UART1_BASE_PHYS),
-               .irq            = IRQ_IXP4XX_UART1,
-               .flags          = UPF_SKIP_TEST,
-               .iotype         = UPIO_MEM,     
-               .regshift       = 2,
-               .uartclk        = IXP4XX_UART_XTAL,
-               .line           = 0,
-               .type           = PORT_XSCALE,
-               .fifosize       = 32
-       } , {
-               .membase        = (char*)(IXP4XX_UART2_BASE_VIRT + REG_OFFSET),
-               .mapbase        = (IXP4XX_UART2_BASE_PHYS),
-               .irq            = IRQ_IXP4XX_UART2,
-               .flags          = UPF_SKIP_TEST,
-               .iotype         = UPIO_MEM,     
-               .regshift       = 2,
-               .uartclk        = IXP4XX_UART_XTAL,
-               .line           = 1,
-               .type           = PORT_XSCALE,
-               .fifosize       = 32
-       }
-};
-

 void __init ixdp425_map_io(void) 
 {
 void __init ixdp425_map_io(void) 
 {

-       early_serial_setup(&ixdp425_serial_ports[0]);
-       early_serial_setup(&ixdp425_serial_ports[1]);
-

        ixp4xx_map_io();
 }
 
        ixp4xx_map_io();
 }
 


@@ -102,11 +64,55 @@ static struct platform_device ixdp425_i2c_controller = {
        .num_resources  = 0
 };
 
        .num_resources  = 0
 };
 

+static struct resource ixdp425_uart_resources[] = {
+       {
+               .start          = IXP4XX_UART1_BASE_PHYS,
+               .end            = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+               .flags          = IORESOURCE_MEM
+       },
+       {
+               .start          = IXP4XX_UART2_BASE_PHYS,
+               .end            = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+               .flags          = IORESOURCE_MEM
+       }
+};
+
+static struct plat_serial8250_port ixdp425_uart_data[] = {
+       {
+               .mapbase        = IXP4XX_UART1_BASE_PHYS,
+               .membase        = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+               .irq            = IRQ_IXP4XX_UART1,
+               .flags          = UPF_BOOT_AUTOCONF,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = IXP4XX_UART_XTAL,
+       },
+       {
+               .mapbase        = IXP4XX_UART2_BASE_PHYS,
+               .membase        = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+               .irq            = IRQ_IXP4XX_UART1,
+               .flags          = UPF_BOOT_AUTOCONF,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = IXP4XX_UART_XTAL,
+       }
+};
+
+static struct platform_device ixdp425_uart = {
+       .name                   = "serial8250",
+       .id                     = 0,
+       .dev.platform_data      = ixdp425_uart_data,
+       .num_resources          = 2,
+       .resource               = ixdp425_uart_resources
+};
+

 static struct platform_device *ixdp425_devices[] __initdata = {
        &ixdp425_i2c_controller,
 static struct platform_device *ixdp425_devices[] __initdata = {
        &ixdp425_i2c_controller,

-       &ixdp425_flash
+       &ixdp425_flash,
+       &ixdp425_uart

 };
 
 };
 

+

 static void __init ixdp425_init(void)
 {
        ixp4xx_sys_init();
 static void __init ixdp425_init(void)
 {
        ixp4xx_sys_init();

diff --git a/arch/arm26/mm/small_page.c b/arch/arm26/mm/small_page.c
index 77be86c..3044710 100644 (file)
--- a/arch/arm26/mm/small_page.c
+++ b/arch/arm26/mm/small_page.c
@@ -92,8 +92,7 @@ static unsigned long __get_small_page(int priority, struct order *order)
                page = list_entry(order->queue.next, struct page, lru);
 again:
 #ifdef PEDANTIC
                page = list_entry(order->queue.next, struct page, lru);
 again:
 #ifdef PEDANTIC

-               if (USED_MAP(page) & ~order->all_used)
-                       PAGE_BUG(page);
+               BUG_ON(USED_MAP(page) & ~order->all_used);

 #endif
                offset = ffz(USED_MAP(page));
                SET_USED(page, offset);
 #endif
                offset = ffz(USED_MAP(page));
                SET_USED(page, offset);


@@ -141,8 +140,7 @@ static void __free_small_page(unsigned long spage, struct order *order)
                        goto non_small;
 
 #ifdef PEDANTIC
                        goto non_small;
 
 #ifdef PEDANTIC

-               if (USED_MAP(page) & ~order->all_used)
-                       PAGE_BUG(page);
+               BUG_ON(USED_MAP(page) & ~order->all_used);

 #endif
 
                spage = spage >> order->shift;
 #endif
 
                spage = spage >> order->shift;

diff --git a/arch/i386/oprofile/backtrace.c b/arch/i386/oprofile/backtrace.c
index 49a0605..52d72e0 100644 (file)
--- a/arch/i386/oprofile/backtrace.c
+++ b/arch/i386/oprofile/backtrace.c
@@ -18,7 +18,6 @@ struct frame_head {
        unsigned long ret;
 } __attribute__((packed));
 
        unsigned long ret;
 } __attribute__((packed));
 

-

 static struct frame_head *
 dump_backtrace(struct frame_head * head)
 {
 static struct frame_head *
 dump_backtrace(struct frame_head * head)
 {


@@ -27,21 +26,11 @@ dump_backtrace(struct frame_head * head)
        /* frame pointers should strictly progress back up the stack
         * (towards higher addresses) */
        if (head >= head->ebp)
        /* frame pointers should strictly progress back up the stack
         * (towards higher addresses) */
        if (head >= head->ebp)

-               return 0;
+               return NULL;

 
        return head->ebp;
 }
 
 
        return head->ebp;
 }
 

-
-#ifdef CONFIG_X86_4G
-/* With a 4G kernel/user split, user pages are not directly
- * accessible from the kernel, so don't try
- */
-static int pages_present(struct frame_head * head)
-{
-       return 0;
-}
-#else

 /* check that the page(s) containing the frame head are present */
 static int pages_present(struct frame_head * head)
 {
 /* check that the page(s) containing the frame head are present */
 static int pages_present(struct frame_head * head)
 {


@@ -53,8 +42,6 @@ static int pages_present(struct frame_head * head)
 
        return check_user_page_readable(mm, (unsigned long)(head + 1));
 }
 
        return check_user_page_readable(mm, (unsigned long)(head + 1));
 }

-#endif /* CONFIG_X86_4G */
-

 
 /*
  * |             | /\ Higher addresses
 
 /*
  * |             | /\ Higher addresses

diff --git a/arch/ia64/sn/kernel/bte_error.c b/arch/ia64/sn/kernel/bte_error.c
index fd10431..fcbc748 100644 (file)
--- a/arch/ia64/sn/kernel/bte_error.c
+++ b/arch/ia64/sn/kernel/bte_error.c
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *

- * Copyright (c) 2000-2004 Silicon Graphics, Inc.  All Rights Reserved.
+ * Copyright (c) 2000-2005 Silicon Graphics, Inc.  All Rights Reserved.

  */
 
 #include <linux/types.h>
  */
 
 #include <linux/types.h>


@@ -33,48 +33,28 @@ void bte_error_handler(unsigned long);
  * Wait until all BTE related CRBs are completed
  * and then reset the interfaces.
  */
  * Wait until all BTE related CRBs are completed
  * and then reset the interfaces.
  */

-void bte_error_handler(unsigned long _nodepda)
+void shub1_bte_error_handler(unsigned long _nodepda)

 {
        struct nodepda_s *err_nodepda = (struct nodepda_s *)_nodepda;
 {
        struct nodepda_s *err_nodepda = (struct nodepda_s *)_nodepda;

-       spinlock_t *recovery_lock = &err_nodepda->bte_recovery_lock;

        struct timer_list *recovery_timer = &err_nodepda->bte_recovery_timer;
        nasid_t nasid;
        int i;
        int valid_crbs;
        struct timer_list *recovery_timer = &err_nodepda->bte_recovery_timer;
        nasid_t nasid;
        int i;
        int valid_crbs;

-       unsigned long irq_flags;
-       volatile u64 *notify;
-       bte_result_t bh_error;

        ii_imem_u_t imem;       /* II IMEM Register */
        ii_icrb0_d_u_t icrbd;   /* II CRB Register D */
        ii_ibcr_u_t ibcr;
        ii_icmr_u_t icmr;
        ii_ieclr_u_t ieclr;
 
        ii_imem_u_t imem;       /* II IMEM Register */
        ii_icrb0_d_u_t icrbd;   /* II CRB Register D */
        ii_ibcr_u_t ibcr;
        ii_icmr_u_t icmr;
        ii_ieclr_u_t ieclr;
 

-       BTE_PRINTK(("bte_error_handler(%p) - %d\n", err_nodepda,
+       BTE_PRINTK(("shub1_bte_error_handler(%p) - %d\n", err_nodepda,

                    smp_processor_id()));
 
                    smp_processor_id()));
 

-       spin_lock_irqsave(recovery_lock, irq_flags);
-

        if ((err_nodepda->bte_if[0].bh_error == BTE_SUCCESS) &&
            (err_nodepda->bte_if[1].bh_error == BTE_SUCCESS)) {
                BTE_PRINTK(("eh:%p:%d Nothing to do.\n", err_nodepda,
                            smp_processor_id()));
        if ((err_nodepda->bte_if[0].bh_error == BTE_SUCCESS) &&
            (err_nodepda->bte_if[1].bh_error == BTE_SUCCESS)) {
                BTE_PRINTK(("eh:%p:%d Nothing to do.\n", err_nodepda,
                            smp_processor_id()));

-               spin_unlock_irqrestore(recovery_lock, irq_flags);

                return;
        }
                return;
        }

-       /*
-        * Lock all interfaces on this node to prevent new transfers
-        * from being queued.
-        */
-       for (i = 0; i < BTES_PER_NODE; i++) {
-               if (err_nodepda->bte_if[i].cleanup_active) {
-                       continue;
-               }
-               spin_lock(&err_nodepda->bte_if[i].spinlock);
-               BTE_PRINTK(("eh:%p:%d locked %d\n", err_nodepda,
-                           smp_processor_id(), i));
-               err_nodepda->bte_if[i].cleanup_active = 1;
-       }

 
        /* Determine information about our hub */
        nasid = cnodeid_to_nasid(err_nodepda->bte_if[0].bte_cnode);
 
        /* Determine information about our hub */
        nasid = cnodeid_to_nasid(err_nodepda->bte_if[0].bte_cnode);


@@ -101,7 +81,6 @@ void bte_error_handler(unsigned long _nodepda)
                mod_timer(recovery_timer, HZ * 5);
                BTE_PRINTK(("eh:%p:%d Marked Giving up\n", err_nodepda,
                            smp_processor_id()));
                mod_timer(recovery_timer, HZ * 5);
                BTE_PRINTK(("eh:%p:%d Marked Giving up\n", err_nodepda,
                            smp_processor_id()));

-               spin_unlock_irqrestore(recovery_lock, irq_flags);

                return;
        }
        if (icmr.ii_icmr_fld_s.i_crb_vld != 0) {
                return;
        }
        if (icmr.ii_icmr_fld_s.i_crb_vld != 0) {


@@ -120,8 +99,6 @@ void bte_error_handler(unsigned long _nodepda)
                                BTE_PRINTK(("eh:%p:%d Valid %d, Giving up\n",
                                            err_nodepda, smp_processor_id(),
                                            i));
                                BTE_PRINTK(("eh:%p:%d Valid %d, Giving up\n",
                                            err_nodepda, smp_processor_id(),
                                            i));

-                               spin_unlock_irqrestore(recovery_lock,
-                                                      irq_flags);

                                return;
                        }
                }
                                return;
                        }
                }


@@ -146,6 +123,51 @@ void bte_error_handler(unsigned long _nodepda)
        ibcr.ii_ibcr_fld_s.i_soft_reset = 1;
        REMOTE_HUB_S(nasid, IIO_IBCR, ibcr.ii_ibcr_regval);
 
        ibcr.ii_ibcr_fld_s.i_soft_reset = 1;
        REMOTE_HUB_S(nasid, IIO_IBCR, ibcr.ii_ibcr_regval);
 

+       del_timer(recovery_timer);
+}
+
+/*
+ * Wait until all BTE related CRBs are completed
+ * and then reset the interfaces.
+ */
+void bte_error_handler(unsigned long _nodepda)
+{
+       struct nodepda_s *err_nodepda = (struct nodepda_s *)_nodepda;
+       spinlock_t *recovery_lock = &err_nodepda->bte_recovery_lock;
+       int i;
+       nasid_t nasid;
+       unsigned long irq_flags;
+       volatile u64 *notify;
+       bte_result_t bh_error;
+
+       BTE_PRINTK(("bte_error_handler(%p) - %d\n", err_nodepda,
+                   smp_processor_id()));
+
+       spin_lock_irqsave(recovery_lock, irq_flags);
+
+       /*
+        * Lock all interfaces on this node to prevent new transfers
+        * from being queued.
+        */
+       for (i = 0; i < BTES_PER_NODE; i++) {
+               if (err_nodepda->bte_if[i].cleanup_active) {
+                       continue;
+               }
+               spin_lock(&err_nodepda->bte_if[i].spinlock);
+               BTE_PRINTK(("eh:%p:%d locked %d\n", err_nodepda,
+                           smp_processor_id(), i));
+               err_nodepda->bte_if[i].cleanup_active = 1;
+       }
+
+       if (is_shub1()) {
+               shub1_bte_error_handler(_nodepda);
+       } else {
+               nasid = cnodeid_to_nasid(err_nodepda->bte_if[0].bte_cnode);
+
+               if (ia64_sn_bte_recovery(nasid))
+                       panic("bte_error_handler(): Fatal BTE Error");
+       }
+

        for (i = 0; i < BTES_PER_NODE; i++) {
                bh_error = err_nodepda->bte_if[i].bh_error;
                if (bh_error != BTE_SUCCESS) {
        for (i = 0; i < BTES_PER_NODE; i++) {
                bh_error = err_nodepda->bte_if[i].bh_error;
                if (bh_error != BTE_SUCCESS) {


@@ -165,8 +187,6 @@ void bte_error_handler(unsigned long _nodepda)
                spin_unlock(&err_nodepda->bte_if[i].spinlock);
        }
 
                spin_unlock(&err_nodepda->bte_if[i].spinlock);
        }
 

-       del_timer(recovery_timer);
-

        spin_unlock_irqrestore(recovery_lock, irq_flags);
 }
 
        spin_unlock_irqrestore(recovery_lock, irq_flags);
 }
 

diff --git a/arch/ia64/sn/pci/Makefile b/arch/ia64/sn/pci/Makefile
index b5dca00..2f915bc 100644 (file)
--- a/arch/ia64/sn/pci/Makefile
+++ b/arch/ia64/sn/pci/Makefile
@@ -7,4 +7,4 @@
 #
 # Makefile for the sn pci general routines.
 
 #
 # Makefile for the sn pci general routines.
 

-obj-y := pci_dma.o pcibr/ 
+obj-y := pci_dma.o tioca_provider.o pcibr/ 

diff --git a/arch/ia64/sn/pci/pcibr/pcibr_reg.c b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
index 74a74a7..865c11c 100644 (file)
--- a/arch/ia64/sn/pci/pcibr/pcibr_reg.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
@@ -8,8 +8,8 @@
 
 #include <linux/types.h>
 #include <linux/interrupt.h>
 
 #include <linux/types.h>
 #include <linux/interrupt.h>

-#include "pci/pcibus_provider_defs.h"
-#include "pci/pcidev.h"
+#include <asm/sn/pcibus_provider_defs.h>
+#include <asm/sn/pcidev.h>

 #include "pci/tiocp.h"
 #include "pci/pic.h"
 #include "pci/pcibr_provider.h"
 #include "pci/tiocp.h"
 #include "pci/pic.h"
 #include "pci/pcibr_provider.h"

diff --git a/arch/mips/pci/ops-vr41xx.c b/arch/mips/pci/ops-vr41xx.c
index 4465460..430429b 100644 (file)
--- a/arch/mips/pci/ops-vr41xx.c
+++ b/arch/mips/pci/ops-vr41xx.c
@@ -3,7 +3,7 @@
  *
  *  Copyright (C) 2001-2003 MontaVista Software Inc.
  *    Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
  *
  *  Copyright (C) 2001-2003 MontaVista Software Inc.
  *    Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>

- *  Copyright (C) 2004  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ *  Copyright (C) 2004-2005  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by


@@ -29,8 +29,8 @@
 
 #include <asm/io.h>
 
 
 #include <asm/io.h>
 

-#define PCICONFDREG    KSEG1ADDR(0x0f000c14)
-#define PCICONFAREG    KSEG1ADDR(0x0f000c18)
+#define PCICONFDREG    (void __iomem *)KSEG1ADDR(0x0f000c14)
+#define PCICONFAREG    (void __iomem *)KSEG1ADDR(0x0f000c18)

 
 static inline int set_pci_configuration_address(unsigned char number,
                                                 unsigned int devfn, int where)
 
 static inline int set_pci_configuration_address(unsigned char number,
                                                 unsigned int devfn, int where)

diff --git a/arch/ppc/configs/chestnut_defconfig b/arch/ppc/configs/chestnut_defconfig
index 2c34eb8..e219aad 100644 (file)
--- a/arch/ppc/configs/chestnut_defconfig
+++ b/arch/ppc/configs/chestnut_defconfig
@@ -1,11 +1,12 @@
 #
 # Automatically generated make config: don't edit
 #
 # Automatically generated make config: don't edit

-# Linux kernel version: 2.6.10-rc2
-# Tue Dec  7 16:02:09 2004
+# Linux kernel version: 2.6.11
+# Fri Mar 11 14:32:49 2005

 #
 CONFIG_MMU=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
 #
 CONFIG_MMU=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y

+CONFIG_GENERIC_CALIBRATE_DELAY=y

 CONFIG_HAVE_DEC_LOCK=y
 CONFIG_PPC=y
 CONFIG_PPC32=y
 CONFIG_HAVE_DEC_LOCK=y
 CONFIG_PPC=y
 CONFIG_PPC32=y


@@ -35,6 +36,7 @@ CONFIG_KOBJECT_UEVENT=y
 # CONFIG_EMBEDDED is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 # CONFIG_EMBEDDED is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set

+CONFIG_BASE_FULL=y

 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set


@@ -44,6 +46,7 @@ CONFIG_CC_ALIGN_LABELS=0
 CONFIG_CC_ALIGN_LOOPS=0
 CONFIG_CC_ALIGN_JUMPS=0
 # CONFIG_TINY_SHMEM is not set
 CONFIG_CC_ALIGN_LOOPS=0
 CONFIG_CC_ALIGN_JUMPS=0
 # CONFIG_TINY_SHMEM is not set

+CONFIG_BASE_SMALL=0

 
 #
 # Loadable module support
 
 #
 # Loadable module support


@@ -78,7 +81,9 @@ CONFIG_NOT_COHERENT_CACHE=y
 #
 # CONFIG_PPC_MULTIPLATFORM is not set
 # CONFIG_APUS is not set
 #
 # CONFIG_PPC_MULTIPLATFORM is not set
 # CONFIG_APUS is not set

+# CONFIG_KATANA is not set

 # CONFIG_WILLOW is not set
 # CONFIG_WILLOW is not set

+# CONFIG_CPCI690 is not set

 # CONFIG_PCORE is not set
 # CONFIG_POWERPMC250 is not set
 CONFIG_CHESTNUT=y
 # CONFIG_PCORE is not set
 # CONFIG_POWERPMC250 is not set
 CONFIG_CHESTNUT=y


@@ -91,6 +96,7 @@ CONFIG_CHESTNUT=y
 # CONFIG_PRPMC750 is not set
 # CONFIG_PRPMC800 is not set
 # CONFIG_SANDPOINT is not set
 # CONFIG_PRPMC750 is not set
 # CONFIG_PRPMC800 is not set
 # CONFIG_SANDPOINT is not set

+# CONFIG_RADSTONE_PPC7D is not set

 # CONFIG_ADIR is not set
 # CONFIG_K2 is not set
 # CONFIG_PAL4 is not set
 # CONFIG_ADIR is not set
 # CONFIG_K2 is not set
 # CONFIG_PAL4 is not set


@@ -101,7 +107,9 @@ CONFIG_CHESTNUT=y
 # CONFIG_RPX8260 is not set
 # CONFIG_TQM8260 is not set
 # CONFIG_ADS8272 is not set
 # CONFIG_RPX8260 is not set
 # CONFIG_TQM8260 is not set
 # CONFIG_ADS8272 is not set

+# CONFIG_PQ2FADS is not set

 # CONFIG_LITE5200 is not set
 # CONFIG_LITE5200 is not set

+# CONFIG_MPC834x_SYS is not set

 CONFIG_MV64360=y
 CONFIG_MV64X60=y
 
 CONFIG_MV64360=y
 CONFIG_MV64X60=y
 


@@ -127,6 +135,15 @@ CONFIG_PCI_DOMAINS=y
 CONFIG_PCI_LEGACY_PROC=y
 CONFIG_PCI_NAMES=y
 
 CONFIG_PCI_LEGACY_PROC=y
 CONFIG_PCI_NAMES=y
 

+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PC-card bridges
+#
+

 #
 # Advanced setup
 #
 #
 # Advanced setup
 #


@@ -154,6 +171,7 @@ CONFIG_BOOT_LOAD=0x00800000
 #
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 #
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y

+# CONFIG_FW_LOADER is not set

 
 #
 # Memory Technology Devices (MTD)
 
 #
 # Memory Technology Devices (MTD)


@@ -181,6 +199,9 @@ CONFIG_MTD_CFI=y
 # CONFIG_MTD_JEDECPROBE is not set
 CONFIG_MTD_GEN_PROBE=y
 # CONFIG_MTD_CFI_ADV_OPTIONS is not set
 # CONFIG_MTD_JEDECPROBE is not set
 CONFIG_MTD_GEN_PROBE=y
 # CONFIG_MTD_CFI_ADV_OPTIONS is not set

+# CONFIG_MTD_CFI_NOSWAP is not set
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set

 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
 CONFIG_MTD_MAP_BANK_WIDTH_4=y
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
 CONFIG_MTD_MAP_BANK_WIDTH_4=y


@@ -198,13 +219,16 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set

+# CONFIG_MTD_XIP is not set

 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set

-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_CHESTNUT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0xfc000000
+CONFIG_MTD_PHYSMAP_LEN=0x02000000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=4

 
 #
 # Self-contained MTD device drivers
 
 #
 # Self-contained MTD device drivers


@@ -214,6 +238,7 @@ CONFIG_MTD_CHESTNUT=y
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
 # CONFIG_MTD_BLKMTD is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
 # CONFIG_MTD_BLKMTD is not set

+# CONFIG_MTD_BLOCK2MTD is not set

 
 #
 # Disk-On-Chip Device Drivers
 
 #
 # Disk-On-Chip Device Drivers


@@ -244,11 +269,13 @@ CONFIG_MTD_CHESTNUT=y
 # CONFIG_BLK_CPQ_CISS_DA is not set
 # CONFIG_BLK_DEV_DAC960 is not set
 # CONFIG_BLK_DEV_UMEM is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
 # CONFIG_BLK_DEV_DAC960 is not set
 # CONFIG_BLK_DEV_UMEM is not set

+# CONFIG_BLK_DEV_COW_COMMON is not set

 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_SX8 is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_SX8 is not set
 CONFIG_BLK_DEV_RAM=y

+CONFIG_BLK_DEV_RAM_COUNT=16

 CONFIG_BLK_DEV_RAM_SIZE=4096
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_BLK_DEV_RAM_SIZE=4096
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""


@@ -262,6 +289,7 @@ CONFIG_IOSCHED_NOOP=y
 CONFIG_IOSCHED_AS=y
 CONFIG_IOSCHED_DEADLINE=y
 CONFIG_IOSCHED_CFQ=y
 CONFIG_IOSCHED_AS=y
 CONFIG_IOSCHED_DEADLINE=y
 CONFIG_IOSCHED_CFQ=y

+# CONFIG_ATA_OVER_ETH is not set

 
 #
 # ATA/ATAPI/MFM/RLL support
 
 #
 # ATA/ATAPI/MFM/RLL support


@@ -404,7 +432,6 @@ CONFIG_NET_PCI=y
 # CONFIG_DGRS is not set
 # CONFIG_EEPRO100 is not set
 CONFIG_E100=y
 # CONFIG_DGRS is not set
 # CONFIG_EEPRO100 is not set
 CONFIG_E100=y

-# CONFIG_E100_NAPI is not set

 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set


@@ -429,6 +456,10 @@ CONFIG_E100=y
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set

+CONFIG_MV643XX_ETH=y
+CONFIG_MV643XX_ETH_0=y
+CONFIG_MV643XX_ETH_1=y
+# CONFIG_MV643XX_ETH_2 is not set

 
 #
 # Ethernet (10000 Mbit)
 
 #
 # Ethernet (10000 Mbit)


@@ -484,14 +515,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 

-#
-# Input I/O drivers
-#
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-# CONFIG_SERIO is not set
-# CONFIG_SERIO_I8042 is not set
-

 #
 # Input Device Drivers
 #
 #
 # Input Device Drivers
 #


@@ -501,6 +524,13 @@ CONFIG_SOUND_GAMEPORT=y
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 

+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+

 #
 # Character devices
 #
 #
 # Character devices
 #


@@ -520,6 +550,7 @@ CONFIG_SERIAL_8250_NR_UARTS=2
 #
 # Non-8250 serial port support
 #
 #
 # Non-8250 serial port support
 #

+# CONFIG_SERIAL_MPSC is not set

 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y


@@ -549,6 +580,11 @@ CONFIG_GEN_RTC=y
 # CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
 
 # CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
 

+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+

 #
 # I2C support
 #
 #
 # I2C support
 #


@@ -605,6 +641,16 @@ CONFIG_USB_ARCH_HAS_OHCI=y
 #
 # CONFIG_USB_GADGET is not set
 
 #
 # CONFIG_USB_GADGET is not set
 

+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+

 #
 # File systems
 #
 #
 # File systems
 #


@@ -614,6 +660,10 @@ CONFIG_EXT2_FS=y
 # CONFIG_JBD is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set

+
+#
+# XFS support
+#

 # CONFIG_XFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
 # CONFIG_XFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set


@@ -664,6 +714,7 @@ CONFIG_RAMFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 # CONFIG_JFFS2_FS_NAND is not set
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 # CONFIG_JFFS2_FS_NAND is not set

+# CONFIG_JFFS2_FS_NOR_ECC is not set

 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
 CONFIG_JFFS2_RTIME=y


@@ -686,7 +737,6 @@ CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y

-# CONFIG_EXPORTFS is not set

 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set


@@ -725,6 +775,7 @@ CONFIG_ZLIB_DEFLATE=y
 # Kernel hacking
 #
 # CONFIG_DEBUG_KERNEL is not set
 # Kernel hacking
 #
 # CONFIG_DEBUG_KERNEL is not set

+# CONFIG_PRINTK_TIME is not set

 # CONFIG_SERIAL_TEXT_DEBUG is not set
 
 #
 # CONFIG_SERIAL_TEXT_DEBUG is not set
 
 #


@@ -737,3 +788,7 @@ CONFIG_ZLIB_DEFLATE=y
 # Cryptographic options
 #
 # CONFIG_CRYPTO is not set
 # Cryptographic options
 #
 # CONFIG_CRYPTO is not set

+
+#
+# Hardware crypto devices
+#

diff --git a/arch/ppc/configs/katana_defconfig b/arch/ppc/configs/katana_defconfig
index 0134ae1..f0b0d57 100644 (file)
--- a/arch/ppc/configs/katana_defconfig
+++ b/arch/ppc/configs/katana_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 #
 # Automatically generated make config: don't edit

-# Linux kernel version: 2.6.11-rc2
-# Tue Jan 25 16:31:13 2005
+# Linux kernel version: 2.6.11
+# Tue Mar  8 17:31:00 2005

 #
 CONFIG_MMU=y
 CONFIG_GENERIC_HARDIRQS=y
 #
 CONFIG_MMU=y
 CONFIG_GENERIC_HARDIRQS=y


@@ -36,6 +36,7 @@ CONFIG_KOBJECT_UEVENT=y
 # CONFIG_EMBEDDED is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 # CONFIG_EMBEDDED is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set

+CONFIG_BASE_FULL=y

 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set


@@ -45,6 +46,7 @@ CONFIG_CC_ALIGN_LABELS=0
 CONFIG_CC_ALIGN_LOOPS=0
 CONFIG_CC_ALIGN_JUMPS=0
 # CONFIG_TINY_SHMEM is not set
 CONFIG_CC_ALIGN_LOOPS=0
 CONFIG_CC_ALIGN_JUMPS=0
 # CONFIG_TINY_SHMEM is not set

+CONFIG_BASE_SMALL=0

 
 #
 # Loadable module support
 
 #
 # Loadable module support


@@ -70,6 +72,7 @@ CONFIG_6xx=y
 CONFIG_ALTIVEC=y
 # CONFIG_TAU is not set
 # CONFIG_CPU_FREQ is not set
 CONFIG_ALTIVEC=y
 # CONFIG_TAU is not set
 # CONFIG_CPU_FREQ is not set

+# CONFIG_83xx is not set

 CONFIG_PPC_STD_MMU=y
 CONFIG_NOT_COHERENT_CACHE=y
 
 CONFIG_PPC_STD_MMU=y
 CONFIG_NOT_COHERENT_CACHE=y
 


@@ -93,6 +96,7 @@ CONFIG_KATANA=y
 # CONFIG_PRPMC750 is not set
 # CONFIG_PRPMC800 is not set
 # CONFIG_SANDPOINT is not set
 # CONFIG_PRPMC750 is not set
 # CONFIG_PRPMC800 is not set
 # CONFIG_SANDPOINT is not set

+# CONFIG_RADSTONE_PPC7D is not set

 # CONFIG_ADIR is not set
 # CONFIG_K2 is not set
 # CONFIG_PAL4 is not set
 # CONFIG_ADIR is not set
 # CONFIG_K2 is not set
 # CONFIG_PAL4 is not set


@@ -152,8 +156,8 @@ CONFIG_KERNEL_START=0xc0000000
 CONFIG_TASK_SIZE=0x80000000
 CONFIG_CONSISTENT_START_BOOL=y
 CONFIG_CONSISTENT_START=0xf0000000
 CONFIG_TASK_SIZE=0x80000000
 CONFIG_CONSISTENT_START_BOOL=y
 CONFIG_CONSISTENT_START=0xf0000000

-# CONFIG_CONSISTENT_SIZE_BOOL is not set
-CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_CONSISTENT_SIZE_BOOL=y
+CONFIG_CONSISTENT_SIZE=0x00400000

 # CONFIG_BOOT_LOAD_BOOL is not set
 CONFIG_BOOT_LOAD=0x00800000
 
 # CONFIG_BOOT_LOAD_BOOL is not set
 CONFIG_BOOT_LOAD=0x00800000
 


@@ -171,7 +175,82 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 #
 # Memory Technology Devices (MTD)
 #
 #
 # Memory Technology Devices (MTD)
 #

-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CONCAT=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+# CONFIG_MTD_CFI_I1 is not set
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0xe0000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=4
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+CONFIG_MTD_PHRAM=y
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set

 
 #
 # Parallel port support
 
 #
 # Parallel port support


@@ -353,7 +432,6 @@ CONFIG_NET_PCI=y
 # CONFIG_DGRS is not set
 # CONFIG_EEPRO100 is not set
 CONFIG_E100=y
 # CONFIG_DGRS is not set
 # CONFIG_EEPRO100 is not set
 CONFIG_E100=y

-# CONFIG_E100_NAPI is not set

 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set


@@ -378,6 +456,10 @@ CONFIG_E100=y
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set

+CONFIG_MV643XX_ETH=y
+CONFIG_MV643XX_ETH_0=y
+CONFIG_MV643XX_ETH_1=y
+CONFIG_MV643XX_ETH_2=y

 
 #
 # Ethernet (10000 Mbit)
 
 #
 # Ethernet (10000 Mbit)


@@ -500,7 +582,90 @@ CONFIG_GEN_RTC=y
 #
 # I2C support
 #
 #
 # I2C support
 #

-# CONFIG_I2C is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+CONFIG_I2C_MV64XXX=y
+
+#
+# Hardware Sensors Chip support
+#
+# CONFIG_I2C_SENSOR is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+
+#
+# Other I2C Chip support
+#
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+CONFIG_SENSORS_M41T00=y
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set

 
 #
 # Dallas's 1-wire bus
 
 #
 # Dallas's 1-wire bus


@@ -531,7 +696,6 @@ CONFIG_GEN_RTC=y
 #
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
 #
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y

-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set

 
 #
 # Sound
 
 #
 # Sound


@@ -573,6 +737,10 @@ CONFIG_EXT2_FS=y
 # CONFIG_JBD is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set

+
+#
+# XFS support
+#

 # CONFIG_XFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
 # CONFIG_XFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set


@@ -619,6 +787,8 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set

+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set

 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_HPFS_FS is not set


@@ -637,7 +807,6 @@ CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y

-# CONFIG_EXPORTFS is not set

 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set


@@ -674,6 +843,7 @@ CONFIG_CRC32=y
 # Kernel hacking
 #
 # CONFIG_DEBUG_KERNEL is not set
 # Kernel hacking
 #
 # CONFIG_DEBUG_KERNEL is not set

+# CONFIG_PRINTK_TIME is not set

 
 #
 # Security options
 
 #
 # Security options

diff --git a/arch/ppc/configs/mpc8555_cds_defconfig b/arch/ppc/configs/mpc8555_cds_defconfig
index 728bd9e..15abebf 100644 (file)
--- a/arch/ppc/configs/mpc8555_cds_defconfig
+++ b/arch/ppc/configs/mpc8555_cds_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 #
 # Automatically generated make config: don't edit

-# Linux kernel version: 2.6.11-rc1
-# Thu Jan 20 01:25:35 2005
+# Linux kernel version: 2.6.12-rc4
+# Tue May 17 11:56:01 2005

 #
 CONFIG_MMU=y
 CONFIG_GENERIC_HARDIRQS=y
 #
 CONFIG_MMU=y
 CONFIG_GENERIC_HARDIRQS=y


@@ -11,6 +11,7 @@ CONFIG_HAVE_DEC_LOCK=y
 CONFIG_PPC=y
 CONFIG_PPC32=y
 CONFIG_GENERIC_NVRAM=y
 CONFIG_PPC=y
 CONFIG_PPC32=y
 CONFIG_GENERIC_NVRAM=y

+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y

 
 #
 # Code maturity level options
 
 #
 # Code maturity level options


@@ -18,6 +19,7 @@ CONFIG_GENERIC_NVRAM=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y

+CONFIG_INIT_ENV_ARG_LIMIT=32

 
 #
 # General setup
 
 #
 # General setup


@@ -29,12 +31,14 @@ CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
 # CONFIG_AUDIT is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
 # CONFIG_AUDIT is not set

-CONFIG_LOG_BUF_SHIFT=14

 # CONFIG_HOTPLUG is not set
 CONFIG_KOBJECT_UEVENT=y
 # CONFIG_IKCONFIG is not set
 CONFIG_EMBEDDED=y
 # CONFIG_KALLSYMS is not set
 # CONFIG_HOTPLUG is not set
 CONFIG_KOBJECT_UEVENT=y
 # CONFIG_IKCONFIG is not set
 CONFIG_EMBEDDED=y
 # CONFIG_KALLSYMS is not set

+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_BASE_FULL=y

 CONFIG_FUTEX=y
 # CONFIG_EPOLL is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_FUTEX=y
 # CONFIG_EPOLL is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set


@@ -44,6 +48,7 @@ CONFIG_CC_ALIGN_LABELS=0
 CONFIG_CC_ALIGN_LOOPS=0
 CONFIG_CC_ALIGN_JUMPS=0
 # CONFIG_TINY_SHMEM is not set
 CONFIG_CC_ALIGN_LOOPS=0
 CONFIG_CC_ALIGN_JUMPS=0
 # CONFIG_TINY_SHMEM is not set

+CONFIG_BASE_SMALL=0

 
 #
 # Loadable module support
 
 #
 # Loadable module support


@@ -62,10 +67,12 @@ CONFIG_CC_ALIGN_JUMPS=0
 CONFIG_E500=y
 CONFIG_BOOKE=y
 CONFIG_FSL_BOOKE=y
 CONFIG_E500=y
 CONFIG_BOOKE=y
 CONFIG_FSL_BOOKE=y

+# CONFIG_PHYS_64BIT is not set

 CONFIG_SPE=y
 CONFIG_MATH_EMULATION=y
 # CONFIG_CPU_FREQ is not set
 CONFIG_PPC_GEN550=y
 CONFIG_SPE=y
 CONFIG_MATH_EMULATION=y
 # CONFIG_CPU_FREQ is not set
 CONFIG_PPC_GEN550=y

+# CONFIG_PM is not set

 CONFIG_85xx=y
 CONFIG_PPC_INDIRECT_PCI_BE=y
 
 CONFIG_85xx=y
 CONFIG_PPC_INDIRECT_PCI_BE=y
 


@@ -76,6 +83,7 @@ CONFIG_PPC_INDIRECT_PCI_BE=y
 CONFIG_MPC8555_CDS=y
 # CONFIG_MPC8560_ADS is not set
 # CONFIG_SBC8560 is not set
 CONFIG_MPC8555_CDS=y
 # CONFIG_MPC8560_ADS is not set
 # CONFIG_SBC8560 is not set

+# CONFIG_STX_GP3 is not set

 CONFIG_MPC8555=y
 CONFIG_85xx_PCI2=y
 
 CONFIG_MPC8555=y
 CONFIG_85xx_PCI2=y
 


@@ -90,6 +98,7 @@ CONFIG_CPM2=y
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
 # CONFIG_CMDLINE_BOOL is not set
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
 # CONFIG_CMDLINE_BOOL is not set

+CONFIG_ISA_DMA_API=y

 
 #
 # Bus options
 
 #
 # Bus options


@@ -104,10 +113,6 @@ CONFIG_PCI_NAMES=y
 #
 # CONFIG_PCCARD is not set
 
 #
 # CONFIG_PCCARD is not set
 

-#
-# PC-card bridges
-#
-

 #
 # Advanced setup
 #
 #
 # Advanced setup
 #


@@ -180,7 +185,59 @@ CONFIG_IOSCHED_CFQ=y
 #
 # ATA/ATAPI/MFM/RLL support
 #
 #
 # ATA/ATAPI/MFM/RLL support
 #

-# CONFIG_IDE is not set
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+CONFIG_BLK_DEV_IDEPCI=y
+CONFIG_IDEPCI_SHARE_IRQ=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_GENERIC=y
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_SL82C105 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+CONFIG_IDEDMA_PCI_AUTO=y
+# CONFIG_IDEDMA_ONLYDISK is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+CONFIG_BLK_DEV_VIA82CXXX=y
+# CONFIG_IDE_ARM is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_IVB is not set
+CONFIG_IDEDMA_AUTO=y
+# CONFIG_BLK_DEV_HD is not set

 
 #
 # SCSI device support
 
 #
 # SCSI device support


@@ -220,7 +277,6 @@ CONFIG_NET=y
 #
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 #
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set

-# CONFIG_NETLINK_DEV is not set

 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y


@@ -369,14 +425,6 @@ CONFIG_INPUT=y
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 

-#
-# Input I/O drivers
-#
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-# CONFIG_SERIO is not set
-# CONFIG_SERIO_I8042 is not set
-

 #
 # Input Device Drivers
 #
 #
 # Input Device Drivers
 #


@@ -386,6 +434,13 @@ CONFIG_SOUND_GAMEPORT=y
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 

+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+

 #
 # Character devices
 #
 #
 # Character devices
 #


@@ -406,6 +461,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_CPM is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_CPM is not set

+# CONFIG_SERIAL_JSM is not set

 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256


@@ -433,6 +489,11 @@ CONFIG_GEN_RTC=y
 # CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
 
 # CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
 

+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+

 #
 # I2C support
 #
 #
 # I2C support
 #


@@ -456,11 +517,11 @@ CONFIG_I2C_CHARDEV=y
 # CONFIG_I2C_AMD8111 is not set
 # CONFIG_I2C_I801 is not set
 # CONFIG_I2C_I810 is not set
 # CONFIG_I2C_AMD8111 is not set
 # CONFIG_I2C_I801 is not set
 # CONFIG_I2C_I810 is not set

+# CONFIG_I2C_PIIX4 is not set

 # CONFIG_I2C_ISA is not set
 CONFIG_I2C_MPC=y
 # CONFIG_I2C_NFORCE2 is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_ISA is not set
 CONFIG_I2C_MPC=y
 # CONFIG_I2C_NFORCE2 is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set

-# CONFIG_I2C_PIIX4 is not set

 # CONFIG_I2C_PROSAVAGE is not set
 # CONFIG_I2C_SAVAGE4 is not set
 # CONFIG_SCx200_ACB is not set
 # CONFIG_I2C_PROSAVAGE is not set
 # CONFIG_I2C_SAVAGE4 is not set
 # CONFIG_SCx200_ACB is not set


@@ -483,7 +544,9 @@ CONFIG_I2C_MPC=y
 # CONFIG_SENSORS_ASB100 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_FSCHER is not set
 # CONFIG_SENSORS_ASB100 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_FSCHER is not set

+# CONFIG_SENSORS_FSCPOS is not set

 # CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_GL518SM is not set

+# CONFIG_SENSORS_GL520SM is not set

 # CONFIG_SENSORS_IT87 is not set
 # CONFIG_SENSORS_LM63 is not set
 # CONFIG_SENSORS_LM75 is not set
 # CONFIG_SENSORS_IT87 is not set
 # CONFIG_SENSORS_LM63 is not set
 # CONFIG_SENSORS_LM75 is not set


@@ -494,9 +557,11 @@ CONFIG_I2C_MPC=y
 # CONFIG_SENSORS_LM85 is not set
 # CONFIG_SENSORS_LM87 is not set
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM85 is not set
 # CONFIG_SENSORS_LM87 is not set
 # CONFIG_SENSORS_LM90 is not set

+# CONFIG_SENSORS_LM92 is not set

 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set

+# CONFIG_SENSORS_SIS5595 is not set

 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_W83781D is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_W83781D is not set


@@ -506,10 +571,12 @@ CONFIG_I2C_MPC=y
 #
 # Other I2C Chip support
 #
 #
 # Other I2C Chip support
 #

+# CONFIG_SENSORS_DS1337 is not set

 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_RTC8564 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_RTC8564 is not set

+# CONFIG_SENSORS_M41T00 is not set

 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set


@@ -538,7 +605,6 @@ CONFIG_I2C_MPC=y
 # Graphics support
 #
 # CONFIG_FB is not set
 # Graphics support
 #
 # CONFIG_FB is not set

-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set

 
 #
 # Sound
 
 #
 # Sound


@@ -548,13 +614,9 @@ CONFIG_I2C_MPC=y
 #
 # USB support
 #
 #
 # USB support
 #

-# CONFIG_USB is not set

 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y

-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
-#
+# CONFIG_USB is not set

 
 #
 # USB Gadget Support
 
 #
 # USB Gadget Support


@@ -585,6 +647,10 @@ CONFIG_JBD=y
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set

+
+#
+# XFS support
+#

 # CONFIG_XFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
 # CONFIG_XFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set


@@ -646,7 +712,6 @@ CONFIG_NFS_FS=y
 # CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 # CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y

-# CONFIG_EXPORTFS is not set

 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set


@@ -698,7 +763,9 @@ CONFIG_CRC32=y
 #
 # Kernel hacking
 #
 #
 # Kernel hacking
 #

+# CONFIG_PRINTK_TIME is not set

 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_DEBUG_KERNEL is not set

+CONFIG_LOG_BUF_SHIFT=14

 # CONFIG_KGDB_CONSOLE is not set
 # CONFIG_SERIAL_TEXT_DEBUG is not set
 
 # CONFIG_KGDB_CONSOLE is not set
 # CONFIG_SERIAL_TEXT_DEBUG is not set
 

diff --git a/arch/ppc/platforms/85xx/Makefile b/arch/ppc/platforms/85xx/Makefile
index b5161e3..854fbd2 100644 (file)
--- a/arch/ppc/platforms/85xx/Makefile
+++ b/arch/ppc/platforms/85xx/Makefile
@@ -1,8 +1,6 @@
 #
 # Makefile for the PowerPC 85xx linux kernel.
 #
 #
 # Makefile for the PowerPC 85xx linux kernel.
 #

-obj-$(CONFIG_85xx)             += mpc85xx_sys.o mpc85xx_devices.o
-

 obj-$(CONFIG_MPC8540_ADS)      += mpc85xx_ads_common.o mpc8540_ads.o
 obj-$(CONFIG_MPC8555_CDS)      += mpc85xx_cds_common.o
 obj-$(CONFIG_MPC8560_ADS)      += mpc85xx_ads_common.o mpc8560_ads.o
 obj-$(CONFIG_MPC8540_ADS)      += mpc85xx_ads_common.o mpc8540_ads.o
 obj-$(CONFIG_MPC8555_CDS)      += mpc85xx_cds_common.o
 obj-$(CONFIG_MPC8560_ADS)      += mpc85xx_ads_common.o mpc8560_ads.o

diff --git a/arch/sh64/kernel/Makefile b/arch/sh64/kernel/Makefile
index 2f8d077..5816657 100644 (file)
--- a/arch/sh64/kernel/Makefile
+++ b/arch/sh64/kernel/Makefile
@@ -13,7 +13,7 @@
 # unless it's something special (ie not a .c file).
 #
 
 # unless it's something special (ie not a .c file).
 #
 

-extra-y        := head.o init_task.o vmlinux.lds.s
+extra-y        := head.o init_task.o vmlinux.lds

 
 obj-y  := process.o signal.o entry.o traps.o irq.o irq_intc.o \
           ptrace.o setup.o time.o sys_sh64.o semaphore.o sh_ksyms.o \
 
 obj-y  := process.o signal.o entry.o traps.o irq.o irq_intc.o \
           ptrace.o setup.o time.o sys_sh64.o semaphore.o sh_ksyms.o \


@@ -22,17 +22,15 @@ obj-y       := process.o signal.o entry.o traps.o irq.o irq_intc.o \
 obj-$(CONFIG_HEARTBEAT)                += led.o
 obj-$(CONFIG_SH_ALPHANUMERIC)  += alphanum.o
 obj-$(CONFIG_SH_DMA)           += dma.o
 obj-$(CONFIG_HEARTBEAT)                += led.o
 obj-$(CONFIG_SH_ALPHANUMERIC)  += alphanum.o
 obj-$(CONFIG_SH_DMA)           += dma.o

+obj-$(CONFIG_SH_FPU)           += fpu.o

 obj-$(CONFIG_EARLY_PRINTK)     += early_printk.o
 obj-$(CONFIG_KALLSYMS)         += unwind.o
 obj-$(CONFIG_PCI)              += pci-dma.o pcibios.o
 obj-$(CONFIG_EARLY_PRINTK)     += early_printk.o
 obj-$(CONFIG_KALLSYMS)         += unwind.o
 obj-$(CONFIG_PCI)              += pci-dma.o pcibios.o

+obj-$(CONFIG_MODULES)          += module.o

 
 ifeq ($(CONFIG_PCI),y)
 obj-$(CONFIG_CPU_SH5)          += pci_sh5.o
 endif
 
 
 ifeq ($(CONFIG_PCI),y)
 obj-$(CONFIG_CPU_SH5)          += pci_sh5.o
 endif
 

-ifndef CONFIG_NOFPU_SUPPORT
-obj-y                          += fpu.o
-endif
-

 USE_STANDARD_AS_RULE := true
 
 USE_STANDARD_AS_RULE := true
 

diff --git a/arch/sh64/kernel/early_printk.c b/arch/sh64/kernel/early_printk.c
index 3d03ca7..8c8a76e 100644 (file)
--- a/arch/sh64/kernel/early_printk.c
+++ b/arch/sh64/kernel/early_printk.c
@@ -16,8 +16,6 @@
 #include <asm/io.h>
 #include <asm/hardware.h>
 
 #include <asm/io.h>
 #include <asm/hardware.h>
 

-extern void cpu_relax(void);
-

 #define SCIF_BASE_ADDR 0x01030000
 #define SCIF_ADDR_SH5  PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
 
 #define SCIF_BASE_ADDR 0x01030000
 #define SCIF_ADDR_SH5  PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
 

diff --git a/arch/sh64/kernel/switchto.S b/arch/sh64/kernel/switchto.S
index 24ef14c..45b2d90 100644 (file)
--- a/arch/sh64/kernel/switchto.S
+++ b/arch/sh64/kernel/switchto.S
@@ -27,7 +27,7 @@ sh64_switch_to:
    r5 - &next->thread
 
    Outgoing results
    r5 - &next->thread
 
    Outgoing results

-   r2 - last (=prev)
+   r2 - last (=prev) : this just stays in r2 throughout

 
    Want to create a full (struct pt_regs) on the stack to allow backtracing
    functions to work.  However, we only need to populate the callee-save
 
    Want to create a full (struct pt_regs) on the stack to allow backtracing
    functions to work.  However, we only need to populate the callee-save


@@ -188,7 +188,6 @@ sh64_switch_to:
        ! epilogue
        ld.l    r15, 0, r18
        ld.l    r15, 4, r14
        ! epilogue
        ld.l    r15, 0, r18
        ld.l    r15, 4, r14

-       ori     r4, 0, r2       ! last = prev

        ptabs   r18, tr0
        movi    FRAME_SIZE, r0
        add     r15, r0, r15
        ptabs   r18, tr0
        movi    FRAME_SIZE, r0
        add     r15, r0, r15

diff --git a/arch/sh64/kernel/syscalls.S b/arch/sh64/kernel/syscalls.S
index 819e335..6aabc63 100644 (file)
--- a/arch/sh64/kernel/syscalls.S
+++ b/arch/sh64/kernel/syscalls.S
@@ -268,7 +268,7 @@ sys_call_table:
        .long sys_msgrcv
        .long sys_msgget
        .long sys_msgctl
        .long sys_msgrcv
        .long sys_msgget
        .long sys_msgctl

-       .long sys_ni_syscall /* sys_shmatcall */
+       .long sys_shmat

        .long sys_shmdt                 /* 245 */
        .long sys_shmget
        .long sys_shmctl
        .long sys_shmdt                 /* 245 */
        .long sys_shmget
        .long sys_shmctl


@@ -337,4 +337,9 @@ sys_call_table:
        .long sys_mq_timedreceive
        .long sys_mq_notify
        .long sys_mq_getsetattr         /* 310 */
        .long sys_mq_timedreceive
        .long sys_mq_notify
        .long sys_mq_getsetattr         /* 310 */

+       .long sys_ni_syscall    /* Reserved for kexec */
+       .long sys_waitid
+       .long sys_add_key
+       .long sys_request_key
+       .long sys_keyctl                /* 315 */

 
 

diff --git a/arch/sh64/kernel/traps.c b/arch/sh64/kernel/traps.c
index b2b2bde..224b7f5 100644 (file)
--- a/arch/sh64/kernel/traps.c
+++ b/arch/sh64/kernel/traps.c
@@ -30,6 +30,7 @@
 #include <linux/kallsyms.h>
 #include <linux/interrupt.h>
 #include <linux/sysctl.h>
 #include <linux/kallsyms.h>
 #include <linux/interrupt.h>
 #include <linux/sysctl.h>

+#include <linux/module.h>

 
 #include <asm/system.h>
 #include <asm/uaccess.h>
 
 #include <asm/system.h>
 #include <asm/uaccess.h>


@@ -286,6 +287,8 @@ void dump_stack(void)
 {
        show_task(NULL);
 }
 {
        show_task(NULL);
 }

+/* Needed by any user of WARN_ON in view of the defn in include/asm-sh/bug.h */
+EXPORT_SYMBOL(dump_stack);

 
 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
                unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk)
 
 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
                unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk)

diff --git a/arch/sh64/lib/Makefile b/arch/sh64/lib/Makefile
index 0a2dc69..6a4cc3f 100644 (file)
--- a/arch/sh64/lib/Makefile
+++ b/arch/sh64/lib/Makefile
@@ -15,5 +15,5 @@
 
 # Panic should really be compiled as PIC
 lib-y  := udelay.o c-checksum.o dbg.o io.o panic.o memcpy.o copy_user_memcpy.o \
 
 # Panic should really be compiled as PIC
 lib-y  := udelay.o c-checksum.o dbg.o io.o panic.o memcpy.o copy_user_memcpy.o \

-               page_copy.o page_clear.o
+               page_copy.o page_clear.o iomap.o

 
 

diff --git a/arch/sh64/lib/copy_user_memcpy.S b/arch/sh64/lib/copy_user_memcpy.S
index 5b6ca39..2a62816 100644 (file)
--- a/arch/sh64/lib/copy_user_memcpy.S
+++ b/arch/sh64/lib/copy_user_memcpy.S
@@ -46,6 +46,11 @@
 
 */
 
 
 */
 

+/* NOTE : Prefetches removed and allocos guarded by synco to avoid TAKum03020
+ * erratum.  The first two prefetches are nop-ed out to avoid upsetting the
+ * instruction counts used in the jump address calculation.
+ * */
+

        .section .text..SHmedia32,"ax"
        .little
        .balign 32
        .section .text..SHmedia32,"ax"
        .little
        .balign 32


@@ -58,7 +63,7 @@ copy_user_memcpy:
 #define LDUAL(P,O,D0,D1) ldlo.l P,O,D0; ldhi.l P,O+3,D1
 #define STUAL(P,O,D0,D1) stlo.l P,O,D0; sthi.l P,O+3,D1
 
 #define LDUAL(P,O,D0,D1) ldlo.l P,O,D0; ldhi.l P,O+3,D1
 #define STUAL(P,O,D0,D1) stlo.l P,O,D0; sthi.l P,O+3,D1
 

-       ld.b r3,0,r63
+       nop ! ld.b r3,0,r63 ! TAKum03020

        pta/l Large,tr0
        movi 25,r0
        bgeu/u r4,r0,tr0
        pta/l Large,tr0
        movi 25,r0
        bgeu/u r4,r0,tr0


@@ -108,7 +113,7 @@ L8_15:      /* 8..15 byte memcpy cntd. */
 
        /* 2 or 3 byte memcpy */
        ld.b r3,0,r0
 
        /* 2 or 3 byte memcpy */
        ld.b r3,0,r0

-       ld.b r2,0,r63
+       nop ! ld.b r2,0,r63 ! TAKum03020

        ld.b r3,1,r1
        st.b r2,0,r0
        pta/l L2_3,tr0
        ld.b r3,1,r1
        st.b r2,0,r0
        pta/l L2_3,tr0


@@ -151,7 +156,7 @@ L8_15:      /* 8..15 byte memcpy cntd. */
        blink tr1,r63
 
 Large:
        blink tr1,r63
 
 Large:

-       ld.b r2, 0, r63
+       ! ld.b r2, 0, r63 ! TAKum03020

        pta/l  Loop_ua, tr1
        ori r3, -8, r7
        sub r2, r7, r22
        pta/l  Loop_ua, tr1
        ori r3, -8, r7
        sub r2, r7, r22


@@ -173,8 +178,7 @@ Large:
        addi r6, -8, r21
 
 Loop_line:
        addi r6, -8, r21
 
 Loop_line:

-       ldx.q r22, r36, r63
-       synco
+       ! ldx.q r22, r36, r63 ! TAKum03020

        alloco r22, 32
        synco
        addi r22, 32, r22
        alloco r22, 32
        synco
        addi r22, 32, r22

diff --git a/arch/sh64/lib/page_clear.S b/arch/sh64/lib/page_clear.S
index 2aadd2c..ac0111d 100644 (file)
--- a/arch/sh64/lib/page_clear.S
+++ b/arch/sh64/lib/page_clear.S
@@ -17,6 +17,8 @@
 
    Always clears 4096 bytes.
 
 
    Always clears 4096 bytes.
 

+   Note : alloco guarded by synco to avoid TAKum03020 erratum
+

 */
 
        .section .text..SHmedia32,"ax"
 */
 
        .section .text..SHmedia32,"ax"


@@ -34,6 +36,7 @@ sh64_page_clear:
        add  r2, r63, r6
 1:
        alloco r6, 0
        add  r2, r63, r6
 1:
        alloco r6, 0

+       synco   ! TAKum03020

        addi    r6, 32, r6
        bgt/l   r7, r6, tr1
 
        addi    r6, 32, r6
        bgt/l   r7, r6, tr1
 

diff --git a/arch/sh64/lib/page_copy.S b/arch/sh64/lib/page_copy.S
index 804d2a0..e159c3c 100644 (file)
--- a/arch/sh64/lib/page_copy.S
+++ b/arch/sh64/lib/page_copy.S
@@ -39,12 +39,17 @@ sh64_page_copy:
        pta 3f, tr3
        ptabs r18, tr0
 
        pta 3f, tr3
        ptabs r18, tr0
 

+#if 0
+       /* TAKum03020 */

        ld.q r2, 0x00, r63
        ld.q r2, 0x20, r63
        ld.q r2, 0x40, r63
        ld.q r2, 0x60, r63
        ld.q r2, 0x00, r63
        ld.q r2, 0x20, r63
        ld.q r2, 0x40, r63
        ld.q r2, 0x60, r63

+#endif

        alloco r3, 0x00
        alloco r3, 0x00

+       synco           ! TAKum03020

        alloco r3, 0x20
        alloco r3, 0x20

+       synco           ! TAKum03020

 
        movi 3968, r6
        add  r3, r6, r6
 
        movi 3968, r6
        add  r3, r6, r6


@@ -60,11 +65,15 @@ sh64_page_copy:
    because they overlap with the time spent waiting for prefetches to
    complete. */
 1:
    because they overlap with the time spent waiting for prefetches to
    complete. */
 1:

+#if 0
+       /* TAKum03020 */

        bge/u r3, r6, tr2  ! skip prefetch for last 4 lines
        ldx.q r3, r22, r63 ! prefetch 4 lines hence
        bge/u r3, r6, tr2  ! skip prefetch for last 4 lines
        ldx.q r3, r22, r63 ! prefetch 4 lines hence

+#endif

 2:
        bge/u r3, r7, tr3  ! skip alloco for last 2 lines
        alloco r3, 0x40    ! alloc destination line 2 lines ahead
 2:
        bge/u r3, r7, tr3  ! skip alloco for last 2 lines
        alloco r3, 0x40    ! alloc destination line 2 lines ahead

+       synco           ! TAKum03020

 3:
        ldx.q r3, r60, r36
        ldx.q r3, r61, r37
 3:
        ldx.q r3, r60, r36
        ldx.q r3, r61, r37

diff --git a/arch/sh64/mach-cayman/Makefile b/arch/sh64/mach-cayman/Makefile
index 4a48b53..67a2258 100644 (file)
--- a/arch/sh64/mach-cayman/Makefile
+++ b/arch/sh64/mach-cayman/Makefile
@@ -6,6 +6,6 @@
 # unless it's something special (ie not a .c file).
 #
 
 # unless it's something special (ie not a .c file).
 #
 

-obj-y := setup.o irq.o
+obj-y := setup.o irq.o iomap.o

 obj-$(CONFIG_HEARTBEAT)        += led.o
 
 obj-$(CONFIG_HEARTBEAT)        += led.o
 

diff --git a/arch/sh64/mm/tlbmiss.c b/arch/sh64/mm/tlbmiss.c
index 69f686c..c861595 100644 (file)
--- a/arch/sh64/mm/tlbmiss.c
+++ b/arch/sh64/mm/tlbmiss.c
@@ -75,7 +75,6 @@ inline void __do_tlb_refill(unsigned long address,
 
        /* Set PTEL register, set_pte has performed the sign extension */
        ptel &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
 
        /* Set PTEL register, set_pte has performed the sign extension */
        ptel &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */

-       ptel |= _PAGE_FLAGS_HARDWARE_DEFAULT; /* add default flags */

 
        tlbp = is_text_not_data ? &(cpu_data->itlb) : &(cpu_data->dtlb);
        next = tlbp->next;
 
        tlbp = is_text_not_data ? &(cpu_data->itlb) : &(cpu_data->dtlb);
        next = tlbp->next;

diff --git a/arch/um/include/sysdep-x86_64/sigcontext.h b/arch/um/include/sysdep-x86_64/sigcontext.h
index 6a0c346..2a78260 100644 (file)
--- a/arch/um/include/sysdep-x86_64/sigcontext.h
+++ b/arch/um/include/sysdep-x86_64/sigcontext.h
@@ -7,7 +7,7 @@
 #ifndef __SYSDEP_X86_64_SIGCONTEXT_H
 #define __SYSDEP_X86_64_SIGCONTEXT_H
 
 #ifndef __SYSDEP_X86_64_SIGCONTEXT_H
 #define __SYSDEP_X86_64_SIGCONTEXT_H
 

-#include "sc.h"
+#include <sysdep/sc.h>

 
 #define IP_RESTART_SYSCALL(ip) ((ip) -= 2)
 
 
 #define IP_RESTART_SYSCALL(ip) ((ip) -= 2)
 


@@ -17,11 +17,12 @@
 #define SC_FAULT_ADDR(sc) SC_CR2(sc)
 #define SC_FAULT_TYPE(sc) SC_ERR(sc)
 
 #define SC_FAULT_ADDR(sc) SC_CR2(sc)
 #define SC_FAULT_TYPE(sc) SC_ERR(sc)
 

-#define FAULT_WRITE(err) ((err) & 2)
-
-#define SC_FAULT_WRITE(sc) FAULT_WRITE(SC_FAULT_TYPE(sc))
-
-#define SC_TRAP_TYPE(sc) SC_TRAPNO(sc)
+#define GET_FAULTINFO_FROM_SC(fi,sc) \
+       { \
+               (fi).cr2 = SC_CR2(sc); \
+               (fi).error_code = SC_ERR(sc); \
+               (fi).trap_no = SC_TRAPNO(sc); \
+       }

 
 /* ptrace expects that, at the start of a system call, %eax contains
  * -ENOSYS, so this makes it so.
 
 /* ptrace expects that, at the start of a system call, %eax contains
  * -ENOSYS, so this makes it so.


@@ -29,8 +30,8 @@
 
 #define SC_START_SYSCALL(sc) do SC_RAX(sc) = -ENOSYS; while(0)
 
 
 #define SC_START_SYSCALL(sc) do SC_RAX(sc) = -ENOSYS; while(0)
 

-#define SEGV_IS_FIXABLE(trap) ((trap) == 14)
-#define SC_SEGV_IS_FIXABLE(sc) SEGV_IS_FIXABLE(SC_TRAP_TYPE(sc))
+/* This is Page Fault */
+#define SEGV_IS_FIXABLE(fi) ((fi)->trap_no == 14)

 
 extern unsigned long *sc_sigmask(void *sc_ptr);
 
 
 extern unsigned long *sc_sigmask(void *sc_ptr);
 

diff --git a/arch/um/sys-x86_64/ptrace_user.c b/arch/um/sys-x86_64/ptrace_user.c
index e1f8bac..12e404c 100644 (file)
--- a/arch/um/sys-x86_64/ptrace_user.c
+++ b/arch/um/sys-x86_64/ptrace_user.c
@@ -6,9 +6,7 @@
 
 #include <stddef.h>
 #include <errno.h>
 
 #include <stddef.h>
 #include <errno.h>

-#define __FRAME_OFFSETS
-#include <sys/ptrace.h>
-#include <asm/ptrace.h>
+#include "ptrace_user.h"

 #include "user.h"
 #include "kern_constants.h"
 
 #include "user.h"
 #include "kern_constants.h"
 


@@ -42,23 +40,12 @@ void arch_enter_kernel(void *task, int pid)
 void arch_leave_kernel(void *task, int pid)
 {
 #ifdef UM_USER_CS
 void arch_leave_kernel(void *task, int pid)
 {
 #ifdef UM_USER_CS

-       if(ptrace(PTRACE_POKEUSER, pid, CS, UM_USER_CS) < 0)
-               tracer_panic("POKEUSER CS failed");
+        if(ptrace(PTRACE_POKEUSR, pid, CS, UM_USER_CS) < 0)
+                printk("POKEUSR CS failed");

 #endif
 
 #endif
 

-       if(ptrace(PTRACE_POKEUSER, pid, DS, __USER_DS) < 0)
-               tracer_panic("POKEUSER DS failed");
-       if(ptrace(PTRACE_POKEUSER, pid, ES, __USER_DS) < 0)
-               tracer_panic("POKEUSER ES failed");
+        if(ptrace(PTRACE_POKEUSR, pid, DS, __USER_DS) < 0)
+                printk("POKEUSR DS failed");
+        if(ptrace(PTRACE_POKEUSR, pid, ES, __USER_DS) < 0)
+                printk("POKEUSR ES failed");

 }
 }

-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */

diff --git a/drivers/base/transport_class.c b/drivers/base/transport_class.c
index 3bae11c..6c2b447 100644 (file)
--- a/drivers/base/transport_class.c
+++ b/drivers/base/transport_class.c
@@ -145,6 +145,20 @@ void transport_setup_device(struct device *dev)
 }
 EXPORT_SYMBOL_GPL(transport_setup_device);
 
 }
 EXPORT_SYMBOL_GPL(transport_setup_device);
 

+static int transport_add_class_device(struct attribute_container *cont,
+                                     struct device *dev,
+                                     struct class_device *classdev)
+{
+       int error = attribute_container_add_class_device(classdev);
+       struct transport_container *tcont = 
+               attribute_container_to_transport_container(cont);
+
+       if (!error && tcont->statistics)
+               error = sysfs_create_group(&classdev->kobj, tcont->statistics);
+
+       return error;
+}
+

 
 /**
  * transport_add_device - declare a new dev for transport class association
 
 /**
  * transport_add_device - declare a new dev for transport class association


@@ -159,8 +173,7 @@ EXPORT_SYMBOL_GPL(transport_setup_device);
 
 void transport_add_device(struct device *dev)
 {
 
 void transport_add_device(struct device *dev)
 {

-       attribute_container_device_trigger(dev,
-                          attribute_container_add_class_device_adapter);
+       attribute_container_device_trigger(dev, transport_add_class_device);

 }
 EXPORT_SYMBOL_GPL(transport_add_device);
 
 }
 EXPORT_SYMBOL_GPL(transport_add_device);
 


@@ -197,13 +210,18 @@ static int transport_remove_classdev(struct attribute_container *cont,
                                     struct device *dev,
                                     struct class_device *classdev)
 {
                                     struct device *dev,
                                     struct class_device *classdev)
 {

+       struct transport_container *tcont = 
+               attribute_container_to_transport_container(cont);

        struct transport_class *tclass = class_to_transport_class(cont->class);
 
        if (tclass->remove)
                tclass->remove(dev);
 
        struct transport_class *tclass = class_to_transport_class(cont->class);
 
        if (tclass->remove)
                tclass->remove(dev);
 

-       if (tclass->remove != anon_transport_dummy_function)
+       if (tclass->remove != anon_transport_dummy_function) {
+               if (tcont->statistics)
+                       sysfs_remove_group(&classdev->kobj, tcont->statistics);

                attribute_container_class_device_del(classdev);
                attribute_container_class_device_del(classdev);

+       }

 
        return 0;
 }
 
        return 0;
 }

diff --git a/drivers/char/drm/drm_context.c b/drivers/char/drm/drm_context.c
index 3a7637c..f15c86c 100644 (file)
--- a/drivers/char/drm/drm_context.c
+++ b/drivers/char/drm/drm_context.c
@@ -208,7 +208,7 @@ int drm_getsareactx(struct inode *inode, struct file *filp,
                     unsigned int cmd, unsigned long arg)
 {
        drm_file_t      *priv   = filp->private_data;
                     unsigned int cmd, unsigned long arg)
 {
        drm_file_t      *priv   = filp->private_data;

-       drm_device_t    *dev    = priv->dev;
+       drm_device_t    *dev    = priv->head->dev;

        drm_ctx_priv_map_t __user *argp = (void __user *)arg;
        drm_ctx_priv_map_t request;
        drm_map_t *map;
        drm_ctx_priv_map_t __user *argp = (void __user *)arg;
        drm_ctx_priv_map_t request;
        drm_map_t *map;


@@ -247,7 +247,7 @@ int drm_setsareactx(struct inode *inode, struct file *filp,
                     unsigned int cmd, unsigned long arg)
 {
        drm_file_t      *priv   = filp->private_data;
                     unsigned int cmd, unsigned long arg)
 {
        drm_file_t      *priv   = filp->private_data;

-       drm_device_t    *dev    = priv->dev;
+       drm_device_t    *dev    = priv->head->dev;

        drm_ctx_priv_map_t request;
        drm_map_t *map = NULL;
        drm_map_list_t *r_list = NULL;
        drm_ctx_priv_map_t request;
        drm_map_t *map = NULL;
        drm_map_list_t *r_list = NULL;


@@ -395,7 +395,7 @@ int drm_addctx( struct inode *inode, struct file *filp,
                 unsigned int cmd, unsigned long arg )
 {
        drm_file_t *priv = filp->private_data;
                 unsigned int cmd, unsigned long arg )
 {
        drm_file_t *priv = filp->private_data;

-       drm_device_t *dev = priv->dev;
+       drm_device_t *dev = priv->head->dev;

        drm_ctx_list_t * ctx_entry;
        drm_ctx_t __user *argp = (void __user *)arg;
        drm_ctx_t ctx;
        drm_ctx_list_t * ctx_entry;
        drm_ctx_t __user *argp = (void __user *)arg;
        drm_ctx_t ctx;


@@ -489,7 +489,7 @@ int drm_switchctx( struct inode *inode, struct file *filp,
                    unsigned int cmd, unsigned long arg )
 {
        drm_file_t *priv = filp->private_data;
                    unsigned int cmd, unsigned long arg )
 {
        drm_file_t *priv = filp->private_data;

-       drm_device_t *dev = priv->dev;
+       drm_device_t *dev = priv->head->dev;

        drm_ctx_t ctx;
 
        if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) )
        drm_ctx_t ctx;
 
        if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) )


@@ -514,7 +514,7 @@ int drm_newctx( struct inode *inode, struct file *filp,
                 unsigned int cmd, unsigned long arg )
 {
        drm_file_t *priv = filp->private_data;
                 unsigned int cmd, unsigned long arg )
 {
        drm_file_t *priv = filp->private_data;

-       drm_device_t *dev = priv->dev;
+       drm_device_t *dev = priv->head->dev;

        drm_ctx_t ctx;
 
        if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) )
        drm_ctx_t ctx;
 
        if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) )


@@ -541,7 +541,7 @@ int drm_rmctx( struct inode *inode, struct file *filp,
                unsigned int cmd, unsigned long arg )
 {
        drm_file_t *priv = filp->private_data;
                unsigned int cmd, unsigned long arg )
 {
        drm_file_t *priv = filp->private_data;

-       drm_device_t *dev = priv->dev;
+       drm_device_t *dev = priv->head->dev;

        drm_ctx_t ctx;
 
        if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) )
        drm_ctx_t ctx;
 
        if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) )

diff --git a/drivers/infiniband/hw/mthca/mthca_config_reg.h b/drivers/infiniband/hw/mthca/mthca_config_reg.h
index acb94ae..b4bfbbf 100644 (file)
--- a/drivers/infiniband/hw/mthca/mthca_config_reg.h
+++ b/drivers/infiniband/hw/mthca/mthca_config_reg.h
@@ -46,5 +46,6 @@
 #define MTHCA_MAP_ECR_SIZE     (MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE)
 #define MTHCA_CLR_INT_BASE     0xf00d8
 #define MTHCA_CLR_INT_SIZE     0x00008
 #define MTHCA_MAP_ECR_SIZE     (MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE)
 #define MTHCA_CLR_INT_BASE     0xf00d8
 #define MTHCA_CLR_INT_SIZE     0x00008

+#define MTHCA_EQ_SET_CI_SIZE   (8 * 32)

 
 #endif /* MTHCA_CONFIG_REG_H */
 
 #endif /* MTHCA_CONFIG_REG_H */

diff --git a/drivers/infiniband/hw/mthca/mthca_doorbell.h b/drivers/infiniband/hw/mthca/mthca_doorbell.h
index cc8ad11..821039a 100644 (file)
--- a/drivers/infiniband/hw/mthca/mthca_doorbell.h
+++ b/drivers/infiniband/hw/mthca/mthca_doorbell.h
@@ -51,12 +51,22 @@
 #define MTHCA_INIT_DOORBELL_LOCK(ptr)    do { } while (0)
 #define MTHCA_GET_DOORBELL_LOCK(ptr)      (NULL)
 
 #define MTHCA_INIT_DOORBELL_LOCK(ptr)    do { } while (0)
 #define MTHCA_GET_DOORBELL_LOCK(ptr)      (NULL)
 

+static inline void mthca_write64_raw(__be64 val, void __iomem *dest)
+{
+       __raw_writeq((__force u64) val, dest);
+}
+

 static inline void mthca_write64(u32 val[2], void __iomem *dest,
                                 spinlock_t *doorbell_lock)
 {
        __raw_writeq(*(u64 *) val, dest);
 }
 
 static inline void mthca_write64(u32 val[2], void __iomem *dest,
                                 spinlock_t *doorbell_lock)
 {
        __raw_writeq(*(u64 *) val, dest);
 }
 

+static inline void mthca_write_db_rec(u32 val[2], u32 *db)
+{
+       *(u64 *) db = *(u64 *) val;
+}
+

 #else
 
 /*
 #else
 
 /*


@@ -69,6 +79,12 @@ static inline void mthca_write64(u32 val[2], void __iomem *dest,
 #define MTHCA_INIT_DOORBELL_LOCK(ptr)     spin_lock_init(ptr)
 #define MTHCA_GET_DOORBELL_LOCK(ptr)      (ptr)
 
 #define MTHCA_INIT_DOORBELL_LOCK(ptr)     spin_lock_init(ptr)
 #define MTHCA_GET_DOORBELL_LOCK(ptr)      (ptr)
 

+static inline void mthca_write64_raw(__be64 val, void __iomem *dest)
+{
+       __raw_writel(((__force u32 *) &val)[0], dest);
+       __raw_writel(((__force u32 *) &val)[1], dest + 4);
+}
+

 static inline void mthca_write64(u32 val[2], void __iomem *dest,
                                 spinlock_t *doorbell_lock)
 {
 static inline void mthca_write64(u32 val[2], void __iomem *dest,
                                 spinlock_t *doorbell_lock)
 {


@@ -80,4 +96,11 @@ static inline void mthca_write64(u32 val[2], void __iomem *dest,
        spin_unlock_irqrestore(doorbell_lock, flags);
 }
 
        spin_unlock_irqrestore(doorbell_lock, flags);
 }
 

+static inline void mthca_write_db_rec(u32 val[2], u32 *db)
+{
+       db[0] = val[0];
+       wmb();
+       db[1] = val[1];
+}
+

 #endif
 #endif

diff --git a/drivers/infiniband/hw/mthca/mthca_profile.h b/drivers/infiniband/hw/mthca/mthca_profile.h
index daaf799..17aef33 100644 (file)
--- a/drivers/infiniband/hw/mthca/mthca_profile.h
+++ b/drivers/infiniband/hw/mthca/mthca_profile.h
@@ -48,6 +48,7 @@ struct mthca_profile {
        int num_udav;
        int num_uar;
        int uarc_size;
        int num_udav;
        int num_uar;
        int uarc_size;

+       int fmr_reserved_mtts;

 };
 
 u64 mthca_make_profile(struct mthca_dev *mdev,
 };
 
 u64 mthca_make_profile(struct mthca_dev *mdev,

diff --git a/drivers/md/raid6altivec.uc b/drivers/md/raid6altivec.uc
index f4ff644..1de8f03 100644 (file)
--- a/drivers/md/raid6altivec.uc
+++ b/drivers/md/raid6altivec.uc
@@ -108,11 +108,7 @@ int raid6_have_altivec(void);
 int raid6_have_altivec(void)
 {
        /* This assumes either all CPUs have Altivec or none does */
 int raid6_have_altivec(void)
 {
        /* This assumes either all CPUs have Altivec or none does */

-#ifdef CONFIG_PPC64
-       return cur_cpu_spec->cpu_features & CPU_FTR_ALTIVEC;
-#else
-       return cur_cpu_spec[0]->cpu_features & CPU_FTR_ALTIVEC;
-#endif
+       return cpu_has_feature(CPU_FTR_ALTIVEC);

 }
 #endif
 
 }
 #endif
 

diff --git a/drivers/net/arcnet/capmode.c b/drivers/net/arcnet/capmode.c
index 16e155b..6648558 100644 (file)
--- a/drivers/net/arcnet/capmode.c
+++ b/drivers/net/arcnet/capmode.c
@@ -48,7 +48,7 @@ static int prepare_tx(struct net_device *dev, struct archdr *pkt, int length,
 static int ack_tx(struct net_device *dev, int acked);
 
 
 static int ack_tx(struct net_device *dev, int acked);
 
 

-struct ArcProto capmode_proto =
+static struct ArcProto capmode_proto =

 {
        'r',
        XMTU,
 {
        'r',
        XMTU,

diff --git a/drivers/s390/net/ctcdbug.h b/drivers/s390/net/ctcdbug.h
index ef88839..7fe2ebd 100644 (file)
--- a/drivers/s390/net/ctcdbug.h
+++ b/drivers/s390/net/ctcdbug.h
@@ -1,6 +1,6 @@
 /*
  *
 /*
  *

- * linux/drivers/s390/net/ctcdbug.h ($Revision: 1.4 $)
+ * linux/drivers/s390/net/ctcdbug.h ($Revision: 1.5 $)

  *
  * CTC / ESCON network driver - s390 dbf exploit.
  *
  *
  * CTC / ESCON network driver - s390 dbf exploit.
  *


@@ -9,7 +9,7 @@
  *    Author(s): Original Code written by
  *                       Peter Tiedemann (ptiedem@de.ibm.com)
  *
  *    Author(s): Original Code written by
  *                       Peter Tiedemann (ptiedem@de.ibm.com)
  *

- *    $Revision: 1.4 $  $Date: 2004/10/15 09:26:58 $
+ *    $Revision: 1.5 $  $Date: 2005/02/27 19:46:44 $

  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by


@@ -25,9 +25,11 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */

-
+#ifndef _CTCDBUG_H_
+#define _CTCDBUG_H_

 
 #include <asm/debug.h>
 
 #include <asm/debug.h>

+#include "ctcmain.h"

 /**
  * Debug Facility stuff
  */
 /**
  * Debug Facility stuff
  */


@@ -41,7 +43,7 @@
 #define CTC_DBF_DATA_LEN 128
 #define CTC_DBF_DATA_INDEX 3
 #define CTC_DBF_DATA_NR_AREAS 1
 #define CTC_DBF_DATA_LEN 128
 #define CTC_DBF_DATA_INDEX 3
 #define CTC_DBF_DATA_NR_AREAS 1

-#define CTC_DBF_DATA_LEVEL 2
+#define CTC_DBF_DATA_LEVEL 3

 
 #define CTC_DBF_TRACE_NAME "ctc_trace"
 #define CTC_DBF_TRACE_LEN 16
 
 #define CTC_DBF_TRACE_NAME "ctc_trace"
 #define CTC_DBF_TRACE_LEN 16


@@ -121,3 +123,5 @@ hex_dump(unsigned char *buf, size_t len)
        printk("\n");
 }
 
        printk("\n");
 }
 

+
+#endif

diff --git a/fs/isofs/export.c b/fs/isofs/export.c
index e4252c9..4af856a 100644 (file)
--- a/fs/isofs/export.c
+++ b/fs/isofs/export.c
@@ -13,11 +13,7 @@
  *     fs/exportfs/expfs.c.
  */
 
  *     fs/exportfs/expfs.c.
  */
 

-#include <linux/buffer_head.h>
-#include <linux/errno.h>
-#include <linux/fs.h>
-#include <linux/iso_fs.h>
-#include <linux/kernel.h>
+#include "isofs.h"

 
 static struct dentry *
 isofs_export_iget(struct super_block *sb,
 
 static struct dentry *
 isofs_export_iget(struct super_block *sb,

diff --git a/fs/proc/mmu.c b/fs/proc/mmu.c
index a704103..25d2d9c 100644 (file)
--- a/fs/proc/mmu.c
+++ b/fs/proc/mmu.c
@@ -50,13 +50,23 @@ void get_vmalloc_info(struct vmalloc_info *vmi)
                read_lock(&vmlist_lock);
 
                for (vma = vmlist; vma; vma = vma->next) {
                read_lock(&vmlist_lock);
 
                for (vma = vmlist; vma; vma = vma->next) {

+                       unsigned long addr = (unsigned long) vma->addr;
+
+                       /*
+                        * Some archs keep another range for modules in vmlist
+                        */
+                       if (addr < VMALLOC_START)
+                               continue;
+                       if (addr >= VMALLOC_END)
+                               break;
+

                        vmi->used += vma->size;
 
                        vmi->used += vma->size;
 

-                       free_area_size = (unsigned long) vma->addr - prev_end;
+                       free_area_size = addr - prev_end;

                        if (vmi->largest_chunk < free_area_size)
                                vmi->largest_chunk = free_area_size;
 
                        if (vmi->largest_chunk < free_area_size)
                                vmi->largest_chunk = free_area_size;
 

-                       prev_end = vma->size + (unsigned long) vma->addr;
+                       prev_end = vma->size + addr;

                }
 
                if (VMALLOC_END - prev_end > vmi->largest_chunk)
                }
 
                if (VMALLOC_END - prev_end > vmi->largest_chunk)

diff --git a/include/asm-arm/arch-ixp2000/entry-macro.S b/include/asm-arm/arch-ixp2000/entry-macro.S
index 44db57c..e3a4e41 100644 (file)
--- a/include/asm-arm/arch-ixp2000/entry-macro.S
+++ b/include/asm-arm/arch-ixp2000/entry-macro.S
@@ -15,8 +15,7 @@
 
                mov     \irqnr, #0x0              @clear out irqnr as default
                 mov    \base, #0xfe000000
 
                mov     \irqnr, #0x0              @clear out irqnr as default
                 mov    \base, #0xfe000000

-               orr     \base, \base, #0x00ff0000
-               orr     \base, \base, #0x0000a000
+               orr     \base, \base, #0x00e00000

                orr     \base, \base, #0x08
                ldr     \irqstat, [\base]         @ get interrupts
 
                orr     \base, \base, #0x08
                ldr     \irqstat, [\base]         @ get interrupts
 


@@ -35,8 +34,8 @@
                bne     1001f
 
                mov     \base, #0xfe000000
                bne     1001f
 
                mov     \base, #0xfe000000

-               orr     \base, \base, #0x00fd0000
-               orr     \base, \base, #0x0000e100
+               orr     \base, \base, #0x00c00000
+               orr     \base, \base, #0x00000100

                orr     \base, \base, #0x00000058
                ldr     \irqstat, [\base]
 
                orr     \base, \base, #0x00000058
                ldr     \irqstat, [\base]
 

diff --git a/include/asm-arm/arch-ixp4xx/vmalloc.h b/include/asm-arm/arch-ixp4xx/vmalloc.h
index da46e56..050d46e 100644 (file)
--- a/include/asm-arm/arch-ixp4xx/vmalloc.h
+++ b/include/asm-arm/arch-ixp4xx/vmalloc.h
@@ -1,17 +1,5 @@
 /*
  * linux/include/asm-arm/arch-ixp4xx/vmalloc.h
  */
 /*
  * linux/include/asm-arm/arch-ixp4xx/vmalloc.h
  */

-
-/*
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-#define VMALLOC_OFFSET   (8*1024*1024)
-#define VMALLOC_START    (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
-#define VMALLOC_VMADDR(x) ((unsigned long)(x))

 #define VMALLOC_END       (0xFF000000)
 
 #define VMALLOC_END       (0xFF000000)
 

diff --git a/include/asm-arm/arch-pxa/corgi.h b/include/asm-arm/arch-pxa/corgi.h
index 950c937..324db06 100644 (file)
--- a/include/asm-arm/arch-pxa/corgi.h
+++ b/include/asm-arm/arch-pxa/corgi.h
@@ -100,39 +100,9 @@
 
 
 /*
 
 
 /*

- * Corgi Parameter Area Definitions
+ * Shared data structures

  */
  */

-#define FLASH_MEM_BASE 0xa0000a00
-#define FLASH_MAGIC_CHG(a,b,c,d) ( ( d << 24 ) | ( c << 16 )  | ( b << 8 ) | a )
-
-#define FLASH_COMADJ_MAJIC     FLASH_MAGIC_CHG('C','M','A','D')
-#define        FLASH_COMADJ_MAGIC_ADR  0x00
-#define        FLASH_COMADJ_DATA_ADR   0x04
-
-#define FLASH_PHAD_MAJIC       FLASH_MAGIC_CHG('P','H','A','D')
-#define        FLASH_PHAD_MAGIC_ADR    0x38
-#define        FLASH_PHAD_DATA_ADR     0x3C
-
-struct sharpsl_flash_param_info {
-  unsigned int comadj_keyword;
-  unsigned int comadj;
-
-  unsigned int uuid_keyword;
-  unsigned char uuid[16];
-
-  unsigned int touch_keyword;
-  unsigned int touch1;
-  unsigned int touch2;
-  unsigned int touch3;
-  unsigned int touch4;
-
-  unsigned int adadj_keyword;
-  unsigned int adadj;
-
-  unsigned int phad_keyword;
-  unsigned int phadadj;
-};
-
+extern struct platform_device corgiscoop_device;

 
 /*
  * External Functions
 
 /*
  * External Functions

diff --git a/include/asm-arm/hardware/scoop.h b/include/asm-arm/hardware/scoop.h
index 669b7df..7ea771f 100644 (file)
--- a/include/asm-arm/hardware/scoop.h
+++ b/include/asm-arm/hardware/scoop.h
@@ -40,8 +40,8 @@ struct scoop_config {
        unsigned short io_dir;
 };
 
        unsigned short io_dir;
 };
 

-void reset_scoop(void);
-unsigned short set_scoop_gpio(unsigned short bit);
-unsigned short reset_scoop_gpio(unsigned short bit);
-unsigned short read_scoop_reg(unsigned short reg);
-void write_scoop_reg(unsigned short reg, unsigned short data);
+void reset_scoop(struct device *dev);
+unsigned short set_scoop_gpio(struct device *dev, unsigned short bit);
+unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit);
+unsigned short read_scoop_reg(struct device *dev, unsigned short reg);
+void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data);

diff --git a/include/asm-frv/ipc.h b/include/asm-frv/ipc.h
index 2f72065..a46e3d9 100644 (file)
--- a/include/asm-frv/ipc.h
+++ b/include/asm-frv/ipc.h
@@ -1,33 +1 @@
-#ifndef __ASM_IPC_H__
-#define __ASM_IPC_H__
-
-/*
- * These are used to wrap system calls on FR-V
- *
- * See arch/frv/kernel/sys_frv.c for ugly details..
- */
-struct ipc_kludge {
-       struct msgbuf __user *msgp;
-       long msgtyp;
-};
-
-#define SEMOP           1
-#define SEMGET          2
-#define SEMCTL          3
-#define SEMTIMEDOP      4
-#define MSGSND         11
-#define MSGRCV         12
-#define MSGGET         13
-#define MSGCTL         14
-#define SHMAT          21
-#define SHMDT          22
-#define SHMGET         23
-#define SHMCTL         24
-
-/* Used by the DIPC package, try and avoid reusing it */
-#define DIPC           25
-
-#define IPCCALL(version,op)    ((version)<<16 | (op))
-
-#endif
-
+#include <asm-generic/ipc.h>

diff --git a/include/asm-generic/resource.h b/include/asm-generic/resource.h
index 7ba1bfc..cfe3692 100644 (file)
--- a/include/asm-generic/resource.h
+++ b/include/asm-generic/resource.h
@@ -2,57 +2,90 @@
 #define _ASM_GENERIC_RESOURCE_H
 
 /*
 #define _ASM_GENERIC_RESOURCE_H
 
 /*

- * Resource limits
+ * Resource limit IDs
+ *
+ * ( Compatibility detail: there are architectures that have
+ *   a different rlimit ID order in the 5-9 range and want
+ *   to keep that order for binary compatibility. The reasons
+ *   are historic and all new rlimits are identical across all
+ *   arches. If an arch has such special order for some rlimits
+ *   then it defines them prior including asm-generic/resource.h. )

  */
 
  */
 

-/* Allow arch to control resource order */
-#ifndef __ARCH_RLIMIT_ORDER

 #define RLIMIT_CPU             0       /* CPU time in ms */
 #define RLIMIT_FSIZE           1       /* Maximum filesize */
 #define RLIMIT_DATA            2       /* max data size */
 #define RLIMIT_STACK           3       /* max stack size */
 #define RLIMIT_CORE            4       /* max core file size */
 #define RLIMIT_CPU             0       /* CPU time in ms */
 #define RLIMIT_FSIZE           1       /* Maximum filesize */
 #define RLIMIT_DATA            2       /* max data size */
 #define RLIMIT_STACK           3       /* max stack size */
 #define RLIMIT_CORE            4       /* max core file size */

-#define RLIMIT_RSS             5       /* max resident set size */
-#define RLIMIT_NPROC           6       /* max number of processes */
-#define RLIMIT_NOFILE          7       /* max number of open files */
-#define RLIMIT_MEMLOCK         8       /* max locked-in-memory address space */
-#define RLIMIT_AS              9       /* address space limit */
+
+#ifndef RLIMIT_RSS
+# define RLIMIT_RSS            5       /* max resident set size */
+#endif
+
+#ifndef RLIMIT_NPROC
+# define RLIMIT_NPROC          6       /* max number of processes */
+#endif
+
+#ifndef RLIMIT_NOFILE
+# define RLIMIT_NOFILE         7       /* max number of open files */
+#endif
+
+#ifndef RLIMIT_MEMLOCK
+# define RLIMIT_MEMLOCK                8       /* max locked-in-memory address space */
+#endif
+
+#ifndef RLIMIT_AS
+# define RLIMIT_AS             9       /* address space limit */
+#endif
+

 #define RLIMIT_LOCKS           10      /* maximum file locks held */
 #define RLIMIT_SIGPENDING      11      /* max number of pending signals */
 #define RLIMIT_MSGQUEUE                12      /* maximum bytes in POSIX mqueues */
 #define RLIMIT_LOCKS           10      /* maximum file locks held */
 #define RLIMIT_SIGPENDING      11      /* max number of pending signals */
 #define RLIMIT_MSGQUEUE                12      /* maximum bytes in POSIX mqueues */

+#define RLIMIT_NICE            13      /* max nice prio allowed to raise to
+                                          0-39 for nice level 19 .. -20 */
+#define RLIMIT_RTPRIO          14      /* maximum realtime priority */

 
 

-#define RLIM_NLIMITS           13
-#endif
+#define RLIM_NLIMITS           15

 
 /*
  * SuS says limits have to be unsigned.
  * Which makes a ton more sense anyway.
 
 /*
  * SuS says limits have to be unsigned.
  * Which makes a ton more sense anyway.

+ *
+ * Some architectures override this (for compatibility reasons):

  */
 #ifndef RLIM_INFINITY
  */
 #ifndef RLIM_INFINITY

-#define RLIM_INFINITY  (~0UL)
+# define RLIM_INFINITY         (~0UL)

 #endif
 
 #endif
 

+/*
+ * RLIMIT_STACK default maximum - some architectures override it:
+ */

 #ifndef _STK_LIM_MAX
 #ifndef _STK_LIM_MAX

-#define _STK_LIM_MAX   RLIM_INFINITY
+# define _STK_LIM_MAX          RLIM_INFINITY

 #endif
 
 #ifdef __KERNEL__
 
 #endif
 
 #ifdef __KERNEL__
 

+/*
+ * boot-time rlimit defaults for the init task:
+ */

 #define INIT_RLIMITS                                                   \
 {                                                                      \
 #define INIT_RLIMITS                                                   \
 {                                                                      \

-       [RLIMIT_CPU]            = { RLIM_INFINITY, RLIM_INFINITY },     \
-       [RLIMIT_FSIZE]          = { RLIM_INFINITY, RLIM_INFINITY },     \
-       [RLIMIT_DATA]           = { RLIM_INFINITY, RLIM_INFINITY },     \
-       [RLIMIT_STACK]          = {      _STK_LIM, _STK_LIM_MAX  },     \
-       [RLIMIT_CORE]           = {             0, RLIM_INFINITY },     \
-       [RLIMIT_RSS]            = { RLIM_INFINITY, RLIM_INFINITY },     \
-       [RLIMIT_NPROC]          = {             0,             0 },     \
-       [RLIMIT_NOFILE]         = {      INR_OPEN,     INR_OPEN  },     \
-       [RLIMIT_MEMLOCK]        = {   MLOCK_LIMIT,   MLOCK_LIMIT },     \
-       [RLIMIT_AS]             = { RLIM_INFINITY, RLIM_INFINITY },     \
-       [RLIMIT_LOCKS]          = { RLIM_INFINITY, RLIM_INFINITY },     \
-       [RLIMIT_SIGPENDING]     = { MAX_SIGPENDING, MAX_SIGPENDING },   \
-       [RLIMIT_MSGQUEUE]       = { MQ_BYTES_MAX, MQ_BYTES_MAX },       \
+       [RLIMIT_CPU]            = {  RLIM_INFINITY,  RLIM_INFINITY },   \
+       [RLIMIT_FSIZE]          = {  RLIM_INFINITY,  RLIM_INFINITY },   \
+       [RLIMIT_DATA]           = {  RLIM_INFINITY,  RLIM_INFINITY },   \
+       [RLIMIT_STACK]          = {       _STK_LIM,   _STK_LIM_MAX },   \
+       [RLIMIT_CORE]           = {              0,  RLIM_INFINITY },   \
+       [RLIMIT_RSS]            = {  RLIM_INFINITY,  RLIM_INFINITY },   \
+       [RLIMIT_NPROC]          = {              0,              0 },   \
+       [RLIMIT_NOFILE]         = {       INR_OPEN,       INR_OPEN },   \
+       [RLIMIT_MEMLOCK]        = {    MLOCK_LIMIT,    MLOCK_LIMIT },   \
+       [RLIMIT_AS]             = {  RLIM_INFINITY,  RLIM_INFINITY },   \
+       [RLIMIT_LOCKS]          = {  RLIM_INFINITY,  RLIM_INFINITY },   \
+       [RLIMIT_SIGPENDING]     = {             0,             0 },     \
+       [RLIMIT_MSGQUEUE]       = {   MQ_BYTES_MAX,   MQ_BYTES_MAX },   \
+       [RLIMIT_NICE]           = { 0, 0 },                             \
+       [RLIMIT_RTPRIO]         = { 0, 0 },                             \

 }
 
 #endif /* __KERNEL__ */
 }
 
 #endif /* __KERNEL__ */

diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h
index 5c2fcf1..323fa0c 100644 (file)
--- a/include/asm-ia64/sn/shub_mmr.h
+++ b/include/asm-ia64/sn/shub_mmr.h
@@ -4,7 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *

- * Copyright (c) 2001-2004 Silicon Graphics, Inc.  All rights reserved.
+ * Copyright (c) 2001-2005 Silicon Graphics, Inc.  All rights reserved.

  */
 
 #ifndef _ASM_IA64_SN_SHUB_MMR_H
  */
 
 #ifndef _ASM_IA64_SN_SHUB_MMR_H


@@ -129,6 +129,23 @@
 #define SH_EVENT_OCCURRED_II_INT1_SHFT           30
 #define SH_EVENT_OCCURRED_II_INT1_MASK           0x0000000040000000
 
 #define SH_EVENT_OCCURRED_II_INT1_SHFT           30
 #define SH_EVENT_OCCURRED_II_INT1_MASK           0x0000000040000000
 

+/*   SH2_EVENT_OCCURRED_EXTIO_INT2                                      */
+/*   Description:  Pending SHUB 2 EXT IO INT2                           */
+#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT       33
+#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK       0x0000000200000000
+
+/*   SH2_EVENT_OCCURRED_EXTIO_INT3                                      */
+/*   Description:  Pending SHUB 2 EXT IO INT3                           */
+#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT       34
+#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK       0x0000000400000000
+
+#define SH_ALL_INT_MASK \
+       (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
+        SH_EVENT_OCCURRED_II_INT0_MASK | SH_EVENT_OCCURRED_II_INT1_MASK | \
+        SH_EVENT_OCCURRED_II_INT1_MASK | SH2_EVENT_OCCURRED_EXTIO_INT2_MASK | \
+        SH2_EVENT_OCCURRED_EXTIO_INT3_MASK)
+
+

 /* ==================================================================== */
 /*                         LEDS                                         */
 /* ==================================================================== */
 /* ==================================================================== */
 /*                         LEDS                                         */
 /* ==================================================================== */


@@ -367,6 +384,17 @@
 #define SH_EVENT_OCCURRED_RTC3_INT_SHFT          26
 #define SH_EVENT_OCCURRED_RTC3_INT_MASK          0x0000000004000000
 
 #define SH_EVENT_OCCURRED_RTC3_INT_SHFT          26
 #define SH_EVENT_OCCURRED_RTC3_INT_MASK          0x0000000004000000
 

+/* ==================================================================== */
+/*                       Register "SH_IPI_ACCESS"                       */
+/*                 CPU interrupt Access Permission Bits                 */
+/* ==================================================================== */
+
+#define SH1_IPI_ACCESS                           0x0000000110060480
+#define SH2_IPI_ACCESS0                          0x0000000010060c00
+#define SH2_IPI_ACCESS1                          0x0000000010060c80
+#define SH2_IPI_ACCESS2                          0x0000000010060d00
+#define SH2_IPI_ACCESS3                          0x0000000010060d80
+

 /* ==================================================================== */
 /*                        Register "SH_INT_CMPB"                        */
 /*                  RTC Compare Value for Processor B                   */
 /* ==================================================================== */
 /*                        Register "SH_INT_CMPB"                        */
 /*                  RTC Compare Value for Processor B                   */


@@ -412,6 +440,19 @@
 #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT          0
 #define SH_INT_CMPD_REAL_TIME_CMPD_MASK          0x007fffffffffffff
 
 #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT          0
 #define SH_INT_CMPD_REAL_TIME_CMPD_MASK          0x007fffffffffffff
 

+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+
+#define SH1_MD_DQLP_MMR_DIR_PRIVEC0              0x0000000100030300
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+
+#define SH1_MD_DQRP_MMR_DIR_PRIVEC0              0x0000000100050300

 
 /* ==================================================================== */
 /* Some MMRs are functionally identical (or close enough) on both SHUB1 */
 
 /* ==================================================================== */
 /* Some MMRs are functionally identical (or close enough) on both SHUB1 */


@@ -438,4 +479,22 @@
 #define SH_INT_CMPC            shubmmr(SH, INT_CMPC)
 #define SH_INT_CMPD            shubmmr(SH, INT_CMPD)
 
 #define SH_INT_CMPC            shubmmr(SH, INT_CMPC)
 #define SH_INT_CMPD            shubmmr(SH, INT_CMPD)
 

+/* ========================================================================== */
+/*                        Register "SH2_BT_ENG_CSR_0"                         */
+/*                    Engine 0 Control and Status Register                    */
+/* ========================================================================== */
+
+#define SH2_BT_ENG_CSR_0                         0x0000000030040000
+#define SH2_BT_ENG_SRC_ADDR_0                    0x0000000030040080
+#define SH2_BT_ENG_DEST_ADDR_0                   0x0000000030040100
+#define SH2_BT_ENG_NOTIF_ADDR_0                  0x0000000030040180
+
+/* ========================================================================== */
+/*                       BTE interfaces 1-3                                   */
+/* ========================================================================== */
+
+#define SH2_BT_ENG_CSR_1                         0x0000000030050000
+#define SH2_BT_ENG_CSR_2                         0x0000000030060000
+#define SH2_BT_ENG_CSR_3                         0x0000000030070000
+

 #endif /* _ASM_IA64_SN_SHUB_MMR_H */
 #endif /* _ASM_IA64_SN_SHUB_MMR_H */

diff --git a/include/asm-ia64/sn/shubio.h b/include/asm-ia64/sn/shubio.h
index fbd880e..831b721 100644 (file)
--- a/include/asm-ia64/sn/shubio.h
+++ b/include/asm-ia64/sn/shubio.h
@@ -3,292 +3,287 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *

- * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.

  */
 
 #ifndef _ASM_IA64_SN_SHUBIO_H
 #define _ASM_IA64_SN_SHUBIO_H
 
  */
 
 #ifndef _ASM_IA64_SN_SHUBIO_H
 #define _ASM_IA64_SN_SHUBIO_H
 

-#define HUB_WIDGET_ID_MAX 0xf
-#define IIO_NUM_ITTES   7
-#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
-
-#define    IIO_WID                   0x00400000    /* Crosstalk Widget Identification */
-                                                   /* This register is also accessible from
-                                                    * Crosstalk at address 0x0.  */
-#define    IIO_WSTAT                 0x00400008    /* Crosstalk Widget Status */
-#define    IIO_WCR                   0x00400020    /* Crosstalk Widget Control Register */
-#define    IIO_ILAPR                 0x00400100    /* IO Local Access Protection Register */
-#define    IIO_ILAPO                 0x00400108    /* IO Local Access Protection Override */
-#define    IIO_IOWA                  0x00400110    /* IO Outbound Widget Access */
-#define    IIO_IIWA                  0x00400118    /* IO Inbound Widget Access */
-#define    IIO_IIDEM                 0x00400120    /* IO Inbound Device Error Mask */
-#define    IIO_ILCSR                 0x00400128    /* IO LLP Control and Status Register */
-#define    IIO_ILLR                  0x00400130    /* IO LLP Log Register    */
-#define    IIO_IIDSR                 0x00400138    /* IO Interrupt Destination */
-
-#define    IIO_IGFX0                 0x00400140    /* IO Graphics Node-Widget Map 0 */
-#define    IIO_IGFX1                 0x00400148    /* IO Graphics Node-Widget Map 1 */
-
-#define    IIO_ISCR0                 0x00400150    /* IO Scratch Register 0 */
-#define    IIO_ISCR1                 0x00400158    /* IO Scratch Register 1 */
-
-#define    IIO_ITTE1                 0x00400160    /* IO Translation Table Entry 1 */
-#define    IIO_ITTE2                 0x00400168    /* IO Translation Table Entry 2 */
-#define    IIO_ITTE3                 0x00400170    /* IO Translation Table Entry 3 */
-#define    IIO_ITTE4                 0x00400178    /* IO Translation Table Entry 4 */
-#define    IIO_ITTE5                 0x00400180    /* IO Translation Table Entry 5 */
-#define    IIO_ITTE6                 0x00400188    /* IO Translation Table Entry 6 */
-#define    IIO_ITTE7                 0x00400190    /* IO Translation Table Entry 7 */
-
-#define    IIO_IPRB0                 0x00400198    /* IO PRB Entry 0         */
-#define    IIO_IPRB8                 0x004001A0    /* IO PRB Entry 8         */
-#define    IIO_IPRB9                 0x004001A8    /* IO PRB Entry 9         */
-#define    IIO_IPRBA                 0x004001B0    /* IO PRB Entry A         */
-#define    IIO_IPRBB                 0x004001B8    /* IO PRB Entry B         */
-#define    IIO_IPRBC                 0x004001C0    /* IO PRB Entry C         */
-#define    IIO_IPRBD                 0x004001C8    /* IO PRB Entry D         */
-#define    IIO_IPRBE                 0x004001D0    /* IO PRB Entry E         */
-#define    IIO_IPRBF                 0x004001D8    /* IO PRB Entry F         */
-
-#define    IIO_IXCC                  0x004001E0    /* IO Crosstalk Credit Count Timeout */
-#define    IIO_IMEM                  0x004001E8    /* IO Miscellaneous Error Mask */
-#define    IIO_IXTT                  0x004001F0    /* IO Crosstalk Timeout Threshold */
-#define    IIO_IECLR                 0x004001F8    /* IO Error Clear Register */
-#define    IIO_IBCR                  0x00400200    /* IO BTE Control Register */
-
-#define    IIO_IXSM                  0x00400208    /* IO Crosstalk Spurious Message */
-#define    IIO_IXSS                  0x00400210    /* IO Crosstalk Spurious Sideband */
-
-#define    IIO_ILCT                  0x00400218    /* IO LLP Channel Test    */
-
-#define    IIO_IIEPH1                0x00400220    /* IO Incoming Error Packet Header, Part 1 */
-#define    IIO_IIEPH2                0x00400228    /* IO Incoming Error Packet Header, Part 2 */
-
-
-#define    IIO_ISLAPR                0x00400230    /* IO SXB Local Access Protection Regster */
-#define    IIO_ISLAPO                0x00400238    /* IO SXB Local Access Protection Override */
-
-#define    IIO_IWI                   0x00400240    /* IO Wrapper Interrupt Register */
-#define    IIO_IWEL                  0x00400248    /* IO Wrapper Error Log Register */
-#define    IIO_IWC                   0x00400250    /* IO Wrapper Control Register */
-#define    IIO_IWS                   0x00400258    /* IO Wrapper Status Register */
-#define    IIO_IWEIM                 0x00400260    /* IO Wrapper Error Interrupt Masking Register */
-
-#define    IIO_IPCA                  0x00400300    /* IO PRB Counter Adjust */
-
-#define    IIO_IPRTE0_A              0x00400308    /* IO PIO Read Address Table Entry 0, Part A */
-#define    IIO_IPRTE1_A              0x00400310    /* IO PIO Read Address Table Entry 1, Part A */
-#define    IIO_IPRTE2_A              0x00400318    /* IO PIO Read Address Table Entry 2, Part A */
-#define    IIO_IPRTE3_A               0x00400320    /* IO PIO Read Address Table Entry 3, Part A */
-#define    IIO_IPRTE4_A               0x00400328    /* IO PIO Read Address Table Entry 4, Part A */
-#define    IIO_IPRTE5_A               0x00400330    /* IO PIO Read Address Table Entry 5, Part A */
-#define    IIO_IPRTE6_A               0x00400338    /* IO PIO Read Address Table Entry 6, Part A */
-#define    IIO_IPRTE7_A               0x00400340    /* IO PIO Read Address Table Entry 7, Part A */
-
-#define    IIO_IPRTE0_B              0x00400348    /* IO PIO Read Address Table Entry 0, Part B */
-#define    IIO_IPRTE1_B              0x00400350    /* IO PIO Read Address Table Entry 1, Part B */
-#define    IIO_IPRTE2_B              0x00400358    /* IO PIO Read Address Table Entry 2, Part B */
-#define    IIO_IPRTE3_B               0x00400360    /* IO PIO Read Address Table Entry 3, Part B */
-#define    IIO_IPRTE4_B               0x00400368    /* IO PIO Read Address Table Entry 4, Part B */
-#define    IIO_IPRTE5_B               0x00400370    /* IO PIO Read Address Table Entry 5, Part B */
-#define    IIO_IPRTE6_B               0x00400378    /* IO PIO Read Address Table Entry 6, Part B */
-#define    IIO_IPRTE7_B               0x00400380    /* IO PIO Read Address Table Entry 7, Part B */
-
-#define    IIO_IPDR                  0x00400388    /* IO PIO Deallocation Register */
-#define    IIO_ICDR                  0x00400390    /* IO CRB Entry Deallocation Register */
-#define    IIO_IFDR                  0x00400398    /* IO IOQ FIFO Depth Register */
-#define    IIO_IIAP                  0x004003A0    /* IO IIQ Arbitration Parameters */
-#define    IIO_ICMR                  0x004003A8    /* IO CRB Management Register */
-#define    IIO_ICCR                  0x004003B0    /* IO CRB Control Register */
-#define    IIO_ICTO                  0x004003B8    /* IO CRB Timeout         */
-#define    IIO_ICTP                  0x004003C0    /* IO CRB Timeout Prescalar */
-
-#define    IIO_ICRB0_A               0x00400400    /* IO CRB Entry 0_A       */
-#define    IIO_ICRB0_B               0x00400408    /* IO CRB Entry 0_B       */
-#define    IIO_ICRB0_C               0x00400410    /* IO CRB Entry 0_C       */
-#define    IIO_ICRB0_D               0x00400418    /* IO CRB Entry 0_D       */
-#define    IIO_ICRB0_E               0x00400420    /* IO CRB Entry 0_E       */
-
-#define    IIO_ICRB1_A               0x00400430    /* IO CRB Entry 1_A       */
-#define    IIO_ICRB1_B               0x00400438    /* IO CRB Entry 1_B       */
-#define    IIO_ICRB1_C               0x00400440    /* IO CRB Entry 1_C       */
-#define    IIO_ICRB1_D               0x00400448    /* IO CRB Entry 1_D       */
-#define    IIO_ICRB1_E               0x00400450    /* IO CRB Entry 1_E       */
-
-#define    IIO_ICRB2_A               0x00400460    /* IO CRB Entry 2_A       */
-#define    IIO_ICRB2_B               0x00400468    /* IO CRB Entry 2_B       */
-#define    IIO_ICRB2_C               0x00400470    /* IO CRB Entry 2_C       */
-#define    IIO_ICRB2_D               0x00400478    /* IO CRB Entry 2_D       */
-#define    IIO_ICRB2_E               0x00400480    /* IO CRB Entry 2_E       */
-
-#define    IIO_ICRB3_A               0x00400490    /* IO CRB Entry 3_A       */
-#define    IIO_ICRB3_B               0x00400498    /* IO CRB Entry 3_B       */
-#define    IIO_ICRB3_C               0x004004a0    /* IO CRB Entry 3_C       */
-#define    IIO_ICRB3_D               0x004004a8    /* IO CRB Entry 3_D       */
-#define    IIO_ICRB3_E               0x004004b0    /* IO CRB Entry 3_E       */
-
-#define    IIO_ICRB4_A               0x004004c0    /* IO CRB Entry 4_A       */
-#define    IIO_ICRB4_B               0x004004c8    /* IO CRB Entry 4_B       */
-#define    IIO_ICRB4_C               0x004004d0    /* IO CRB Entry 4_C       */
-#define    IIO_ICRB4_D               0x004004d8    /* IO CRB Entry 4_D       */
-#define    IIO_ICRB4_E               0x004004e0    /* IO CRB Entry 4_E       */
-
-#define    IIO_ICRB5_A               0x004004f0    /* IO CRB Entry 5_A       */
-#define    IIO_ICRB5_B               0x004004f8    /* IO CRB Entry 5_B       */
-#define    IIO_ICRB5_C               0x00400500    /* IO CRB Entry 5_C       */
-#define    IIO_ICRB5_D               0x00400508    /* IO CRB Entry 5_D       */
-#define    IIO_ICRB5_E               0x00400510    /* IO CRB Entry 5_E       */
-
-#define    IIO_ICRB6_A               0x00400520    /* IO CRB Entry 6_A       */
-#define    IIO_ICRB6_B               0x00400528    /* IO CRB Entry 6_B       */
-#define    IIO_ICRB6_C               0x00400530    /* IO CRB Entry 6_C       */
-#define    IIO_ICRB6_D               0x00400538    /* IO CRB Entry 6_D       */
-#define    IIO_ICRB6_E               0x00400540    /* IO CRB Entry 6_E       */
-
-#define    IIO_ICRB7_A               0x00400550    /* IO CRB Entry 7_A       */
-#define    IIO_ICRB7_B               0x00400558    /* IO CRB Entry 7_B       */
-#define    IIO_ICRB7_C               0x00400560    /* IO CRB Entry 7_C       */
-#define    IIO_ICRB7_D               0x00400568    /* IO CRB Entry 7_D       */
-#define    IIO_ICRB7_E               0x00400570    /* IO CRB Entry 7_E       */
-
-#define    IIO_ICRB8_A               0x00400580    /* IO CRB Entry 8_A       */
-#define    IIO_ICRB8_B               0x00400588    /* IO CRB Entry 8_B       */
-#define    IIO_ICRB8_C               0x00400590    /* IO CRB Entry 8_C       */
-#define    IIO_ICRB8_D               0x00400598    /* IO CRB Entry 8_D       */
-#define    IIO_ICRB8_E               0x004005a0    /* IO CRB Entry 8_E       */
-
-#define    IIO_ICRB9_A               0x004005b0    /* IO CRB Entry 9_A       */
-#define    IIO_ICRB9_B               0x004005b8    /* IO CRB Entry 9_B       */
-#define    IIO_ICRB9_C               0x004005c0    /* IO CRB Entry 9_C       */
-#define    IIO_ICRB9_D               0x004005c8    /* IO CRB Entry 9_D       */
-#define    IIO_ICRB9_E               0x004005d0    /* IO CRB Entry 9_E       */
-
-#define    IIO_ICRBA_A               0x004005e0    /* IO CRB Entry A_A       */
-#define    IIO_ICRBA_B               0x004005e8    /* IO CRB Entry A_B       */
-#define    IIO_ICRBA_C               0x004005f0    /* IO CRB Entry A_C       */
-#define    IIO_ICRBA_D               0x004005f8    /* IO CRB Entry A_D       */
-#define    IIO_ICRBA_E               0x00400600    /* IO CRB Entry A_E       */
-
-#define    IIO_ICRBB_A               0x00400610    /* IO CRB Entry B_A       */
-#define    IIO_ICRBB_B               0x00400618    /* IO CRB Entry B_B       */
-#define    IIO_ICRBB_C               0x00400620    /* IO CRB Entry B_C       */
-#define    IIO_ICRBB_D               0x00400628    /* IO CRB Entry B_D       */
-#define    IIO_ICRBB_E               0x00400630    /* IO CRB Entry B_E       */
-
-#define    IIO_ICRBC_A               0x00400640    /* IO CRB Entry C_A       */
-#define    IIO_ICRBC_B               0x00400648    /* IO CRB Entry C_B       */
-#define    IIO_ICRBC_C               0x00400650    /* IO CRB Entry C_C       */
-#define    IIO_ICRBC_D               0x00400658    /* IO CRB Entry C_D       */
-#define    IIO_ICRBC_E               0x00400660    /* IO CRB Entry C_E       */
-
-#define    IIO_ICRBD_A               0x00400670    /* IO CRB Entry D_A       */
-#define    IIO_ICRBD_B               0x00400678    /* IO CRB Entry D_B       */
-#define    IIO_ICRBD_C               0x00400680    /* IO CRB Entry D_C       */
-#define    IIO_ICRBD_D               0x00400688    /* IO CRB Entry D_D       */
-#define    IIO_ICRBD_E               0x00400690    /* IO CRB Entry D_E       */
-
-#define    IIO_ICRBE_A               0x004006a0    /* IO CRB Entry E_A       */
-#define    IIO_ICRBE_B               0x004006a8    /* IO CRB Entry E_B       */
-#define    IIO_ICRBE_C               0x004006b0    /* IO CRB Entry E_C       */
-#define    IIO_ICRBE_D               0x004006b8    /* IO CRB Entry E_D       */
-#define    IIO_ICRBE_E               0x004006c0    /* IO CRB Entry E_E       */
-
-#define    IIO_ICSML                 0x00400700    /* IO CRB Spurious Message Low */
-#define    IIO_ICSMM                 0x00400708    /* IO CRB Spurious Message Middle */
-#define    IIO_ICSMH                 0x00400710    /* IO CRB Spurious Message High */
-
-#define    IIO_IDBSS                 0x00400718    /* IO Debug Submenu Select */
-
-#define    IIO_IBLS0                 0x00410000    /* IO BTE Length Status 0 */
-#define    IIO_IBSA0                 0x00410008    /* IO BTE Source Address 0 */
-#define    IIO_IBDA0                 0x00410010    /* IO BTE Destination Address 0 */
-#define    IIO_IBCT0                 0x00410018    /* IO BTE Control Terminate 0 */
-#define    IIO_IBNA0                 0x00410020    /* IO BTE Notification Address 0 */
-#define    IIO_IBIA0                 0x00410028    /* IO BTE Interrupt Address 0 */
-#define    IIO_IBLS1                 0x00420000    /* IO BTE Length Status 1 */
-#define    IIO_IBSA1                 0x00420008    /* IO BTE Source Address 1 */
-#define    IIO_IBDA1                 0x00420010    /* IO BTE Destination Address 1 */
-#define    IIO_IBCT1                 0x00420018    /* IO BTE Control Terminate 1 */
-#define    IIO_IBNA1                 0x00420020    /* IO BTE Notification Address 1 */
-#define    IIO_IBIA1                 0x00420028    /* IO BTE Interrupt Address 1 */
-
-#define    IIO_IPCR                  0x00430000    /* IO Performance Control */
-#define    IIO_IPPR                  0x00430008    /* IO Performance Profiling */
-
-
-/************************************************************************
- *                                                                      *
+#define HUB_WIDGET_ID_MAX      0xf
+#define IIO_NUM_ITTES          7
+#define HUB_NUM_BIG_WINDOW     (IIO_NUM_ITTES - 1)
+
+#define                IIO_WID                 0x00400000      /* Crosstalk Widget Identification */
+                                                       /* This register is also accessible from
+                                                        * Crosstalk at address 0x0.  */
+#define                IIO_WSTAT               0x00400008      /* Crosstalk Widget Status */
+#define                IIO_WCR                 0x00400020      /* Crosstalk Widget Control Register */
+#define                IIO_ILAPR               0x00400100      /* IO Local Access Protection Register */
+#define                IIO_ILAPO               0x00400108      /* IO Local Access Protection Override */
+#define                IIO_IOWA                0x00400110      /* IO Outbound Widget Access */
+#define                IIO_IIWA                0x00400118      /* IO Inbound Widget Access */
+#define                IIO_IIDEM               0x00400120      /* IO Inbound Device Error Mask */
+#define                IIO_ILCSR               0x00400128      /* IO LLP Control and Status Register */
+#define                IIO_ILLR                0x00400130      /* IO LLP Log Register    */
+#define                IIO_IIDSR               0x00400138      /* IO Interrupt Destination */
+
+#define                IIO_IGFX0               0x00400140      /* IO Graphics Node-Widget Map 0 */
+#define                IIO_IGFX1               0x00400148      /* IO Graphics Node-Widget Map 1 */
+
+#define                IIO_ISCR0               0x00400150      /* IO Scratch Register 0 */
+#define                IIO_ISCR1               0x00400158      /* IO Scratch Register 1 */
+
+#define                IIO_ITTE1               0x00400160      /* IO Translation Table Entry 1 */
+#define                IIO_ITTE2               0x00400168      /* IO Translation Table Entry 2 */
+#define                IIO_ITTE3               0x00400170      /* IO Translation Table Entry 3 */
+#define                IIO_ITTE4               0x00400178      /* IO Translation Table Entry 4 */
+#define                IIO_ITTE5               0x00400180      /* IO Translation Table Entry 5 */
+#define                IIO_ITTE6               0x00400188      /* IO Translation Table Entry 6 */
+#define                IIO_ITTE7               0x00400190      /* IO Translation Table Entry 7 */
+
+#define                IIO_IPRB0               0x00400198      /* IO PRB Entry 0   */
+#define                IIO_IPRB8               0x004001A0      /* IO PRB Entry 8   */
+#define                IIO_IPRB9               0x004001A8      /* IO PRB Entry 9   */
+#define                IIO_IPRBA               0x004001B0      /* IO PRB Entry A   */
+#define                IIO_IPRBB               0x004001B8      /* IO PRB Entry B   */
+#define                IIO_IPRBC               0x004001C0      /* IO PRB Entry C   */
+#define                IIO_IPRBD               0x004001C8      /* IO PRB Entry D   */
+#define                IIO_IPRBE               0x004001D0      /* IO PRB Entry E   */
+#define                IIO_IPRBF               0x004001D8      /* IO PRB Entry F   */
+
+#define                IIO_IXCC                0x004001E0      /* IO Crosstalk Credit Count Timeout */
+#define                IIO_IMEM                0x004001E8      /* IO Miscellaneous Error Mask */
+#define                IIO_IXTT                0x004001F0      /* IO Crosstalk Timeout Threshold */
+#define                IIO_IECLR               0x004001F8      /* IO Error Clear Register */
+#define                IIO_IBCR                0x00400200      /* IO BTE Control Register */
+
+#define                IIO_IXSM                0x00400208      /* IO Crosstalk Spurious Message */
+#define                IIO_IXSS                0x00400210      /* IO Crosstalk Spurious Sideband */
+
+#define                IIO_ILCT                0x00400218      /* IO LLP Channel Test    */
+
+#define                IIO_IIEPH1              0x00400220      /* IO Incoming Error Packet Header, Part 1 */
+#define                IIO_IIEPH2              0x00400228      /* IO Incoming Error Packet Header, Part 2 */
+
+#define                IIO_ISLAPR              0x00400230      /* IO SXB Local Access Protection Regster */
+#define                IIO_ISLAPO              0x00400238      /* IO SXB Local Access Protection Override */
+
+#define                IIO_IWI                 0x00400240      /* IO Wrapper Interrupt Register */
+#define                IIO_IWEL                0x00400248      /* IO Wrapper Error Log Register */
+#define                IIO_IWC                 0x00400250      /* IO Wrapper Control Register */
+#define                IIO_IWS                 0x00400258      /* IO Wrapper Status Register */
+#define                IIO_IWEIM               0x00400260      /* IO Wrapper Error Interrupt Masking Register */
+
+#define                IIO_IPCA                0x00400300      /* IO PRB Counter Adjust */
+
+#define                IIO_IPRTE0_A            0x00400308      /* IO PIO Read Address Table Entry 0, Part A */
+#define                IIO_IPRTE1_A            0x00400310      /* IO PIO Read Address Table Entry 1, Part A */
+#define                IIO_IPRTE2_A            0x00400318      /* IO PIO Read Address Table Entry 2, Part A */
+#define                IIO_IPRTE3_A            0x00400320      /* IO PIO Read Address Table Entry 3, Part A */
+#define                IIO_IPRTE4_A            0x00400328      /* IO PIO Read Address Table Entry 4, Part A */
+#define                IIO_IPRTE5_A            0x00400330      /* IO PIO Read Address Table Entry 5, Part A */
+#define                IIO_IPRTE6_A            0x00400338      /* IO PIO Read Address Table Entry 6, Part A */
+#define                IIO_IPRTE7_A            0x00400340      /* IO PIO Read Address Table Entry 7, Part A */
+
+#define                IIO_IPRTE0_B            0x00400348      /* IO PIO Read Address Table Entry 0, Part B */
+#define                IIO_IPRTE1_B            0x00400350      /* IO PIO Read Address Table Entry 1, Part B */
+#define                IIO_IPRTE2_B            0x00400358      /* IO PIO Read Address Table Entry 2, Part B */
+#define                IIO_IPRTE3_B            0x00400360      /* IO PIO Read Address Table Entry 3, Part B */
+#define                IIO_IPRTE4_B            0x00400368      /* IO PIO Read Address Table Entry 4, Part B */
+#define                IIO_IPRTE5_B            0x00400370      /* IO PIO Read Address Table Entry 5, Part B */
+#define                IIO_IPRTE6_B            0x00400378      /* IO PIO Read Address Table Entry 6, Part B */
+#define                IIO_IPRTE7_B            0x00400380      /* IO PIO Read Address Table Entry 7, Part B */
+
+#define                IIO_IPDR                0x00400388      /* IO PIO Deallocation Register */
+#define                IIO_ICDR                0x00400390      /* IO CRB Entry Deallocation Register */
+#define                IIO_IFDR                0x00400398      /* IO IOQ FIFO Depth Register */
+#define                IIO_IIAP                0x004003A0      /* IO IIQ Arbitration Parameters */
+#define                IIO_ICMR                0x004003A8      /* IO CRB Management Register */
+#define                IIO_ICCR                0x004003B0      /* IO CRB Control Register */
+#define                IIO_ICTO                0x004003B8      /* IO CRB Timeout   */
+#define                IIO_ICTP                0x004003C0      /* IO CRB Timeout Prescalar */
+
+#define                IIO_ICRB0_A             0x00400400      /* IO CRB Entry 0_A */
+#define                IIO_ICRB0_B             0x00400408      /* IO CRB Entry 0_B */
+#define                IIO_ICRB0_C             0x00400410      /* IO CRB Entry 0_C */
+#define                IIO_ICRB0_D             0x00400418      /* IO CRB Entry 0_D */
+#define                IIO_ICRB0_E             0x00400420      /* IO CRB Entry 0_E */
+
+#define                IIO_ICRB1_A             0x00400430      /* IO CRB Entry 1_A */
+#define                IIO_ICRB1_B             0x00400438      /* IO CRB Entry 1_B */
+#define                IIO_ICRB1_C             0x00400440      /* IO CRB Entry 1_C */
+#define                IIO_ICRB1_D             0x00400448      /* IO CRB Entry 1_D */
+#define                IIO_ICRB1_E             0x00400450      /* IO CRB Entry 1_E */
+
+#define                IIO_ICRB2_A             0x00400460      /* IO CRB Entry 2_A */
+#define                IIO_ICRB2_B             0x00400468      /* IO CRB Entry 2_B */
+#define                IIO_ICRB2_C             0x00400470      /* IO CRB Entry 2_C */
+#define                IIO_ICRB2_D             0x00400478      /* IO CRB Entry 2_D */
+#define                IIO_ICRB2_E             0x00400480      /* IO CRB Entry 2_E */
+
+#define                IIO_ICRB3_A             0x00400490      /* IO CRB Entry 3_A */
+#define                IIO_ICRB3_B             0x00400498      /* IO CRB Entry 3_B */
+#define                IIO_ICRB3_C             0x004004a0      /* IO CRB Entry 3_C */
+#define                IIO_ICRB3_D             0x004004a8      /* IO CRB Entry 3_D */
+#define                IIO_ICRB3_E             0x004004b0      /* IO CRB Entry 3_E */
+
+#define                IIO_ICRB4_A             0x004004c0      /* IO CRB Entry 4_A */
+#define                IIO_ICRB4_B             0x004004c8      /* IO CRB Entry 4_B */
+#define                IIO_ICRB4_C             0x004004d0      /* IO CRB Entry 4_C */
+#define                IIO_ICRB4_D             0x004004d8      /* IO CRB Entry 4_D */
+#define                IIO_ICRB4_E             0x004004e0      /* IO CRB Entry 4_E */
+
+#define                IIO_ICRB5_A             0x004004f0      /* IO CRB Entry 5_A */
+#define                IIO_ICRB5_B             0x004004f8      /* IO CRB Entry 5_B */
+#define                IIO_ICRB5_C             0x00400500      /* IO CRB Entry 5_C */
+#define                IIO_ICRB5_D             0x00400508      /* IO CRB Entry 5_D */
+#define                IIO_ICRB5_E             0x00400510      /* IO CRB Entry 5_E */
+
+#define                IIO_ICRB6_A             0x00400520      /* IO CRB Entry 6_A */
+#define                IIO_ICRB6_B             0x00400528      /* IO CRB Entry 6_B */
+#define                IIO_ICRB6_C             0x00400530      /* IO CRB Entry 6_C */
+#define                IIO_ICRB6_D             0x00400538      /* IO CRB Entry 6_D */
+#define                IIO_ICRB6_E             0x00400540      /* IO CRB Entry 6_E */
+
+#define                IIO_ICRB7_A             0x00400550      /* IO CRB Entry 7_A */
+#define                IIO_ICRB7_B             0x00400558      /* IO CRB Entry 7_B */
+#define                IIO_ICRB7_C             0x00400560      /* IO CRB Entry 7_C */
+#define                IIO_ICRB7_D             0x00400568      /* IO CRB Entry 7_D */
+#define                IIO_ICRB7_E             0x00400570      /* IO CRB Entry 7_E */
+
+#define                IIO_ICRB8_A             0x00400580      /* IO CRB Entry 8_A */
+#define                IIO_ICRB8_B             0x00400588      /* IO CRB Entry 8_B */
+#define                IIO_ICRB8_C             0x00400590      /* IO CRB Entry 8_C */
+#define                IIO_ICRB8_D             0x00400598      /* IO CRB Entry 8_D */
+#define                IIO_ICRB8_E             0x004005a0      /* IO CRB Entry 8_E */
+
+#define                IIO_ICRB9_A             0x004005b0      /* IO CRB Entry 9_A */
+#define                IIO_ICRB9_B             0x004005b8      /* IO CRB Entry 9_B */
+#define                IIO_ICRB9_C             0x004005c0      /* IO CRB Entry 9_C */
+#define                IIO_ICRB9_D             0x004005c8      /* IO CRB Entry 9_D */
+#define                IIO_ICRB9_E             0x004005d0      /* IO CRB Entry 9_E */
+
+#define                IIO_ICRBA_A             0x004005e0      /* IO CRB Entry A_A */
+#define                IIO_ICRBA_B             0x004005e8      /* IO CRB Entry A_B */
+#define                IIO_ICRBA_C             0x004005f0      /* IO CRB Entry A_C */
+#define                IIO_ICRBA_D             0x004005f8      /* IO CRB Entry A_D */
+#define                IIO_ICRBA_E             0x00400600      /* IO CRB Entry A_E */
+
+#define                IIO_ICRBB_A             0x00400610      /* IO CRB Entry B_A */
+#define                IIO_ICRBB_B             0x00400618      /* IO CRB Entry B_B */
+#define                IIO_ICRBB_C             0x00400620      /* IO CRB Entry B_C */
+#define                IIO_ICRBB_D             0x00400628      /* IO CRB Entry B_D */
+#define                IIO_ICRBB_E             0x00400630      /* IO CRB Entry B_E */
+
+#define                IIO_ICRBC_A             0x00400640      /* IO CRB Entry C_A */
+#define                IIO_ICRBC_B             0x00400648      /* IO CRB Entry C_B */
+#define                IIO_ICRBC_C             0x00400650      /* IO CRB Entry C_C */
+#define                IIO_ICRBC_D             0x00400658      /* IO CRB Entry C_D */
+#define                IIO_ICRBC_E             0x00400660      /* IO CRB Entry C_E */
+
+#define                IIO_ICRBD_A             0x00400670      /* IO CRB Entry D_A */
+#define                IIO_ICRBD_B             0x00400678      /* IO CRB Entry D_B */
+#define                IIO_ICRBD_C             0x00400680      /* IO CRB Entry D_C */
+#define                IIO_ICRBD_D             0x00400688      /* IO CRB Entry D_D */
+#define                IIO_ICRBD_E             0x00400690      /* IO CRB Entry D_E */
+
+#define                IIO_ICRBE_A             0x004006a0      /* IO CRB Entry E_A */
+#define                IIO_ICRBE_B             0x004006a8      /* IO CRB Entry E_B */
+#define                IIO_ICRBE_C             0x004006b0      /* IO CRB Entry E_C */
+#define                IIO_ICRBE_D             0x004006b8      /* IO CRB Entry E_D */
+#define                IIO_ICRBE_E             0x004006c0      /* IO CRB Entry E_E */
+
+#define                IIO_ICSML               0x00400700      /* IO CRB Spurious Message Low */
+#define                IIO_ICSMM               0x00400708      /* IO CRB Spurious Message Middle */
+#define                IIO_ICSMH               0x00400710      /* IO CRB Spurious Message High */
+
+#define                IIO_IDBSS               0x00400718      /* IO Debug Submenu Select */
+
+#define                IIO_IBLS0               0x00410000      /* IO BTE Length Status 0 */
+#define                IIO_IBSA0               0x00410008      /* IO BTE Source Address 0 */
+#define                IIO_IBDA0               0x00410010      /* IO BTE Destination Address 0 */
+#define                IIO_IBCT0               0x00410018      /* IO BTE Control Terminate 0 */
+#define                IIO_IBNA0               0x00410020      /* IO BTE Notification Address 0 */
+#define                IIO_IBIA0               0x00410028      /* IO BTE Interrupt Address 0 */
+#define                IIO_IBLS1               0x00420000      /* IO BTE Length Status 1 */
+#define                IIO_IBSA1               0x00420008      /* IO BTE Source Address 1 */
+#define                IIO_IBDA1               0x00420010      /* IO BTE Destination Address 1 */
+#define                IIO_IBCT1               0x00420018      /* IO BTE Control Terminate 1 */
+#define                IIO_IBNA1               0x00420020      /* IO BTE Notification Address 1 */
+#define                IIO_IBIA1               0x00420028      /* IO BTE Interrupt Address 1 */
+
+#define                IIO_IPCR                0x00430000      /* IO Performance Control */
+#define                IIO_IPPR                0x00430008      /* IO Performance Profiling */
+
+/************************************************************************
+ *                                                                     *

  * Description:  This register echoes some information from the         *
  * LB_REV_ID register. It is available through Crosstalk as described   *
  * above. The REV_NUM and MFG_NUM fields receive their values from      *
  * the REVISION and MANUFACTURER fields in the LB_REV_ID register.      *
  * The PART_NUM field's value is the Crosstalk device ID number that    *
  * Steve Miller assigned to the SHub chip.                              *
  * Description:  This register echoes some information from the         *
  * LB_REV_ID register. It is available through Crosstalk as described   *
  * above. The REV_NUM and MFG_NUM fields receive their values from      *
  * the REVISION and MANUFACTURER fields in the LB_REV_ID register.      *
  * The PART_NUM field's value is the Crosstalk device ID number that    *
  * Steve Miller assigned to the SHub chip.                              *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_wid_u {
  ************************************************************************/
 
 typedef union ii_wid_u {

-       uint64_t        ii_wid_regval;
-       struct  {
-               uint64_t        w_rsvd_1                  :      1;
-               uint64_t        w_mfg_num                 :     11;
-               uint64_t        w_part_num                :     16;
-               uint64_t        w_rev_num                 :      4;
-               uint64_t        w_rsvd                    :     32;
+       uint64_t ii_wid_regval;
+       struct {
+               uint64_t w_rsvd_1:1;
+               uint64_t w_mfg_num:11;
+               uint64_t w_part_num:16;
+               uint64_t w_rev_num:4;
+               uint64_t w_rsvd:32;

        } ii_wid_fld_s;
 } ii_wid_u_t;
 
        } ii_wid_fld_s;
 } ii_wid_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  The fields in this register are set upon detection of an error      *
  * and cleared by various mechanisms, as explained in the               *
  * description.                                                         *
  *  The fields in this register are set upon detection of an error      *
  * and cleared by various mechanisms, as explained in the               *
  * description.                                                         *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_wstat_u {
  ************************************************************************/
 
 typedef union ii_wstat_u {

-       uint64_t        ii_wstat_regval;
-       struct  {
-               uint64_t        w_pending                 :      4;
-               uint64_t        w_xt_crd_to               :      1;
-               uint64_t        w_xt_tail_to              :      1;
-               uint64_t        w_rsvd_3                  :      3;
-               uint64_t       w_tx_mx_rty               :      1;
-               uint64_t        w_rsvd_2                  :      6;
-               uint64_t        w_llp_tx_cnt              :      8;
-               uint64_t        w_rsvd_1                  :      8;
-               uint64_t        w_crazy                   :      1;
-               uint64_t        w_rsvd                    :     31;
+       uint64_t ii_wstat_regval;
+       struct {
+               uint64_t w_pending:4;
+               uint64_t w_xt_crd_to:1;
+               uint64_t w_xt_tail_to:1;
+               uint64_t w_rsvd_3:3;
+               uint64_t w_tx_mx_rty:1;
+               uint64_t w_rsvd_2:6;
+               uint64_t w_llp_tx_cnt:8;
+               uint64_t w_rsvd_1:8;
+               uint64_t w_crazy:1;
+               uint64_t w_rsvd:31;

        } ii_wstat_fld_s;
 } ii_wstat_u_t;
 
        } ii_wstat_fld_s;
 } ii_wstat_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  This is a read-write enabled register. It controls     *
  * various aspects of the Crosstalk flow control.                       *
  * Description:  This is a read-write enabled register. It controls     *
  * various aspects of the Crosstalk flow control.                       *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_wcr_u {
  ************************************************************************/
 
 typedef union ii_wcr_u {

-       uint64_t        ii_wcr_regval;
-       struct  {
-               uint64_t        w_wid                     :      4;
-               uint64_t        w_tag                     :      1;
-               uint64_t        w_rsvd_1                  :      8;
-               uint64_t        w_dst_crd                 :      3;
-               uint64_t        w_f_bad_pkt               :      1;
-               uint64_t        w_dir_con                 :      1;
-               uint64_t        w_e_thresh                :      5;
-               uint64_t        w_rsvd                    :     41;
+       uint64_t ii_wcr_regval;
+       struct {
+               uint64_t w_wid:4;
+               uint64_t w_tag:1;
+               uint64_t w_rsvd_1:8;
+               uint64_t w_dst_crd:3;
+               uint64_t w_f_bad_pkt:1;
+               uint64_t w_dir_con:1;
+               uint64_t w_e_thresh:5;
+               uint64_t w_rsvd:41;

        } ii_wcr_fld_s;
 } ii_wcr_u_t;
 
        } ii_wcr_fld_s;
 } ii_wcr_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  This register's value is a bit vector that guards      *
  * access to local registers within the II as well as to external       *
  * Crosstalk widgets. Each bit in the register corresponds to a         *
  * Description:  This register's value is a bit vector that guards      *
  * access to local registers within the II as well as to external       *
  * Crosstalk widgets. Each bit in the register corresponds to a         *


@@ -311,21 +306,18 @@ typedef union ii_wcr_u {
  * region ID bits are enabled in this same register. It can also be     *
  * accessed through the IAlias space by the local processors.           *
  * The reset value of this register allows access by all nodes.         *
  * region ID bits are enabled in this same register. It can also be     *
  * accessed through the IAlias space by the local processors.           *
  * The reset value of this register allows access by all nodes.         *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ilapr_u {
  ************************************************************************/
 
 typedef union ii_ilapr_u {

-       uint64_t        ii_ilapr_regval;
-       struct  {
-               uint64_t        i_region                  :     64;
+       uint64_t ii_ilapr_regval;
+       struct {
+               uint64_t i_region:64;

        } ii_ilapr_fld_s;
 } ii_ilapr_u_t;
 
        } ii_ilapr_fld_s;
 } ii_ilapr_u_t;
 

-
-
-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  A write to this register of the 64-bit value           *
  * "SGIrules" in ASCII, will cause the bit in the ILAPR register        *
  * corresponding to the region of the requestor to be set (allow        *
  * Description:  A write to this register of the 64-bit value           *
  * "SGIrules" in ASCII, will cause the bit in the ILAPR register        *
  * corresponding to the region of the requestor to be set (allow        *


@@ -334,59 +326,54 @@ typedef union ii_ilapr_u {
  * This register can also be accessed through the IAlias space.         *
  * However, this access will not change the access permissions in the   *
  * ILAPR.                                                               *
  * This register can also be accessed through the IAlias space.         *
  * However, this access will not change the access permissions in the   *
  * ILAPR.                                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ilapo_u {
  ************************************************************************/
 
 typedef union ii_ilapo_u {

-       uint64_t        ii_ilapo_regval;
-       struct  {
-               uint64_t        i_io_ovrride            :       64;
+       uint64_t ii_ilapo_regval;
+       struct {
+               uint64_t i_io_ovrride:64;

        } ii_ilapo_fld_s;
 } ii_ilapo_u_t;
 
        } ii_ilapo_fld_s;
 } ii_ilapo_u_t;
 

-
-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register qualifies all the PIO and Graphics writes launched    *
  * from the SHUB towards a widget.                                      *
  *  This register qualifies all the PIO and Graphics writes launched    *
  * from the SHUB towards a widget.                                      *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iowa_u {
  ************************************************************************/
 
 typedef union ii_iowa_u {

-       uint64_t        ii_iowa_regval;
-       struct  {
-               uint64_t        i_w0_oac                  :      1;
-               uint64_t        i_rsvd_1                  :      7;
-                uint64_t       i_wx_oac                  :      8;
-               uint64_t        i_rsvd                    :     48;
+       uint64_t ii_iowa_regval;
+       struct {
+               uint64_t i_w0_oac:1;
+               uint64_t i_rsvd_1:7;
+               uint64_t i_wx_oac:8;
+               uint64_t i_rsvd:48;

        } ii_iowa_fld_s;
 } ii_iowa_u_t;
 
        } ii_iowa_fld_s;
 } ii_iowa_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  This register qualifies all the requests launched      *
  * from a widget towards the Shub. This register is intended to be      *
  * used by software in case of misbehaving widgets.                     *
  * Description:  This register qualifies all the requests launched      *
  * from a widget towards the Shub. This register is intended to be      *
  * used by software in case of misbehaving widgets.                     *

- *                                                                      *
- *                                                                      *
+ *                                                                     *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iiwa_u {
  ************************************************************************/
 
 typedef union ii_iiwa_u {

-       uint64_t        ii_iiwa_regval;
-       struct  {
-               uint64_t        i_w0_iac                  :      1;
-               uint64_t        i_rsvd_1                  :      7;
-               uint64_t        i_wx_iac                  :      8;
-               uint64_t        i_rsvd                    :     48;
+       uint64_t ii_iiwa_regval;
+       struct {
+               uint64_t i_w0_iac:1;
+               uint64_t i_rsvd_1:7;
+               uint64_t i_wx_iac:8;
+               uint64_t i_rsvd:48;

        } ii_iiwa_fld_s;
 } ii_iiwa_u_t;
 
        } ii_iiwa_fld_s;
 } ii_iiwa_u_t;
 

-
-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  This register qualifies all the operations launched    *
  * from a widget towards the SHub. It allows individual access          *
  * control for up to 8 devices per widget. A device refers to           *
  * Description:  This register qualifies all the operations launched    *
  * from a widget towards the SHub. It allows individual access          *
  * control for up to 8 devices per widget. A device refers to           *


@@ -401,72 +388,69 @@ typedef union ii_iiwa_u {
  * The bits in this field are set by writing a 1 to them. Incoming      *
  * replies from Crosstalk are not subject to this access control        *
  * mechanism.                                                           *
  * The bits in this field are set by writing a 1 to them. Incoming      *
  * replies from Crosstalk are not subject to this access control        *
  * mechanism.                                                           *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iidem_u {
  ************************************************************************/
 
 typedef union ii_iidem_u {

-       uint64_t        ii_iidem_regval;
-       struct  {
-               uint64_t        i_w8_dxs                  :      8;
-               uint64_t        i_w9_dxs                  :      8;
-               uint64_t        i_wa_dxs                  :      8;
-               uint64_t        i_wb_dxs                  :      8;
-               uint64_t        i_wc_dxs                  :      8;
-               uint64_t        i_wd_dxs                  :      8;
-               uint64_t        i_we_dxs                  :      8;
-               uint64_t        i_wf_dxs                  :      8;
+       uint64_t ii_iidem_regval;
+       struct {
+               uint64_t i_w8_dxs:8;
+               uint64_t i_w9_dxs:8;
+               uint64_t i_wa_dxs:8;
+               uint64_t i_wb_dxs:8;
+               uint64_t i_wc_dxs:8;
+               uint64_t i_wd_dxs:8;
+               uint64_t i_we_dxs:8;
+               uint64_t i_wf_dxs:8;

        } ii_iidem_fld_s;
 } ii_iidem_u_t;
 
        } ii_iidem_fld_s;
 } ii_iidem_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register contains the various programmable fields necessary    *
  * for controlling and observing the LLP signals.                       *
  *  This register contains the various programmable fields necessary    *
  * for controlling and observing the LLP signals.                       *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ilcsr_u {
  ************************************************************************/
 
 typedef union ii_ilcsr_u {

-       uint64_t        ii_ilcsr_regval;
-       struct  {
-               uint64_t        i_nullto                  :      6;
-               uint64_t        i_rsvd_4                  :      2;
-               uint64_t        i_wrmrst                  :      1;
-               uint64_t        i_rsvd_3                  :      1;
-               uint64_t        i_llp_en                  :      1;
-               uint64_t        i_bm8                     :      1;
-               uint64_t        i_llp_stat                :      2;
-               uint64_t        i_remote_power            :      1;
-               uint64_t        i_rsvd_2                  :      1;
-               uint64_t        i_maxrtry                 :     10;
-               uint64_t        i_d_avail_sel             :      2;
-               uint64_t        i_rsvd_1                  :      4;
-               uint64_t        i_maxbrst                 :     10;
-                uint64_t       i_rsvd                    :     22;
+       uint64_t ii_ilcsr_regval;
+       struct {
+               uint64_t i_nullto:6;
+               uint64_t i_rsvd_4:2;
+               uint64_t i_wrmrst:1;
+               uint64_t i_rsvd_3:1;
+               uint64_t i_llp_en:1;
+               uint64_t i_bm8:1;
+               uint64_t i_llp_stat:2;
+               uint64_t i_remote_power:1;
+               uint64_t i_rsvd_2:1;
+               uint64_t i_maxrtry:10;
+               uint64_t i_d_avail_sel:2;
+               uint64_t i_rsvd_1:4;
+               uint64_t i_maxbrst:10;
+               uint64_t i_rsvd:22;

 
        } ii_ilcsr_fld_s;
 } ii_ilcsr_u_t;
 
 
        } ii_ilcsr_fld_s;
 } ii_ilcsr_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This is simply a status registers that monitors the LLP error       *
  *  This is simply a status registers that monitors the LLP error       *

- * rate.                                                                *
- *                                                                      *
+ * rate.                                                               *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_illr_u {
  ************************************************************************/
 
 typedef union ii_illr_u {

-       uint64_t        ii_illr_regval;
-       struct  {
-               uint64_t        i_sn_cnt                  :     16;
-               uint64_t        i_cb_cnt                  :     16;
-               uint64_t        i_rsvd                    :     32;
+       uint64_t ii_illr_regval;
+       struct {
+               uint64_t i_sn_cnt:16;
+               uint64_t i_cb_cnt:16;
+               uint64_t i_rsvd:32;

        } ii_illr_fld_s;
 } ii_illr_u_t;
 
        } ii_illr_fld_s;
 } ii_illr_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  All II-detected non-BTE error interrupts are           *
  * specified via this register.                                         *
  * NOTE: The PI interrupt register address is hardcoded in the II. If   *
  * Description:  All II-detected non-BTE error interrupts are           *
  * specified via this register.                                         *
  * NOTE: The PI interrupt register address is hardcoded in the II. If   *


@@ -476,107 +460,100 @@ typedef union ii_illr_u {
  * PI_ID==1, then the II sends the interrupt request to address         *
  * offset 0x01A0_0090 within the local register address space of PI1    *
  * on the node specified by the NODE field.                             *
  * PI_ID==1, then the II sends the interrupt request to address         *
  * offset 0x01A0_0090 within the local register address space of PI1    *
  * on the node specified by the NODE field.                             *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iidsr_u {
  ************************************************************************/
 
 typedef union ii_iidsr_u {

-       uint64_t        ii_iidsr_regval;
-       struct  {
-               uint64_t        i_level                   :      8;
-               uint64_t        i_pi_id                   :      1;
-               uint64_t        i_node                    :     11;
-               uint64_t       i_rsvd_3                  :      4;
-               uint64_t        i_enable                  :      1;
-               uint64_t        i_rsvd_2                  :      3;
-               uint64_t        i_int_sent                :      2;
-               uint64_t       i_rsvd_1                  :      2;
-               uint64_t        i_pi0_forward_int         :      1;
-               uint64_t        i_pi1_forward_int         :      1;
-               uint64_t        i_rsvd                    :     30;
+       uint64_t ii_iidsr_regval;
+       struct {
+               uint64_t i_level:8;
+               uint64_t i_pi_id:1;
+               uint64_t i_node:11;
+               uint64_t i_rsvd_3:4;
+               uint64_t i_enable:1;
+               uint64_t i_rsvd_2:3;
+               uint64_t i_int_sent:2;
+               uint64_t i_rsvd_1:2;
+               uint64_t i_pi0_forward_int:1;
+               uint64_t i_pi1_forward_int:1;
+               uint64_t i_rsvd:30;

        } ii_iidsr_fld_s;
 } ii_iidsr_u_t;
 
        } ii_iidsr_fld_s;
 } ii_iidsr_u_t;
 

-
-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are two instances of this register. This register is used     *
  * for matching up the incoming responses from the graphics widget to   *
  * the processor that initiated the graphics operation. The             *
  * write-responses are converted to graphics credits and returned to    *
  * the processor so that the processor interface can manage the flow    *
  * control.                                                             *
  *  There are two instances of this register. This register is used     *
  * for matching up the incoming responses from the graphics widget to   *
  * the processor that initiated the graphics operation. The             *
  * write-responses are converted to graphics credits and returned to    *
  * the processor so that the processor interface can manage the flow    *
  * control.                                                             *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_igfx0_u {
  ************************************************************************/
 
 typedef union ii_igfx0_u {

-       uint64_t        ii_igfx0_regval;
-       struct  {
-               uint64_t        i_w_num                   :      4;
-               uint64_t       i_pi_id                   :      1;
-               uint64_t        i_n_num                   :     12;
-               uint64_t       i_p_num                   :      1;
-               uint64_t       i_rsvd                    :     46;
+       uint64_t ii_igfx0_regval;
+       struct {
+               uint64_t i_w_num:4;
+               uint64_t i_pi_id:1;
+               uint64_t i_n_num:12;
+               uint64_t i_p_num:1;
+               uint64_t i_rsvd:46;

        } ii_igfx0_fld_s;
 } ii_igfx0_u_t;
 
        } ii_igfx0_fld_s;
 } ii_igfx0_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are two instances of this register. This register is used     *
  * for matching up the incoming responses from the graphics widget to   *
  * the processor that initiated the graphics operation. The             *
  * write-responses are converted to graphics credits and returned to    *
  * the processor so that the processor interface can manage the flow    *
  * control.                                                             *
  *  There are two instances of this register. This register is used     *
  * for matching up the incoming responses from the graphics widget to   *
  * the processor that initiated the graphics operation. The             *
  * write-responses are converted to graphics credits and returned to    *
  * the processor so that the processor interface can manage the flow    *
  * control.                                                             *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_igfx1_u {
  ************************************************************************/
 
 typedef union ii_igfx1_u {

-       uint64_t        ii_igfx1_regval;
-       struct  {
-               uint64_t        i_w_num                   :      4;
-               uint64_t       i_pi_id                   :      1;
-               uint64_t        i_n_num                   :     12;
-               uint64_t       i_p_num                   :      1;
-               uint64_t       i_rsvd                    :     46;
+       uint64_t ii_igfx1_regval;
+       struct {
+               uint64_t i_w_num:4;
+               uint64_t i_pi_id:1;
+               uint64_t i_n_num:12;
+               uint64_t i_p_num:1;
+               uint64_t i_rsvd:46;

        } ii_igfx1_fld_s;
 } ii_igfx1_u_t;
 
        } ii_igfx1_fld_s;
 } ii_igfx1_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are two instances of this registers. These registers are      *
  * used as scratch registers for software use.                          *
  *  There are two instances of this registers. These registers are      *
  * used as scratch registers for software use.                          *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iscr0_u {
  ************************************************************************/
 
 typedef union ii_iscr0_u {

-       uint64_t        ii_iscr0_regval;
-       struct  {
-               uint64_t        i_scratch                 :     64;
+       uint64_t ii_iscr0_regval;
+       struct {
+               uint64_t i_scratch:64;

        } ii_iscr0_fld_s;
 } ii_iscr0_u_t;
 
        } ii_iscr0_fld_s;
 } ii_iscr0_u_t;
 

-
-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are two instances of this registers. These registers are      *
  * used as scratch registers for software use.                          *
  *  There are two instances of this registers. These registers are      *
  * used as scratch registers for software use.                          *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iscr1_u {
  ************************************************************************/
 
 typedef union ii_iscr1_u {

-       uint64_t        ii_iscr1_regval;
-       struct  {
-               uint64_t        i_scratch                 :     64;
+       uint64_t ii_iscr1_regval;
+       struct {
+               uint64_t i_scratch:64;

        } ii_iscr1_fld_s;
 } ii_iscr1_u_t;
 
        } ii_iscr1_fld_s;
 } ii_iscr1_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *
  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *


@@ -599,23 +576,22 @@ typedef union ii_iscr1_u {
  * Crosstalk space addressable by the Shub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *
  * Crosstalk space addressable by the Shub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_itte1_u {
  ************************************************************************/
 
 typedef union ii_itte1_u {

-       uint64_t        ii_itte1_regval;
-       struct  {
-               uint64_t        i_offset                  :      5;
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_w_num                   :      4;
-               uint64_t        i_iosp                    :      1;
-               uint64_t        i_rsvd                    :     51;
+       uint64_t ii_itte1_regval;
+       struct {
+               uint64_t i_offset:5;
+               uint64_t i_rsvd_1:3;
+               uint64_t i_w_num:4;
+               uint64_t i_iosp:1;
+               uint64_t i_rsvd:51;

        } ii_itte1_fld_s;
 } ii_itte1_u_t;
 
        } ii_itte1_fld_s;
 } ii_itte1_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *
  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *


@@ -638,23 +614,22 @@ typedef union ii_itte1_u {
  * Crosstalk space addressable by the Shub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *
  * Crosstalk space addressable by the Shub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_itte2_u {
  ************************************************************************/
 
 typedef union ii_itte2_u {

-       uint64_t        ii_itte2_regval;
-       struct  {
-               uint64_t        i_offset                  :      5;
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_w_num                   :      4;
-               uint64_t        i_iosp                    :      1;
-               uint64_t       i_rsvd                    :     51;
+       uint64_t ii_itte2_regval;
+       struct {
+               uint64_t i_offset:5;
+               uint64_t i_rsvd_1:3;
+               uint64_t i_w_num:4;
+               uint64_t i_iosp:1;
+               uint64_t i_rsvd:51;

        } ii_itte2_fld_s;
 } ii_itte2_u_t;
 
        } ii_itte2_fld_s;
 } ii_itte2_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *
  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *


@@ -677,23 +652,22 @@ typedef union ii_itte2_u {
  * Crosstalk space addressable by the SHub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *
  * Crosstalk space addressable by the SHub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_itte3_u {
  ************************************************************************/
 
 typedef union ii_itte3_u {

-       uint64_t        ii_itte3_regval;
-       struct  {
-               uint64_t        i_offset                  :      5;
-               uint64_t       i_rsvd_1                  :      3;
-               uint64_t       i_w_num                   :      4;
-               uint64_t       i_iosp                    :      1;
-               uint64_t       i_rsvd                    :     51;
+       uint64_t ii_itte3_regval;
+       struct {
+               uint64_t i_offset:5;
+               uint64_t i_rsvd_1:3;
+               uint64_t i_w_num:4;
+               uint64_t i_iosp:1;
+               uint64_t i_rsvd:51;

        } ii_itte3_fld_s;
 } ii_itte3_u_t;
 
        } ii_itte3_fld_s;
 } ii_itte3_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a SHub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *
  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a SHub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *


@@ -716,23 +690,22 @@ typedef union ii_itte3_u {
  * Crosstalk space addressable by the SHub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *
  * Crosstalk space addressable by the SHub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_itte4_u {
  ************************************************************************/
 
 typedef union ii_itte4_u {

-       uint64_t        ii_itte4_regval;
-       struct  {
-               uint64_t        i_offset                  :      5;
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t       i_w_num                   :      4;
-               uint64_t       i_iosp                    :      1;
-               uint64_t       i_rsvd                    :     51;
+       uint64_t ii_itte4_regval;
+       struct {
+               uint64_t i_offset:5;
+               uint64_t i_rsvd_1:3;
+               uint64_t i_w_num:4;
+               uint64_t i_iosp:1;
+               uint64_t i_rsvd:51;

        } ii_itte4_fld_s;
 } ii_itte4_u_t;
 
        } ii_itte4_fld_s;
 } ii_itte4_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a SHub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *
  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a SHub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *


@@ -755,23 +728,22 @@ typedef union ii_itte4_u {
  * Crosstalk space addressable by the Shub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *
  * Crosstalk space addressable by the Shub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_itte5_u {
  ************************************************************************/
 
 typedef union ii_itte5_u {

-       uint64_t        ii_itte5_regval;
-       struct  {
-               uint64_t        i_offset                  :      5;
-               uint64_t       i_rsvd_1                  :      3;
-               uint64_t       i_w_num                   :      4;
-               uint64_t       i_iosp                    :      1;
-               uint64_t       i_rsvd                    :     51;
+       uint64_t ii_itte5_regval;
+       struct {
+               uint64_t i_offset:5;
+               uint64_t i_rsvd_1:3;
+               uint64_t i_w_num:4;
+               uint64_t i_iosp:1;
+               uint64_t i_rsvd:51;

        } ii_itte5_fld_s;
 } ii_itte5_u_t;
 
        } ii_itte5_fld_s;
 } ii_itte5_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *
  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *


@@ -794,23 +766,22 @@ typedef union ii_itte5_u {
  * Crosstalk space addressable by the Shub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *
  * Crosstalk space addressable by the Shub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_itte6_u {
  ************************************************************************/
 
 typedef union ii_itte6_u {

-       uint64_t        ii_itte6_regval;
-       struct  {
-               uint64_t        i_offset                  :      5;
-               uint64_t       i_rsvd_1                  :      3;
-               uint64_t       i_w_num                   :      4;
-               uint64_t       i_iosp                    :      1;
-               uint64_t       i_rsvd                    :     51;
+       uint64_t ii_itte6_regval;
+       struct {
+               uint64_t i_offset:5;
+               uint64_t i_rsvd_1:3;
+               uint64_t i_w_num:4;
+               uint64_t i_iosp:1;
+               uint64_t i_rsvd:51;

        } ii_itte6_fld_s;
 } ii_itte6_u_t;
 
        } ii_itte6_fld_s;
 } ii_itte6_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *
  * Description:  There are seven instances of translation table entry   *
  * registers. Each register maps a Shub Big Window to a 48-bit          *
  * address on Crosstalk.                                                *


@@ -833,23 +804,22 @@ typedef union ii_itte6_u {
  * Crosstalk space addressable by the SHub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *
  * Crosstalk space addressable by the SHub is thus the lower            *
  * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  * of this space can be accessed.                                       *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_itte7_u {
  ************************************************************************/
 
 typedef union ii_itte7_u {

-       uint64_t        ii_itte7_regval;
-       struct  {
-               uint64_t        i_offset                  :      5;
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t       i_w_num                   :      4;
-               uint64_t       i_iosp                    :      1;
-               uint64_t       i_rsvd                    :     51;
+       uint64_t ii_itte7_regval;
+       struct {
+               uint64_t i_offset:5;
+               uint64_t i_rsvd_1:3;
+               uint64_t i_w_num:4;
+               uint64_t i_iosp:1;
+               uint64_t i_rsvd:51;

        } ii_itte7_fld_s;
 } ii_itte7_u_t;
 
        } ii_itte7_fld_s;
 } ii_itte7_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *


@@ -868,33 +838,32 @@ typedef union ii_itte7_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *

- * .                                                                    *
- *                                                                      *
+ * .                                                                   *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprb0_u {
  ************************************************************************/
 
 typedef union ii_iprb0_u {

-       uint64_t        ii_iprb0_regval;
-       struct  {
-               uint64_t        i_c                       :      8;
-               uint64_t        i_na                      :     14;
-               uint64_t       i_rsvd_2                  :      2;
-               uint64_t        i_nb                      :     14;
-               uint64_t        i_rsvd_1                  :      2;
-               uint64_t        i_m                       :      2;
-               uint64_t        i_f                       :      1;
-               uint64_t        i_of_cnt                  :      5;
-               uint64_t        i_error                   :      1;
-               uint64_t        i_rd_to                   :      1;
-               uint64_t        i_spur_wr                 :      1;
-               uint64_t        i_spur_rd                 :      1;
-               uint64_t        i_rsvd                    :     11;
-               uint64_t        i_mult_err                :      1;
+       uint64_t ii_iprb0_regval;
+       struct {
+               uint64_t i_c:8;
+               uint64_t i_na:14;
+               uint64_t i_rsvd_2:2;
+               uint64_t i_nb:14;
+               uint64_t i_rsvd_1:2;
+               uint64_t i_m:2;
+               uint64_t i_f:1;
+               uint64_t i_of_cnt:5;
+               uint64_t i_error:1;
+               uint64_t i_rd_to:1;
+               uint64_t i_spur_wr:1;
+               uint64_t i_spur_rd:1;
+               uint64_t i_rsvd:11;
+               uint64_t i_mult_err:1;

        } ii_iprb0_fld_s;
 } ii_iprb0_u_t;
 
        } ii_iprb0_fld_s;
 } ii_iprb0_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *


@@ -913,33 +882,32 @@ typedef union ii_iprb0_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *

- * .                                                                    *
- *                                                                      *
+ * .                                                                   *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprb8_u {
  ************************************************************************/
 
 typedef union ii_iprb8_u {

-       uint64_t        ii_iprb8_regval;
-       struct  {
-               uint64_t        i_c                       :      8;
-               uint64_t        i_na                      :     14;
-               uint64_t       i_rsvd_2                  :      2;
-               uint64_t        i_nb                      :     14;
-               uint64_t       i_rsvd_1                  :      2;
-               uint64_t       i_m                       :      2;
-               uint64_t       i_f                       :      1;
-               uint64_t       i_of_cnt                  :      5;
-               uint64_t       i_error                   :      1;
-               uint64_t       i_rd_to                   :      1;
-               uint64_t       i_spur_wr                 :      1;
-               uint64_t        i_spur_rd                 :      1;
-               uint64_t       i_rsvd                    :     11;
-               uint64_t        i_mult_err                :      1;
+       uint64_t ii_iprb8_regval;
+       struct {
+               uint64_t i_c:8;
+               uint64_t i_na:14;
+               uint64_t i_rsvd_2:2;
+               uint64_t i_nb:14;
+               uint64_t i_rsvd_1:2;
+               uint64_t i_m:2;
+               uint64_t i_f:1;
+               uint64_t i_of_cnt:5;
+               uint64_t i_error:1;
+               uint64_t i_rd_to:1;
+               uint64_t i_spur_wr:1;
+               uint64_t i_spur_rd:1;
+               uint64_t i_rsvd:11;
+               uint64_t i_mult_err:1;

        } ii_iprb8_fld_s;
 } ii_iprb8_u_t;
 
        } ii_iprb8_fld_s;
 } ii_iprb8_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *


@@ -958,33 +926,32 @@ typedef union ii_iprb8_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *

- * .                                                                    *
- *                                                                      *
+ * .                                                                   *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprb9_u {
  ************************************************************************/
 
 typedef union ii_iprb9_u {

-       uint64_t        ii_iprb9_regval;
-       struct  {
-               uint64_t        i_c                       :      8;
-               uint64_t        i_na                      :     14;
-               uint64_t        i_rsvd_2                  :      2;
-               uint64_t        i_nb                      :     14;
-               uint64_t        i_rsvd_1                  :      2;
-               uint64_t        i_m                       :      2;
-               uint64_t        i_f                       :      1;
-               uint64_t        i_of_cnt                  :      5;
-               uint64_t        i_error                   :      1;
-               uint64_t        i_rd_to                   :      1;
-               uint64_t        i_spur_wr                 :      1;
-               uint64_t        i_spur_rd                 :      1;
-               uint64_t        i_rsvd                    :     11;
-               uint64_t        i_mult_err                :      1;
+       uint64_t ii_iprb9_regval;
+       struct {
+               uint64_t i_c:8;
+               uint64_t i_na:14;
+               uint64_t i_rsvd_2:2;
+               uint64_t i_nb:14;
+               uint64_t i_rsvd_1:2;
+               uint64_t i_m:2;
+               uint64_t i_f:1;
+               uint64_t i_of_cnt:5;
+               uint64_t i_error:1;
+               uint64_t i_rd_to:1;
+               uint64_t i_spur_wr:1;
+               uint64_t i_spur_rd:1;
+               uint64_t i_rsvd:11;
+               uint64_t i_mult_err:1;

        } ii_iprb9_fld_s;
 } ii_iprb9_u_t;
 
        } ii_iprb9_fld_s;
 } ii_iprb9_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.        *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.        *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *


@@ -1003,33 +970,32 @@ typedef union ii_iprb9_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *

- *                                                                      *
- *                                                                      *
+ *                                                                     *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprba_u {
  ************************************************************************/
 
 typedef union ii_iprba_u {

-       uint64_t        ii_iprba_regval;
-       struct  {
-               uint64_t        i_c                       :      8;
-               uint64_t        i_na                      :     14;
-               uint64_t       i_rsvd_2                  :      2;
-               uint64_t        i_nb                      :     14;
-               uint64_t        i_rsvd_1                  :      2;
-               uint64_t        i_m                       :      2;
-               uint64_t        i_f                       :      1;
-               uint64_t        i_of_cnt                  :      5;
-               uint64_t        i_error                   :      1;
-               uint64_t        i_rd_to                   :      1;
-               uint64_t        i_spur_wr                 :      1;
-               uint64_t        i_spur_rd                 :      1;
-               uint64_t        i_rsvd                    :     11;
-               uint64_t        i_mult_err                :      1;
+       uint64_t ii_iprba_regval;
+       struct {
+               uint64_t i_c:8;
+               uint64_t i_na:14;
+               uint64_t i_rsvd_2:2;
+               uint64_t i_nb:14;
+               uint64_t i_rsvd_1:2;
+               uint64_t i_m:2;
+               uint64_t i_f:1;
+               uint64_t i_of_cnt:5;
+               uint64_t i_error:1;
+               uint64_t i_rd_to:1;
+               uint64_t i_spur_wr:1;
+               uint64_t i_spur_rd:1;
+               uint64_t i_rsvd:11;
+               uint64_t i_mult_err:1;

        } ii_iprba_fld_s;
 } ii_iprba_u_t;
 
        } ii_iprba_fld_s;
 } ii_iprba_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *


@@ -1048,33 +1014,32 @@ typedef union ii_iprba_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *

- * .                                                                    *
- *                                                                      *
+ * .                                                                   *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprbb_u {
  ************************************************************************/
 
 typedef union ii_iprbb_u {

-       uint64_t        ii_iprbb_regval;
-       struct  {
-               uint64_t        i_c                       :      8;
-               uint64_t        i_na                      :     14;
-               uint64_t        i_rsvd_2                  :      2;
-               uint64_t        i_nb                      :     14;
-               uint64_t        i_rsvd_1                  :      2;
-               uint64_t        i_m                       :      2;
-               uint64_t        i_f                       :      1;
-               uint64_t        i_of_cnt                  :      5;
-               uint64_t        i_error                   :      1;
-               uint64_t        i_rd_to                   :      1;
-               uint64_t        i_spur_wr                 :      1;
-               uint64_t        i_spur_rd                 :      1;
-               uint64_t        i_rsvd                    :     11;
-               uint64_t        i_mult_err                :      1;
+       uint64_t ii_iprbb_regval;
+       struct {
+               uint64_t i_c:8;
+               uint64_t i_na:14;
+               uint64_t i_rsvd_2:2;
+               uint64_t i_nb:14;
+               uint64_t i_rsvd_1:2;
+               uint64_t i_m:2;
+               uint64_t i_f:1;
+               uint64_t i_of_cnt:5;
+               uint64_t i_error:1;
+               uint64_t i_rd_to:1;
+               uint64_t i_spur_wr:1;
+               uint64_t i_spur_rd:1;
+               uint64_t i_rsvd:11;
+               uint64_t i_mult_err:1;

        } ii_iprbb_fld_s;
 } ii_iprbb_u_t;
 
        } ii_iprbb_fld_s;
 } ii_iprbb_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *


@@ -1093,33 +1058,32 @@ typedef union ii_iprbb_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *

- * .                                                                    *
- *                                                                      *
+ * .                                                                   *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprbc_u {
  ************************************************************************/
 
 typedef union ii_iprbc_u {

-       uint64_t        ii_iprbc_regval;
-       struct  {
-               uint64_t        i_c                       :      8;
-               uint64_t        i_na                      :     14;
-               uint64_t        i_rsvd_2                  :      2;
-               uint64_t        i_nb                      :     14;
-               uint64_t        i_rsvd_1                  :      2;
-               uint64_t        i_m                       :      2;
-               uint64_t        i_f                       :      1;
-               uint64_t        i_of_cnt                  :      5;
-               uint64_t        i_error                   :      1;
-               uint64_t        i_rd_to                   :      1;
-               uint64_t        i_spur_wr                 :      1;
-               uint64_t        i_spur_rd                 :      1;
-               uint64_t        i_rsvd                    :     11;
-               uint64_t        i_mult_err                :      1;
+       uint64_t ii_iprbc_regval;
+       struct {
+               uint64_t i_c:8;
+               uint64_t i_na:14;
+               uint64_t i_rsvd_2:2;
+               uint64_t i_nb:14;
+               uint64_t i_rsvd_1:2;
+               uint64_t i_m:2;
+               uint64_t i_f:1;
+               uint64_t i_of_cnt:5;
+               uint64_t i_error:1;
+               uint64_t i_rd_to:1;
+               uint64_t i_spur_wr:1;
+               uint64_t i_spur_rd:1;
+               uint64_t i_rsvd:11;
+               uint64_t i_mult_err:1;

        } ii_iprbc_fld_s;
 } ii_iprbc_u_t;
 
        } ii_iprbc_fld_s;
 } ii_iprbc_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *


@@ -1138,33 +1102,32 @@ typedef union ii_iprbc_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *

- * .                                                                    *
- *                                                                      *
+ * .                                                                   *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprbd_u {
  ************************************************************************/
 
 typedef union ii_iprbd_u {

-       uint64_t        ii_iprbd_regval;
-       struct  {
-               uint64_t        i_c                       :      8;
-               uint64_t        i_na                      :     14;
-               uint64_t        i_rsvd_2                  :      2;
-               uint64_t        i_nb                      :     14;
-               uint64_t        i_rsvd_1                  :      2;
-               uint64_t        i_m                       :      2;
-               uint64_t        i_f                       :      1;
-               uint64_t        i_of_cnt                  :      5;
-               uint64_t        i_error                   :      1;
-               uint64_t        i_rd_to                   :      1;
-               uint64_t        i_spur_wr                 :      1;
-               uint64_t        i_spur_rd                 :      1;
-               uint64_t        i_rsvd                    :     11;
-               uint64_t        i_mult_err                :      1;
+       uint64_t ii_iprbd_regval;
+       struct {
+               uint64_t i_c:8;
+               uint64_t i_na:14;
+               uint64_t i_rsvd_2:2;
+               uint64_t i_nb:14;
+               uint64_t i_rsvd_1:2;
+               uint64_t i_m:2;
+               uint64_t i_f:1;
+               uint64_t i_of_cnt:5;
+               uint64_t i_error:1;
+               uint64_t i_rd_to:1;
+               uint64_t i_spur_wr:1;
+               uint64_t i_spur_rd:1;
+               uint64_t i_rsvd:11;
+               uint64_t i_mult_err:1;

        } ii_iprbd_fld_s;
 } ii_iprbd_u_t;
 
        } ii_iprbd_fld_s;
 } ii_iprbd_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of SHub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *


@@ -1183,33 +1146,32 @@ typedef union ii_iprbd_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *

- * .                                                                    *
- *                                                                      *
+ * .                                                                   *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprbe_u {
  ************************************************************************/
 
 typedef union ii_iprbe_u {

-       uint64_t        ii_iprbe_regval;
-       struct  {
-               uint64_t        i_c                       :      8;
-               uint64_t        i_na                      :     14;
-               uint64_t        i_rsvd_2                  :      2;
-               uint64_t        i_nb                      :     14;
-               uint64_t        i_rsvd_1                  :      2;
-               uint64_t        i_m                       :      2;
-               uint64_t        i_f                       :      1;
-               uint64_t        i_of_cnt                  :      5;
-               uint64_t        i_error                   :      1;
-               uint64_t        i_rd_to                   :      1;
-               uint64_t        i_spur_wr                 :      1;
-               uint64_t        i_spur_rd                 :      1;
-               uint64_t        i_rsvd                    :     11;
-               uint64_t        i_mult_err                :      1;
+       uint64_t ii_iprbe_regval;
+       struct {
+               uint64_t i_c:8;
+               uint64_t i_na:14;
+               uint64_t i_rsvd_2:2;
+               uint64_t i_nb:14;
+               uint64_t i_rsvd_1:2;
+               uint64_t i_m:2;
+               uint64_t i_f:1;
+               uint64_t i_of_cnt:5;
+               uint64_t i_error:1;
+               uint64_t i_rd_to:1;
+               uint64_t i_spur_wr:1;
+               uint64_t i_spur_rd:1;
+               uint64_t i_rsvd:11;
+               uint64_t i_mult_err:1;

        } ii_iprbe_fld_s;
 } ii_iprbe_u_t;
 
        } ii_iprbe_fld_s;
 } ii_iprbe_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of Shub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
  * Description:  There are 9 instances of this register, one per        *
  * actual widget in this implementation of Shub and Crossbow.           *
  * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *


@@ -1228,33 +1190,32 @@ typedef union ii_iprbe_u {
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
  * register; the write will correct the C field and capture its new     *
  * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *

- * .                                                                    *
- *                                                                      *
+ * .                                                                   *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprbf_u {
  ************************************************************************/
 
 typedef union ii_iprbf_u {

-        uint64_t       ii_iprbf_regval;
-        struct  {
-                uint64_t       i_c                       :      8;
-                uint64_t       i_na                      :     14;
-                uint64_t       i_rsvd_2                  :      2;
-                uint64_t       i_nb                      :     14;
-                uint64_t       i_rsvd_1                  :      2;
-                uint64_t       i_m                       :      2;
-                uint64_t       i_f                       :      1;
-                uint64_t       i_of_cnt                  :      5;
-                uint64_t       i_error                   :      1;
-                uint64_t       i_rd_to                   :      1;
-                uint64_t       i_spur_wr                 :      1;
-                uint64_t       i_spur_rd                 :      1;
-                uint64_t       i_rsvd                    :     11;
-                uint64_t       i_mult_err                :      1;
-        } ii_iprbe_fld_s;
+       uint64_t ii_iprbf_regval;
+       struct {
+               uint64_t i_c:8;
+               uint64_t i_na:14;
+               uint64_t i_rsvd_2:2;
+               uint64_t i_nb:14;
+               uint64_t i_rsvd_1:2;
+               uint64_t i_m:2;
+               uint64_t i_f:1;
+               uint64_t i_of_cnt:5;
+               uint64_t i_error:1;
+               uint64_t i_rd_to:1;
+               uint64_t i_spur_wr:1;
+               uint64_t i_spur_rd:1;
+               uint64_t i_rsvd:11;
+               uint64_t i_mult_err:1;
+       } ii_iprbe_fld_s;

 } ii_iprbf_u_t;
 
 } ii_iprbf_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register specifies the timeout value to use for monitoring     *
  * Crosstalk credits which are used outbound to Crosstalk. An           *
  * internal counter called the Crosstalk Credit Timeout Counter         *
  *  This register specifies the timeout value to use for monitoring     *
  * Crosstalk credits which are used outbound to Crosstalk. An           *
  * internal counter called the Crosstalk Credit Timeout Counter         *


@@ -1267,20 +1228,19 @@ typedef union ii_iprbf_u {
  * Crosstalk Credit Timeout has occurred. The internal counter is not   *
  * readable from software, and stops counting at its maximum value,     *
  * so it cannot cause more than one interrupt.                          *
  * Crosstalk Credit Timeout has occurred. The internal counter is not   *
  * readable from software, and stops counting at its maximum value,     *
  * so it cannot cause more than one interrupt.                          *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ixcc_u {
  ************************************************************************/
 
 typedef union ii_ixcc_u {

-       uint64_t        ii_ixcc_regval;
-       struct  {
-               uint64_t        i_time_out                :     26;
-               uint64_t        i_rsvd                    :     38;
+       uint64_t ii_ixcc_regval;
+       struct {
+               uint64_t i_time_out:26;
+               uint64_t i_rsvd:38;

        } ii_ixcc_fld_s;
 } ii_ixcc_u_t;
 
        } ii_ixcc_fld_s;
 } ii_ixcc_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  This register qualifies all the PIO and DMA            *
  * operations launched from widget 0 towards the SHub. In               *
  * addition, it also qualifies accesses by the BTE streams.             *
  * Description:  This register qualifies all the PIO and DMA            *
  * operations launched from widget 0 towards the SHub. In               *
  * addition, it also qualifies accesses by the BTE streams.             *


@@ -1292,27 +1252,25 @@ typedef union ii_ixcc_u {
  * the Wx_IAC field. The bits in this field are set by writing a 1 to   *
  * them. Incoming replies from Crosstalk are not subject to this        *
  * access control mechanism.                                            *
  * the Wx_IAC field. The bits in this field are set by writing a 1 to   *
  * them. Incoming replies from Crosstalk are not subject to this        *
  * access control mechanism.                                            *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_imem_u {
  ************************************************************************/
 
 typedef union ii_imem_u {

-       uint64_t        ii_imem_regval;
-       struct  {
-               uint64_t        i_w0_esd                  :      1;
-               uint64_t        i_rsvd_3                  :      3;
-               uint64_t        i_b0_esd                  :      1;
-               uint64_t        i_rsvd_2                  :      3;
-               uint64_t        i_b1_esd                  :      1;
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_clr_precise             :      1;
-               uint64_t       i_rsvd                    :     51;
+       uint64_t ii_imem_regval;
+       struct {
+               uint64_t i_w0_esd:1;
+               uint64_t i_rsvd_3:3;
+               uint64_t i_b0_esd:1;
+               uint64_t i_rsvd_2:3;
+               uint64_t i_b1_esd:1;
+               uint64_t i_rsvd_1:3;
+               uint64_t i_clr_precise:1;
+               uint64_t i_rsvd:51;

        } ii_imem_fld_s;
 } ii_imem_u_t;
 
        } ii_imem_fld_s;
 } ii_imem_u_t;
 

-
-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  This register specifies the timeout value to use for   *
  * monitoring Crosstalk tail flits coming into the Shub in the          *
  * TAIL_TO field. An internal counter associated with this register     *
  * Description:  This register specifies the timeout value to use for   *
  * monitoring Crosstalk tail flits coming into the Shub in the          *
  * TAIL_TO field. An internal counter associated with this register     *


@@ -1332,90 +1290,87 @@ typedef union ii_imem_u {
  * the value in the RRSP_TO field, a Read Response Timeout has          *
  * occurred, and error handling occurs as described in the Error        *
  * Handling section of this document.                                   *
  * the value in the RRSP_TO field, a Read Response Timeout has          *
  * occurred, and error handling occurs as described in the Error        *
  * Handling section of this document.                                   *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ixtt_u {
  ************************************************************************/
 
 typedef union ii_ixtt_u {

-       uint64_t        ii_ixtt_regval;
-       struct  {
-               uint64_t        i_tail_to                 :     26;
-               uint64_t        i_rsvd_1                  :      6;
-               uint64_t        i_rrsp_ps                 :     23;
-               uint64_t        i_rrsp_to                 :      5;
-               uint64_t        i_rsvd                    :      4;
+       uint64_t ii_ixtt_regval;
+       struct {
+               uint64_t i_tail_to:26;
+               uint64_t i_rsvd_1:6;
+               uint64_t i_rrsp_ps:23;
+               uint64_t i_rrsp_to:5;
+               uint64_t i_rsvd:4;

        } ii_ixtt_fld_s;
 } ii_ixtt_u_t;
 
        } ii_ixtt_fld_s;
 } ii_ixtt_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  Writing a 1 to the fields of this register clears the appropriate   *
  * error bits in other areas of SHub. Note that when the                *
  * E_PRB_x bits are used to clear error bits in PRB registers,          *
  * SPUR_RD and SPUR_WR may persist, because they require additional     *
  * action to clear them. See the IPRBx and IXSS Register                *
  * specifications.                                                      *
  *  Writing a 1 to the fields of this register clears the appropriate   *
  * error bits in other areas of SHub. Note that when the                *
  * E_PRB_x bits are used to clear error bits in PRB registers,          *
  * SPUR_RD and SPUR_WR may persist, because they require additional     *
  * action to clear them. See the IPRBx and IXSS Register                *
  * specifications.                                                      *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ieclr_u {
  ************************************************************************/
 
 typedef union ii_ieclr_u {

-       uint64_t        ii_ieclr_regval;
-       struct  {
-               uint64_t        i_e_prb_0                 :      1;
-               uint64_t        i_rsvd                    :      7;
-               uint64_t        i_e_prb_8                 :      1;
-               uint64_t        i_e_prb_9                 :      1;
-               uint64_t        i_e_prb_a                 :      1;
-               uint64_t        i_e_prb_b                 :      1;
-               uint64_t        i_e_prb_c                 :      1;
-               uint64_t        i_e_prb_d                 :      1;
-               uint64_t        i_e_prb_e                 :      1;
-               uint64_t        i_e_prb_f                 :      1;
-               uint64_t        i_e_crazy                 :      1;
-               uint64_t        i_e_bte_0                 :      1;
-               uint64_t        i_e_bte_1                 :      1;
-               uint64_t        i_reserved_1              :     10;
-               uint64_t        i_spur_rd_hdr             :      1;
-               uint64_t        i_cam_intr_to             :      1;
-               uint64_t        i_cam_overflow            :      1;
-               uint64_t        i_cam_read_miss           :      1;
-               uint64_t        i_ioq_rep_underflow       :      1;
-               uint64_t        i_ioq_req_underflow       :      1;
-               uint64_t        i_ioq_rep_overflow        :      1;
-               uint64_t        i_ioq_req_overflow        :      1;
-               uint64_t        i_iiq_rep_overflow        :      1;
-               uint64_t        i_iiq_req_overflow        :      1;
-               uint64_t        i_ii_xn_rep_cred_overflow :      1;
-               uint64_t        i_ii_xn_req_cred_overflow :      1;
-               uint64_t        i_ii_xn_invalid_cmd       :      1;
-               uint64_t        i_xn_ii_invalid_cmd       :      1;
-               uint64_t        i_reserved_2              :     21;
+       uint64_t ii_ieclr_regval;
+       struct {
+               uint64_t i_e_prb_0:1;
+               uint64_t i_rsvd:7;
+               uint64_t i_e_prb_8:1;
+               uint64_t i_e_prb_9:1;
+               uint64_t i_e_prb_a:1;
+               uint64_t i_e_prb_b:1;
+               uint64_t i_e_prb_c:1;
+               uint64_t i_e_prb_d:1;
+               uint64_t i_e_prb_e:1;
+               uint64_t i_e_prb_f:1;
+               uint64_t i_e_crazy:1;
+               uint64_t i_e_bte_0:1;
+               uint64_t i_e_bte_1:1;
+               uint64_t i_reserved_1:10;
+               uint64_t i_spur_rd_hdr:1;
+               uint64_t i_cam_intr_to:1;
+               uint64_t i_cam_overflow:1;
+               uint64_t i_cam_read_miss:1;
+               uint64_t i_ioq_rep_underflow:1;
+               uint64_t i_ioq_req_underflow:1;
+               uint64_t i_ioq_rep_overflow:1;
+               uint64_t i_ioq_req_overflow:1;
+               uint64_t i_iiq_rep_overflow:1;
+               uint64_t i_iiq_req_overflow:1;
+               uint64_t i_ii_xn_rep_cred_overflow:1;
+               uint64_t i_ii_xn_req_cred_overflow:1;
+               uint64_t i_ii_xn_invalid_cmd:1;
+               uint64_t i_xn_ii_invalid_cmd:1;
+               uint64_t i_reserved_2:21;

        } ii_ieclr_fld_s;
 } ii_ieclr_u_t;
 
        } ii_ieclr_fld_s;
 } ii_ieclr_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register controls both BTEs. SOFT_RESET is intended for        *
  * recovery after an error. COUNT controls the total number of CRBs     *
  * that both BTEs (combined) can use, which affects total BTE           *
  * bandwidth.                                                           *
  *  This register controls both BTEs. SOFT_RESET is intended for        *
  * recovery after an error. COUNT controls the total number of CRBs     *
  * that both BTEs (combined) can use, which affects total BTE           *
  * bandwidth.                                                           *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ibcr_u {
  ************************************************************************/
 
 typedef union ii_ibcr_u {

-       uint64_t        ii_ibcr_regval;
-       struct  {
-               uint64_t        i_count                   :      4;
-               uint64_t        i_rsvd_1                  :      4;
-               uint64_t        i_soft_reset              :      1;
-               uint64_t        i_rsvd                    :     55;
+       uint64_t ii_ibcr_regval;
+       struct {
+               uint64_t i_count:4;
+               uint64_t i_rsvd_1:4;
+               uint64_t i_soft_reset:1;
+               uint64_t i_rsvd:55;

        } ii_ibcr_fld_s;
 } ii_ibcr_u_t;
 
        } ii_ibcr_fld_s;
 } ii_ibcr_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register contains the header of a spurious read response       *
  * received from Crosstalk. A spurious read response is defined as a    *
  * read response received by II from a widget for which (1) the SIDN    *
  *  This register contains the header of a spurious read response       *
  * received from Crosstalk. A spurious read response is defined as a    *
  * read response received by II from a widget for which (1) the SIDN    *


@@ -1440,49 +1395,47 @@ typedef union ii_ibcr_u {
  * will be set. Any SPUR_RD bits in any other PRB registers indicate    *
  * spurious messages from other widets which were detected after the    *
  * header was captured..                                                *
  * will be set. Any SPUR_RD bits in any other PRB registers indicate    *
  * spurious messages from other widets which were detected after the    *
  * header was captured..                                                *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ixsm_u {
  ************************************************************************/
 
 typedef union ii_ixsm_u {

-       uint64_t        ii_ixsm_regval;
-       struct  {
-               uint64_t        i_byte_en                 :     32;
-               uint64_t        i_reserved                :      1;
-               uint64_t        i_tag                     :      3;
-               uint64_t        i_alt_pactyp              :      4;
-               uint64_t        i_bo                      :      1;
-               uint64_t        i_error                   :      1;
-               uint64_t        i_vbpm                    :      1;
-               uint64_t        i_gbr                     :      1;
-               uint64_t        i_ds                      :      2;
-               uint64_t        i_ct                      :      1;
-               uint64_t        i_tnum                    :      5;
-               uint64_t        i_pactyp                  :      4;
-               uint64_t        i_sidn                    :      4;
-               uint64_t        i_didn                    :      4;
+       uint64_t ii_ixsm_regval;
+       struct {
+               uint64_t i_byte_en:32;
+               uint64_t i_reserved:1;
+               uint64_t i_tag:3;
+               uint64_t i_alt_pactyp:4;
+               uint64_t i_bo:1;
+               uint64_t i_error:1;
+               uint64_t i_vbpm:1;
+               uint64_t i_gbr:1;
+               uint64_t i_ds:2;
+               uint64_t i_ct:1;
+               uint64_t i_tnum:5;
+               uint64_t i_pactyp:4;
+               uint64_t i_sidn:4;
+               uint64_t i_didn:4;

        } ii_ixsm_fld_s;
 } ii_ixsm_u_t;
 
        } ii_ixsm_fld_s;
 } ii_ixsm_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register contains the sideband bits of a spurious read         *
  * response received from Crosstalk.                                    *
  *  This register contains the sideband bits of a spurious read         *
  * response received from Crosstalk.                                    *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ixss_u {
  ************************************************************************/
 
 typedef union ii_ixss_u {

-       uint64_t        ii_ixss_regval;
-       struct  {
-               uint64_t        i_sideband                :      8;
-               uint64_t        i_rsvd                    :     55;
-               uint64_t        i_valid                   :      1;
+       uint64_t ii_ixss_regval;
+       struct {
+               uint64_t i_sideband:8;
+               uint64_t i_rsvd:55;
+               uint64_t i_valid:1;

        } ii_ixss_fld_s;
 } ii_ixss_u_t;
 
        } ii_ixss_fld_s;
 } ii_ixss_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register enables software to access the II LLP's test port.    *
  * Refer to the LLP 2.5 documentation for an explanation of the test    *
  * port. Software can write to this register to program the values      *
  *  This register enables software to access the II LLP's test port.    *
  * Refer to the LLP 2.5 documentation for an explanation of the test    *
  * port. Software can write to this register to program the values      *


@@ -1490,27 +1443,26 @@ typedef union ii_ixss_u {
  * TestMask and TestSeed). Similarly, software can read from this       *
  * register to obtain the values of the test port's status outputs      *
  * (TestCBerr, TestValid and TestData).                                 *
  * TestMask and TestSeed). Similarly, software can read from this       *
  * register to obtain the values of the test port's status outputs      *
  * (TestCBerr, TestValid and TestData).                                 *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ilct_u {
  ************************************************************************/
 
 typedef union ii_ilct_u {

-       uint64_t        ii_ilct_regval;
-       struct  {
-               uint64_t        i_test_seed               :     20;
-               uint64_t        i_test_mask               :      8;
-               uint64_t        i_test_data               :     20;
-               uint64_t        i_test_valid              :      1;
-               uint64_t        i_test_cberr              :      1;
-               uint64_t        i_test_flit               :      3;
-               uint64_t        i_test_clear              :      1;
-               uint64_t        i_test_err_capture        :      1;
-               uint64_t        i_rsvd                    :      9;
+       uint64_t ii_ilct_regval;
+       struct {
+               uint64_t i_test_seed:20;
+               uint64_t i_test_mask:8;
+               uint64_t i_test_data:20;
+               uint64_t i_test_valid:1;
+               uint64_t i_test_cberr:1;
+               uint64_t i_test_flit:3;
+               uint64_t i_test_clear:1;
+               uint64_t i_test_err_capture:1;
+               uint64_t i_rsvd:9;

        } ii_ilct_fld_s;
 } ii_ilct_u_t;
 
        } ii_ilct_fld_s;
 } ii_ilct_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  If the II detects an illegal incoming Duplonet packet (request or   *
  * reply) when VALID==0 in the IIEPH1 register, then it saves the       *
  * contents of the packet's header flit in the IIEPH1 and IIEPH2        *
  *  If the II detects an illegal incoming Duplonet packet (request or   *
  * reply) when VALID==0 in the IIEPH1 register, then it saves the       *
  * contents of the packet's header flit in the IIEPH1 and IIEPH2        *


@@ -1526,575 +1478,549 @@ typedef union ii_ilct_u {
  * packet when VALID==1 in the IIEPH1 register, then it merely sets     *
  * the OVERRUN bit to indicate that a subsequent error has happened,    *
  * and does nothing further.                                            *
  * packet when VALID==1 in the IIEPH1 register, then it merely sets     *
  * the OVERRUN bit to indicate that a subsequent error has happened,    *
  * and does nothing further.                                            *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iieph1_u {
  ************************************************************************/
 
 typedef union ii_iieph1_u {

-       uint64_t        ii_iieph1_regval;
-       struct  {
-               uint64_t        i_command                 :      7;
-               uint64_t        i_rsvd_5                  :      1;
-               uint64_t        i_suppl                   :     14;
-               uint64_t        i_rsvd_4                  :      1;
-               uint64_t        i_source                  :     14;
-               uint64_t        i_rsvd_3                  :      1;
-               uint64_t        i_err_type                :      4;
-               uint64_t        i_rsvd_2                  :      4;
-               uint64_t        i_overrun                 :      1;
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_valid                   :      1;
-               uint64_t        i_rsvd                    :     13;
+       uint64_t ii_iieph1_regval;
+       struct {
+               uint64_t i_command:7;
+               uint64_t i_rsvd_5:1;
+               uint64_t i_suppl:14;
+               uint64_t i_rsvd_4:1;
+               uint64_t i_source:14;
+               uint64_t i_rsvd_3:1;
+               uint64_t i_err_type:4;
+               uint64_t i_rsvd_2:4;
+               uint64_t i_overrun:1;
+               uint64_t i_rsvd_1:3;
+               uint64_t i_valid:1;
+               uint64_t i_rsvd:13;

        } ii_iieph1_fld_s;
 } ii_iieph1_u_t;
 
        } ii_iieph1_fld_s;
 } ii_iieph1_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register holds the Address field from the header flit of an    *
  * incoming erroneous Duplonet packet, along with the tail bit which    *
  * accompanied this header flit. This register is essentially an        *
  * extension of IIEPH1. Two registers were necessary because the 64     *
  * bits available in only a single register were insufficient to        *
  * capture the entire header flit of an erroneous packet.               *
  *  This register holds the Address field from the header flit of an    *
  * incoming erroneous Duplonet packet, along with the tail bit which    *
  * accompanied this header flit. This register is essentially an        *
  * extension of IIEPH1. Two registers were necessary because the 64     *
  * bits available in only a single register were insufficient to        *
  * capture the entire header flit of an erroneous packet.               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iieph2_u {
  ************************************************************************/
 
 typedef union ii_iieph2_u {

-       uint64_t        ii_iieph2_regval;
-       struct  {
-               uint64_t        i_rsvd_0                  :      3;
-               uint64_t        i_address                 :     47;
-               uint64_t        i_rsvd_1                  :     10;
-               uint64_t        i_tail                    :      1;
-               uint64_t        i_rsvd                    :      3;
+       uint64_t ii_iieph2_regval;
+       struct {
+               uint64_t i_rsvd_0:3;
+               uint64_t i_address:47;
+               uint64_t i_rsvd_1:10;
+               uint64_t i_tail:1;
+               uint64_t i_rsvd:3;

        } ii_iieph2_fld_s;
 } ii_iieph2_u_t;
 
        } ii_iieph2_fld_s;
 } ii_iieph2_u_t;
 

-

 /******************************/
 
 /******************************/
 

-
-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register's value is a bit vector that guards access from SXBs  *
  * to local registers within the II as well as to external Crosstalk    *
  * widgets                                                             *
  *  This register's value is a bit vector that guards access from SXBs  *
  * to local registers within the II as well as to external Crosstalk    *
  * widgets                                                             *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_islapr_u {
  ************************************************************************/
 
 typedef union ii_islapr_u {

-       uint64_t        ii_islapr_regval;
-       struct  {
-               uint64_t        i_region                  :     64;
+       uint64_t ii_islapr_regval;
+       struct {
+               uint64_t i_region:64;

        } ii_islapr_fld_s;
 } ii_islapr_u_t;
 
        } ii_islapr_fld_s;
 } ii_islapr_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  A write to this register of the 56-bit value "Pup+Bun" will cause  *
  * the bit in the ISLAPR register corresponding to the region of the   *
  * requestor to be set (access allowed).                               (
  *  A write to this register of the 56-bit value "Pup+Bun" will cause  *
  * the bit in the ISLAPR register corresponding to the region of the   *
  * requestor to be set (access allowed).                               (

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_islapo_u {
  ************************************************************************/
 
 typedef union ii_islapo_u {

-       uint64_t        ii_islapo_regval;
-       struct  {
-               uint64_t        i_io_sbx_ovrride          :     56;
-               uint64_t        i_rsvd                    :      8;
+       uint64_t ii_islapo_regval;
+       struct {
+               uint64_t i_io_sbx_ovrride:56;
+               uint64_t i_rsvd:8;

        } ii_islapo_fld_s;
 } ii_islapo_u_t;
 
 /************************************************************************
        } ii_islapo_fld_s;
 } ii_islapo_u_t;
 
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  Determines how long the wrapper will wait aftr an interrupt is     *
  * initially issued from the II before it times out the outstanding    *
  * interrupt and drops it from the interrupt queue.                    * 
  *  Determines how long the wrapper will wait aftr an interrupt is     *
  * initially issued from the II before it times out the outstanding    *
  * interrupt and drops it from the interrupt queue.                    * 

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iwi_u {
  ************************************************************************/
 
 typedef union ii_iwi_u {

-       uint64_t        ii_iwi_regval;
-       struct  {
-               uint64_t        i_prescale                :     24;
-               uint64_t        i_rsvd                    :      8;
-               uint64_t        i_timeout                 :      8;
-               uint64_t        i_rsvd1                   :      8;
-               uint64_t        i_intrpt_retry_period     :      8;
-               uint64_t        i_rsvd2                   :      8;
+       uint64_t ii_iwi_regval;
+       struct {
+               uint64_t i_prescale:24;
+               uint64_t i_rsvd:8;
+               uint64_t i_timeout:8;
+               uint64_t i_rsvd1:8;
+               uint64_t i_intrpt_retry_period:8;
+               uint64_t i_rsvd2:8;

        } ii_iwi_fld_s;
 } ii_iwi_u_t;
 
 /************************************************************************
        } ii_iwi_fld_s;
 } ii_iwi_u_t;
 
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  Log errors which have occurred in the II wrapper. The errors are   *
  * cleared by writing to the IECLR register.                           * 
  *  Log errors which have occurred in the II wrapper. The errors are   *
  * cleared by writing to the IECLR register.                           * 

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iwel_u {
  ************************************************************************/
 
 typedef union ii_iwel_u {

-       uint64_t        ii_iwel_regval;
-       struct  {
-               uint64_t        i_intr_timed_out          :      1;
-               uint64_t        i_rsvd                    :      7;
-               uint64_t        i_cam_overflow            :      1;
-               uint64_t        i_cam_read_miss           :      1;
-               uint64_t        i_rsvd1                   :      2;
-               uint64_t        i_ioq_rep_underflow       :      1;
-               uint64_t        i_ioq_req_underflow       :      1;
-               uint64_t        i_ioq_rep_overflow        :      1;
-               uint64_t        i_ioq_req_overflow        :      1;
-               uint64_t        i_iiq_rep_overflow        :      1;
-               uint64_t        i_iiq_req_overflow        :      1;
-               uint64_t        i_rsvd2                   :      6;
-               uint64_t        i_ii_xn_rep_cred_over_under:     1;
-               uint64_t        i_ii_xn_req_cred_over_under:     1;
-               uint64_t        i_rsvd3                   :      6;
-               uint64_t        i_ii_xn_invalid_cmd       :      1;
-               uint64_t        i_xn_ii_invalid_cmd       :      1;
-               uint64_t        i_rsvd4                   :     30;
+       uint64_t ii_iwel_regval;
+       struct {
+               uint64_t i_intr_timed_out:1;
+               uint64_t i_rsvd:7;
+               uint64_t i_cam_overflow:1;
+               uint64_t i_cam_read_miss:1;
+               uint64_t i_rsvd1:2;
+               uint64_t i_ioq_rep_underflow:1;
+               uint64_t i_ioq_req_underflow:1;
+               uint64_t i_ioq_rep_overflow:1;
+               uint64_t i_ioq_req_overflow:1;
+               uint64_t i_iiq_rep_overflow:1;
+               uint64_t i_iiq_req_overflow:1;
+               uint64_t i_rsvd2:6;
+               uint64_t i_ii_xn_rep_cred_over_under:1;
+               uint64_t i_ii_xn_req_cred_over_under:1;
+               uint64_t i_rsvd3:6;
+               uint64_t i_ii_xn_invalid_cmd:1;
+               uint64_t i_xn_ii_invalid_cmd:1;
+               uint64_t i_rsvd4:30;

        } ii_iwel_fld_s;
 } ii_iwel_u_t;
 
 /************************************************************************
        } ii_iwel_fld_s;
 } ii_iwel_u_t;
 
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  Controls the II wrapper.                                           * 
  *  Controls the II wrapper.                                           * 

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iwc_u {
  ************************************************************************/
 
 typedef union ii_iwc_u {

-       uint64_t        ii_iwc_regval;
-       struct  {
-               uint64_t        i_dma_byte_swap           :      1;
-               uint64_t        i_rsvd                    :      3;
-               uint64_t        i_cam_read_lines_reset    :      1;
-               uint64_t        i_rsvd1                   :      3;
-               uint64_t        i_ii_xn_cred_over_under_log:     1;
-               uint64_t        i_rsvd2                   :     19;
-               uint64_t        i_xn_rep_iq_depth         :      5;
-               uint64_t        i_rsvd3                   :      3;
-               uint64_t        i_xn_req_iq_depth         :      5;
-               uint64_t        i_rsvd4                   :      3;
-               uint64_t        i_iiq_depth               :      6;
-               uint64_t        i_rsvd5                   :     12;
-               uint64_t        i_force_rep_cred          :      1;
-               uint64_t        i_force_req_cred          :      1;
+       uint64_t ii_iwc_regval;
+       struct {
+               uint64_t i_dma_byte_swap:1;
+               uint64_t i_rsvd:3;
+               uint64_t i_cam_read_lines_reset:1;
+               uint64_t i_rsvd1:3;
+               uint64_t i_ii_xn_cred_over_under_log:1;
+               uint64_t i_rsvd2:19;
+               uint64_t i_xn_rep_iq_depth:5;
+               uint64_t i_rsvd3:3;
+               uint64_t i_xn_req_iq_depth:5;
+               uint64_t i_rsvd4:3;
+               uint64_t i_iiq_depth:6;
+               uint64_t i_rsvd5:12;
+               uint64_t i_force_rep_cred:1;
+               uint64_t i_force_req_cred:1;

        } ii_iwc_fld_s;
 } ii_iwc_u_t;
 
 /************************************************************************
        } ii_iwc_fld_s;
 } ii_iwc_u_t;
 
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  Status in the II wrapper.                                          * 
  *  Status in the II wrapper.                                          * 

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iws_u {
  ************************************************************************/
 
 typedef union ii_iws_u {

-       uint64_t        ii_iws_regval;
-       struct  {
-               uint64_t        i_xn_rep_iq_credits       :      5;
-               uint64_t        i_rsvd                    :      3;
-               uint64_t        i_xn_req_iq_credits       :      5;
-               uint64_t        i_rsvd1                   :     51;
+       uint64_t ii_iws_regval;
+       struct {
+               uint64_t i_xn_rep_iq_credits:5;
+               uint64_t i_rsvd:3;
+               uint64_t i_xn_req_iq_credits:5;
+               uint64_t i_rsvd1:51;

        } ii_iws_fld_s;
 } ii_iws_u_t;
 
 /************************************************************************
        } ii_iws_fld_s;
 } ii_iws_u_t;
 
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  Masks errors in the IWEL register.                                 *
  *  Masks errors in the IWEL register.                                 *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iweim_u {
  ************************************************************************/
 
 typedef union ii_iweim_u {

-       uint64_t        ii_iweim_regval;
-       struct  {
-               uint64_t        i_intr_timed_out          :      1;
-               uint64_t        i_rsvd                    :      7;
-               uint64_t        i_cam_overflow            :      1;
-               uint64_t        i_cam_read_miss           :      1;
-               uint64_t        i_rsvd1                   :      2;
-               uint64_t        i_ioq_rep_underflow       :      1;
-               uint64_t        i_ioq_req_underflow       :      1;
-               uint64_t        i_ioq_rep_overflow        :      1;
-               uint64_t        i_ioq_req_overflow        :      1;
-               uint64_t        i_iiq_rep_overflow        :      1;
-               uint64_t        i_iiq_req_overflow        :      1;
-               uint64_t        i_rsvd2                   :      6;
-               uint64_t        i_ii_xn_rep_cred_overflow :      1;
-               uint64_t        i_ii_xn_req_cred_overflow :      1;
-               uint64_t        i_rsvd3                   :      6;
-               uint64_t        i_ii_xn_invalid_cmd       :      1;
-               uint64_t        i_xn_ii_invalid_cmd       :      1;
-               uint64_t        i_rsvd4                   :     30;
+       uint64_t ii_iweim_regval;
+       struct {
+               uint64_t i_intr_timed_out:1;
+               uint64_t i_rsvd:7;
+               uint64_t i_cam_overflow:1;
+               uint64_t i_cam_read_miss:1;
+               uint64_t i_rsvd1:2;
+               uint64_t i_ioq_rep_underflow:1;
+               uint64_t i_ioq_req_underflow:1;
+               uint64_t i_ioq_rep_overflow:1;
+               uint64_t i_ioq_req_overflow:1;
+               uint64_t i_iiq_rep_overflow:1;
+               uint64_t i_iiq_req_overflow:1;
+               uint64_t i_rsvd2:6;
+               uint64_t i_ii_xn_rep_cred_overflow:1;
+               uint64_t i_ii_xn_req_cred_overflow:1;
+               uint64_t i_rsvd3:6;
+               uint64_t i_ii_xn_invalid_cmd:1;
+               uint64_t i_xn_ii_invalid_cmd:1;
+               uint64_t i_rsvd4:30;

        } ii_iweim_fld_s;
 } ii_iweim_u_t;
 
        } ii_iweim_fld_s;
 } ii_iweim_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  A write to this register causes a particular field in the           *
  * corresponding widget's PRB entry to be adjusted up or down by 1.     *
  * This counter should be used when recovering from error and reset     *
  * conditions. Note that software would be capable of causing           *
  * inadvertent overflow or underflow of these counters.                 *
  *  A write to this register causes a particular field in the           *
  * corresponding widget's PRB entry to be adjusted up or down by 1.     *
  * This counter should be used when recovering from error and reset     *
  * conditions. Note that software would be capable of causing           *
  * inadvertent overflow or underflow of these counters.                 *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ipca_u {
  ************************************************************************/
 
 typedef union ii_ipca_u {

-       uint64_t        ii_ipca_regval;
-       struct  {
-               uint64_t        i_wid                     :      4;
-               uint64_t        i_adjust                  :      1;
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_field                   :      2;
-               uint64_t        i_rsvd                    :     54;
+       uint64_t ii_ipca_regval;
+       struct {
+               uint64_t i_wid:4;
+               uint64_t i_adjust:1;
+               uint64_t i_rsvd_1:3;
+               uint64_t i_field:2;
+               uint64_t i_rsvd:54;

        } ii_ipca_fld_s;
 } ii_ipca_u_t;
 
        } ii_ipca_fld_s;
 } ii_ipca_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
  ************************************************************************/
 

-

 typedef union ii_iprte0a_u {
 typedef union ii_iprte0a_u {

-       uint64_t        ii_iprte0a_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :     54;
-               uint64_t        i_widget                  :      4;
-               uint64_t        i_to_cnt                  :      5;
-               uint64_t       i_vld                     :      1;
+       uint64_t ii_iprte0a_regval;
+       struct {
+               uint64_t i_rsvd_1:54;
+               uint64_t i_widget:4;
+               uint64_t i_to_cnt:5;
+               uint64_t i_vld:1;

        } ii_iprte0a_fld_s;
 } ii_iprte0a_u_t;
 
        } ii_iprte0a_fld_s;
 } ii_iprte0a_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprte1a_u {
  ************************************************************************/
 
 typedef union ii_iprte1a_u {

-       uint64_t        ii_iprte1a_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :     54;
-               uint64_t        i_widget                  :      4;
-               uint64_t        i_to_cnt                  :      5;
-               uint64_t       i_vld                     :      1;
+       uint64_t ii_iprte1a_regval;
+       struct {
+               uint64_t i_rsvd_1:54;
+               uint64_t i_widget:4;
+               uint64_t i_to_cnt:5;
+               uint64_t i_vld:1;

        } ii_iprte1a_fld_s;
 } ii_iprte1a_u_t;
 
        } ii_iprte1a_fld_s;
 } ii_iprte1a_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprte2a_u {
  ************************************************************************/
 
 typedef union ii_iprte2a_u {

-       uint64_t        ii_iprte2a_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :     54;
-               uint64_t        i_widget                  :      4;
-               uint64_t        i_to_cnt                  :      5;
-               uint64_t       i_vld                     :      1;
+       uint64_t ii_iprte2a_regval;
+       struct {
+               uint64_t i_rsvd_1:54;
+               uint64_t i_widget:4;
+               uint64_t i_to_cnt:5;
+               uint64_t i_vld:1;

        } ii_iprte2a_fld_s;
 } ii_iprte2a_u_t;
 
        } ii_iprte2a_fld_s;
 } ii_iprte2a_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprte3a_u {
  ************************************************************************/
 
 typedef union ii_iprte3a_u {

-       uint64_t        ii_iprte3a_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :     54;
-               uint64_t        i_widget                  :      4;
-               uint64_t        i_to_cnt                  :      5;
-               uint64_t        i_vld                     :      1;
+       uint64_t ii_iprte3a_regval;
+       struct {
+               uint64_t i_rsvd_1:54;
+               uint64_t i_widget:4;
+               uint64_t i_to_cnt:5;
+               uint64_t i_vld:1;

        } ii_iprte3a_fld_s;
 } ii_iprte3a_u_t;
 
        } ii_iprte3a_fld_s;
 } ii_iprte3a_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprte4a_u {
  ************************************************************************/
 
 typedef union ii_iprte4a_u {

-       uint64_t        ii_iprte4a_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :     54;
-               uint64_t        i_widget                  :      4;
-               uint64_t        i_to_cnt                  :      5;
-               uint64_t        i_vld                     :      1;
+       uint64_t ii_iprte4a_regval;
+       struct {
+               uint64_t i_rsvd_1:54;
+               uint64_t i_widget:4;
+               uint64_t i_to_cnt:5;
+               uint64_t i_vld:1;

        } ii_iprte4a_fld_s;
 } ii_iprte4a_u_t;
 
        } ii_iprte4a_fld_s;
 } ii_iprte4a_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprte5a_u {
  ************************************************************************/
 
 typedef union ii_iprte5a_u {

-       uint64_t        ii_iprte5a_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :     54;
-               uint64_t        i_widget                  :      4;
-               uint64_t        i_to_cnt                  :      5;
-               uint64_t        i_vld                     :      1;
+       uint64_t ii_iprte5a_regval;
+       struct {
+               uint64_t i_rsvd_1:54;
+               uint64_t i_widget:4;
+               uint64_t i_to_cnt:5;
+               uint64_t i_vld:1;

        } ii_iprte5a_fld_s;
 } ii_iprte5a_u_t;
 
        } ii_iprte5a_fld_s;
 } ii_iprte5a_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprte6a_u {
  ************************************************************************/
 
 typedef union ii_iprte6a_u {

-       uint64_t        ii_iprte6a_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :     54;
-               uint64_t        i_widget                  :      4;
-               uint64_t        i_to_cnt                  :      5;
-               uint64_t        i_vld                     :      1;
+       uint64_t ii_iprte6a_regval;
+       struct {
+               uint64_t i_rsvd_1:54;
+               uint64_t i_widget:4;
+               uint64_t i_to_cnt:5;
+               uint64_t i_vld:1;

        } ii_iprte6a_fld_s;
 } ii_iprte6a_u_t;
 
        } ii_iprte6a_fld_s;
 } ii_iprte6a_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprte7a_u {
  ************************************************************************/
 
 typedef union ii_iprte7a_u {

-        uint64_t       ii_iprte7a_regval;
-        struct  {
-                uint64_t       i_rsvd_1                  :     54;
-                uint64_t       i_widget                  :      4;
-                uint64_t       i_to_cnt                  :      5;
-                uint64_t       i_vld                     :      1;
-        } ii_iprtea7_fld_s;
+       uint64_t ii_iprte7a_regval;
+       struct {
+               uint64_t i_rsvd_1:54;
+               uint64_t i_widget:4;
+               uint64_t i_to_cnt:5;
+               uint64_t i_vld:1;
+       } ii_iprtea7_fld_s;

 } ii_iprte7a_u_t;
 
 } ii_iprte7a_u_t;
 

-
-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
  ************************************************************************/
 

-

 typedef union ii_iprte0b_u {
 typedef union ii_iprte0b_u {

-       uint64_t        ii_iprte0b_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_address                 :     47;
-               uint64_t        i_init                    :      3;
-               uint64_t       i_source                  :     11;
+       uint64_t ii_iprte0b_regval;
+       struct {
+               uint64_t i_rsvd_1:3;
+               uint64_t i_address:47;
+               uint64_t i_init:3;
+               uint64_t i_source:11;

        } ii_iprte0b_fld_s;
 } ii_iprte0b_u_t;
 
        } ii_iprte0b_fld_s;
 } ii_iprte0b_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprte1b_u {
  ************************************************************************/
 
 typedef union ii_iprte1b_u {

-       uint64_t        ii_iprte1b_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_address                 :     47;
-               uint64_t        i_init                    :      3;
-               uint64_t       i_source                  :     11;
+       uint64_t ii_iprte1b_regval;
+       struct {
+               uint64_t i_rsvd_1:3;
+               uint64_t i_address:47;
+               uint64_t i_init:3;
+               uint64_t i_source:11;

        } ii_iprte1b_fld_s;
 } ii_iprte1b_u_t;
 
        } ii_iprte1b_fld_s;
 } ii_iprte1b_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprte2b_u {
  ************************************************************************/
 
 typedef union ii_iprte2b_u {

-       uint64_t        ii_iprte2b_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_address                 :     47;
-               uint64_t        i_init                    :      3;
-               uint64_t       i_source                  :     11;
+       uint64_t ii_iprte2b_regval;
+       struct {
+               uint64_t i_rsvd_1:3;
+               uint64_t i_address:47;
+               uint64_t i_init:3;
+               uint64_t i_source:11;

        } ii_iprte2b_fld_s;
 } ii_iprte2b_u_t;
 
        } ii_iprte2b_fld_s;
 } ii_iprte2b_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprte3b_u {
  ************************************************************************/
 
 typedef union ii_iprte3b_u {

-       uint64_t        ii_iprte3b_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_address                 :     47;
-               uint64_t        i_init                    :      3;
-               uint64_t       i_source                  :     11;
+       uint64_t ii_iprte3b_regval;
+       struct {
+               uint64_t i_rsvd_1:3;
+               uint64_t i_address:47;
+               uint64_t i_init:3;
+               uint64_t i_source:11;

        } ii_iprte3b_fld_s;
 } ii_iprte3b_u_t;
 
        } ii_iprte3b_fld_s;
 } ii_iprte3b_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprte4b_u {
  ************************************************************************/
 
 typedef union ii_iprte4b_u {

-       uint64_t        ii_iprte4b_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_address                 :     47;
-               uint64_t        i_init                    :      3;
-               uint64_t       i_source                  :     11;
+       uint64_t ii_iprte4b_regval;
+       struct {
+               uint64_t i_rsvd_1:3;
+               uint64_t i_address:47;
+               uint64_t i_init:3;
+               uint64_t i_source:11;

        } ii_iprte4b_fld_s;
 } ii_iprte4b_u_t;
 
        } ii_iprte4b_fld_s;
 } ii_iprte4b_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprte5b_u {
  ************************************************************************/
 
 typedef union ii_iprte5b_u {

-       uint64_t        ii_iprte5b_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_address                 :     47;
-               uint64_t        i_init                    :      3;
-               uint64_t       i_source                  :     11;
+       uint64_t ii_iprte5b_regval;
+       struct {
+               uint64_t i_rsvd_1:3;
+               uint64_t i_address:47;
+               uint64_t i_init:3;
+               uint64_t i_source:11;

        } ii_iprte5b_fld_s;
 } ii_iprte5b_u_t;
 
        } ii_iprte5b_fld_s;
 } ii_iprte5b_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprte6b_u {
  ************************************************************************/
 
 typedef union ii_iprte6b_u {

-       uint64_t        ii_iprte6b_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_address                 :     47;
-               uint64_t        i_init                    :      3;
-               uint64_t       i_source                  :     11;
+       uint64_t ii_iprte6b_regval;
+       struct {
+               uint64_t i_rsvd_1:3;
+               uint64_t i_address:47;
+               uint64_t i_init:3;
+               uint64_t i_source:11;

 
        } ii_iprte6b_fld_s;
 } ii_iprte6b_u_t;
 
 
        } ii_iprte6b_fld_s;
 } ii_iprte6b_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *
  *  There are 8 instances of this register. This register contains      *
  * the information that the II has to remember once it has launched a   *
  * PIO Read operation. The contents are used to form the correct        *
  * Router Network packet and direct the Crosstalk reply to the          *
  * appropriate processor.                                               *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iprte7b_u {
  ************************************************************************/
 
 typedef union ii_iprte7b_u {

-        uint64_t       ii_iprte7b_regval;
-        struct  {
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_address                 :     47;
-               uint64_t        i_init                    :      3;
-               uint64_t       i_source                  :     11;
-        } ii_iprte7b_fld_s;
+       uint64_t ii_iprte7b_regval;
+       struct {
+               uint64_t i_rsvd_1:3;
+               uint64_t i_address:47;
+               uint64_t i_init:3;
+               uint64_t i_source:11;
+       } ii_iprte7b_fld_s;

 } ii_iprte7b_u_t;
 
 } ii_iprte7b_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  SHub II contains a feature which did not exist in      *
  * the Hub which automatically cleans up after a Read Response          *
  * timeout, including deallocation of the IPRTE and recovery of IBuf    *
  * Description:  SHub II contains a feature which did not exist in      *
  * the Hub which automatically cleans up after a Read Response          *
  * timeout, including deallocation of the IPRTE and recovery of IBuf    *


@@ -2108,23 +2034,22 @@ typedef union ii_iprte7b_u {
  * Note that this register does not affect the contents of the IPRTE    *
  * registers. The Valid bits in those registers have to be              *
  * specifically turned off by software.                                 *
  * Note that this register does not affect the contents of the IPRTE    *
  * registers. The Valid bits in those registers have to be              *
  * specifically turned off by software.                                 *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ipdr_u {
  ************************************************************************/
 
 typedef union ii_ipdr_u {

-       uint64_t        ii_ipdr_regval;
-       struct  {
-               uint64_t        i_te                      :      3;
-               uint64_t        i_rsvd_1                  :      1;
-               uint64_t        i_pnd                     :      1;
-               uint64_t        i_init_rpcnt              :      1;
-               uint64_t        i_rsvd                    :     58;
+       uint64_t ii_ipdr_regval;
+       struct {
+               uint64_t i_te:3;
+               uint64_t i_rsvd_1:1;
+               uint64_t i_pnd:1;
+               uint64_t i_init_rpcnt:1;
+               uint64_t i_rsvd:58;

        } ii_ipdr_fld_s;
 } ii_ipdr_u_t;
 
        } ii_ipdr_fld_s;
 } ii_ipdr_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  A write to this register causes a CRB entry to be returned to the   *
  * queue of free CRBs. The entry should have previously been cleared    *
  * (mark bit) via backdoor access to the pertinent CRB entry. This      *
  *  A write to this register causes a CRB entry to be returned to the   *
  * queue of free CRBs. The entry should have previously been cleared    *
  * (mark bit) via backdoor access to the pertinent CRB entry. This      *


@@ -2137,21 +2062,20 @@ typedef union ii_ipdr_u {
  * software clears the mark bit, and finally 4) software writes to      *
  * the ICDR register to return the CRB entry to the list of free CRB    *
  * entries.                                                             *
  * software clears the mark bit, and finally 4) software writes to      *
  * the ICDR register to return the CRB entry to the list of free CRB    *
  * entries.                                                             *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_icdr_u {
  ************************************************************************/
 
 typedef union ii_icdr_u {

-       uint64_t        ii_icdr_regval;
-       struct  {
-               uint64_t        i_crb_num                 :      4;
-               uint64_t        i_pnd                     :      1;
-               uint64_t       i_rsvd                    :     59;
+       uint64_t ii_icdr_regval;
+       struct {
+               uint64_t i_crb_num:4;
+               uint64_t i_pnd:1;
+               uint64_t i_rsvd:59;

        } ii_icdr_fld_s;
 } ii_icdr_u_t;
 
        } ii_icdr_fld_s;
 } ii_icdr_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register provides debug access to two FIFOs inside of II.      *
  * Both IOQ_MAX* fields of this register contain the instantaneous      *
  * depth (in units of the number of available entries) of the           *
  *  This register provides debug access to two FIFOs inside of II.      *
  * Both IOQ_MAX* fields of this register contain the instantaneous      *
  * depth (in units of the number of available entries) of the           *


@@ -2164,130 +2088,124 @@ typedef union ii_icdr_u {
  * this register is written. If there are any active entries in any     *
  * of these FIFOs when this register is written, the results are        *
  * undefined.                                                           *
  * this register is written. If there are any active entries in any     *
  * of these FIFOs when this register is written, the results are        *
  * undefined.                                                           *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ifdr_u {
  ************************************************************************/
 
 typedef union ii_ifdr_u {

-       uint64_t        ii_ifdr_regval;
-       struct  {
-               uint64_t        i_ioq_max_rq              :      7;
-               uint64_t        i_set_ioq_rq              :      1;
-               uint64_t        i_ioq_max_rp              :      7;
-               uint64_t        i_set_ioq_rp              :      1;
-               uint64_t        i_rsvd                    :     48;
+       uint64_t ii_ifdr_regval;
+       struct {
+               uint64_t i_ioq_max_rq:7;
+               uint64_t i_set_ioq_rq:1;
+               uint64_t i_ioq_max_rp:7;
+               uint64_t i_set_ioq_rp:1;
+               uint64_t i_rsvd:48;

        } ii_ifdr_fld_s;
 } ii_ifdr_u_t;
 
        } ii_ifdr_fld_s;
 } ii_ifdr_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register allows the II to become sluggish in removing          *
  * messages from its inbound queue (IIQ). This will cause messages to   *
  * back up in either virtual channel. Disabling the "molasses" mode     *
  * subsequently allows the II to be tested under stress. In the         *
  * sluggish ("Molasses") mode, the localized effects of congestion      *
  * can be observed.                                                     *
  *  This register allows the II to become sluggish in removing          *
  * messages from its inbound queue (IIQ). This will cause messages to   *
  * back up in either virtual channel. Disabling the "molasses" mode     *
  * subsequently allows the II to be tested under stress. In the         *
  * sluggish ("Molasses") mode, the localized effects of congestion      *
  * can be observed.                                                     *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iiap_u {
  ************************************************************************/
 
 typedef union ii_iiap_u {

-        uint64_t       ii_iiap_regval;
-        struct  {
-                uint64_t       i_rq_mls                  :      6;
-               uint64_t        i_rsvd_1                  :      2;
-               uint64_t        i_rp_mls                  :      6;
-               uint64_t       i_rsvd                    :     50;
-        } ii_iiap_fld_s;
+       uint64_t ii_iiap_regval;
+       struct {
+               uint64_t i_rq_mls:6;
+               uint64_t i_rsvd_1:2;
+               uint64_t i_rp_mls:6;
+               uint64_t i_rsvd:50;
+       } ii_iiap_fld_s;

 } ii_iiap_u_t;
 
 } ii_iiap_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register allows several parameters of CRB operation to be      *
  * set. Note that writing to this register can have catastrophic side   *
  * effects, if the CRB is not quiescent, i.e. if the CRB is             *
  * processing protocol messages when the write occurs.                  *
  *  This register allows several parameters of CRB operation to be      *
  * set. Note that writing to this register can have catastrophic side   *
  * effects, if the CRB is not quiescent, i.e. if the CRB is             *
  * processing protocol messages when the write occurs.                  *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_icmr_u {
  ************************************************************************/
 
 typedef union ii_icmr_u {

-       uint64_t        ii_icmr_regval;
-       struct  {
-               uint64_t        i_sp_msg                  :      1;
-               uint64_t        i_rd_hdr                  :      1;
-               uint64_t        i_rsvd_4                  :      2;
-               uint64_t        i_c_cnt                   :      4;
-               uint64_t        i_rsvd_3                  :      4;
-               uint64_t        i_clr_rqpd                :      1;
-               uint64_t        i_clr_rppd                :      1;
-               uint64_t        i_rsvd_2                  :      2;
-               uint64_t        i_fc_cnt                  :      4;
-               uint64_t        i_crb_vld                 :     15;
-               uint64_t        i_crb_mark                :     15;
-               uint64_t        i_rsvd_1                  :      2;
-               uint64_t        i_precise                 :      1;
-               uint64_t        i_rsvd                    :     11;
+       uint64_t ii_icmr_regval;
+       struct {
+               uint64_t i_sp_msg:1;
+               uint64_t i_rd_hdr:1;
+               uint64_t i_rsvd_4:2;
+               uint64_t i_c_cnt:4;
+               uint64_t i_rsvd_3:4;
+               uint64_t i_clr_rqpd:1;
+               uint64_t i_clr_rppd:1;
+               uint64_t i_rsvd_2:2;
+               uint64_t i_fc_cnt:4;
+               uint64_t i_crb_vld:15;
+               uint64_t i_crb_mark:15;
+               uint64_t i_rsvd_1:2;
+               uint64_t i_precise:1;
+               uint64_t i_rsvd:11;

        } ii_icmr_fld_s;
 } ii_icmr_u_t;
 
        } ii_icmr_fld_s;
 } ii_icmr_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register allows control of the table portion of the CRB        *
  * logic via software. Control operations from this register have       *
  * priority over all incoming Crosstalk or BTE requests.                *
  *  This register allows control of the table portion of the CRB        *
  * logic via software. Control operations from this register have       *
  * priority over all incoming Crosstalk or BTE requests.                *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_iccr_u {
  ************************************************************************/
 
 typedef union ii_iccr_u {

-       uint64_t        ii_iccr_regval;
-       struct  {
-               uint64_t        i_crb_num                 :      4;
-               uint64_t        i_rsvd_1                  :      4;
-               uint64_t        i_cmd                     :      8;
-               uint64_t        i_pending                 :      1;
-               uint64_t        i_rsvd                    :     47;
+       uint64_t ii_iccr_regval;
+       struct {
+               uint64_t i_crb_num:4;
+               uint64_t i_rsvd_1:4;
+               uint64_t i_cmd:8;
+               uint64_t i_pending:1;
+               uint64_t i_rsvd:47;

        } ii_iccr_fld_s;
 } ii_iccr_u_t;
 
        } ii_iccr_fld_s;
 } ii_iccr_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register allows the maximum timeout value to be programmed.    *
  *  This register allows the maximum timeout value to be programmed.    *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_icto_u {
  ************************************************************************/
 
 typedef union ii_icto_u {

-       uint64_t        ii_icto_regval;
-       struct  {
-               uint64_t        i_timeout                 :      8;
-               uint64_t        i_rsvd                    :     56;
+       uint64_t ii_icto_regval;
+       struct {
+               uint64_t i_timeout:8;
+               uint64_t i_rsvd:56;

        } ii_icto_fld_s;
 } ii_icto_u_t;
 
        } ii_icto_fld_s;
 } ii_icto_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register allows the timeout prescalar to be programmed. An     *
  * internal counter is associated with this register. When the          *
  * internal counter reaches the value of the PRESCALE field, the        *
  * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT]   *
  * field). The internal counter resets to zero, and then continues      *
  * counting.                                                            *
  *  This register allows the timeout prescalar to be programmed. An     *
  * internal counter is associated with this register. When the          *
  * internal counter reaches the value of the PRESCALE field, the        *
  * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT]   *
  * field). The internal counter resets to zero, and then continues      *
  * counting.                                                            *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ictp_u {
  ************************************************************************/
 
 typedef union ii_ictp_u {

-       uint64_t        ii_ictp_regval;
-       struct  {
-               uint64_t        i_prescale                :     24;
-               uint64_t        i_rsvd                    :     40;
+       uint64_t ii_ictp_regval;
+       struct {
+               uint64_t i_prescale:24;
+               uint64_t i_rsvd:40;

        } ii_ictp_fld_s;
 } ii_ictp_u_t;
 
        } ii_ictp_fld_s;
 } ii_ictp_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *
  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *


@@ -2306,243 +2224,234 @@ typedef union ii_ictp_u {
  * recovering any potential error state from before the reset).         *
  * The following four tables summarize the format for the four          *
  * registers that are used for each ICRB# Entry.                        *
  * recovering any potential error state from before the reset).         *
  * The following four tables summarize the format for the four          *
  * registers that are used for each ICRB# Entry.                        *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_icrb0_a_u {
  ************************************************************************/
 
 typedef union ii_icrb0_a_u {

-       uint64_t        ii_icrb0_a_regval;
-       struct  {
-               uint64_t        ia_iow                    :      1;
-               uint64_t        ia_vld                    :      1;
-               uint64_t        ia_addr                   :     47;
-               uint64_t        ia_tnum                   :      5;
-               uint64_t        ia_sidn                   :      4;
-               uint64_t       ia_rsvd                   :      6;
+       uint64_t ii_icrb0_a_regval;
+       struct {
+               uint64_t ia_iow:1;
+               uint64_t ia_vld:1;
+               uint64_t ia_addr:47;
+               uint64_t ia_tnum:5;
+               uint64_t ia_sidn:4;
+               uint64_t ia_rsvd:6;

        } ii_icrb0_a_fld_s;
 } ii_icrb0_a_u_t;
 
        } ii_icrb0_a_fld_s;
 } ii_icrb0_a_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *
  * registers (_A to _E) are required to read and write each entry.      *
  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *
  * registers (_A to _E) are required to read and write each entry.      *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_icrb0_b_u {
  ************************************************************************/
 
 typedef union ii_icrb0_b_u {

-       uint64_t        ii_icrb0_b_regval;
-       struct  {
-               uint64_t        ib_xt_err                 :      1;
-               uint64_t        ib_mark                   :      1;
-               uint64_t        ib_ln_uce                 :      1;
-               uint64_t        ib_errcode                :      3;
-               uint64_t        ib_error                  :      1;
-               uint64_t        ib_stall__bte_1           :      1;
-               uint64_t        ib_stall__bte_0           :      1;
-               uint64_t        ib_stall__intr            :      1;
-               uint64_t        ib_stall_ib               :      1;
-               uint64_t        ib_intvn                  :      1;
-               uint64_t        ib_wb                     :      1;
-               uint64_t        ib_hold                   :      1;
-               uint64_t        ib_ack                    :      1;
-               uint64_t        ib_resp                   :      1;
-               uint64_t        ib_ack_cnt                :     11;
-               uint64_t        ib_rsvd                   :      7;
-               uint64_t        ib_exc                    :      5;
-               uint64_t        ib_init                   :      3;
-               uint64_t        ib_imsg                   :      8;
-               uint64_t        ib_imsgtype               :      2;
-               uint64_t        ib_use_old                :      1;
-               uint64_t        ib_rsvd_1                 :     11;
+       uint64_t ii_icrb0_b_regval;
+       struct {
+               uint64_t ib_xt_err:1;
+               uint64_t ib_mark:1;
+               uint64_t ib_ln_uce:1;
+               uint64_t ib_errcode:3;
+               uint64_t ib_error:1;
+               uint64_t ib_stall__bte_1:1;
+               uint64_t ib_stall__bte_0:1;
+               uint64_t ib_stall__intr:1;
+               uint64_t ib_stall_ib:1;
+               uint64_t ib_intvn:1;
+               uint64_t ib_wb:1;
+               uint64_t ib_hold:1;
+               uint64_t ib_ack:1;
+               uint64_t ib_resp:1;
+               uint64_t ib_ack_cnt:11;
+               uint64_t ib_rsvd:7;
+               uint64_t ib_exc:5;
+               uint64_t ib_init:3;
+               uint64_t ib_imsg:8;
+               uint64_t ib_imsgtype:2;
+               uint64_t ib_use_old:1;
+               uint64_t ib_rsvd_1:11;

        } ii_icrb0_b_fld_s;
 } ii_icrb0_b_u_t;
 
        } ii_icrb0_b_fld_s;
 } ii_icrb0_b_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *
  * registers (_A to _E) are required to read and write each entry.      *
  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *
  * registers (_A to _E) are required to read and write each entry.      *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_icrb0_c_u {
  ************************************************************************/
 
 typedef union ii_icrb0_c_u {

-       uint64_t        ii_icrb0_c_regval;
-       struct  {
-               uint64_t        ic_source                 :     15;
-               uint64_t        ic_size                   :      2;
-               uint64_t        ic_ct                     :      1;
-               uint64_t        ic_bte_num                :      1;
-               uint64_t        ic_gbr                    :      1;
-               uint64_t        ic_resprqd                :      1;
-               uint64_t        ic_bo                     :      1;
-               uint64_t        ic_suppl                  :     15;
-               uint64_t        ic_rsvd                   :     27;
+       uint64_t ii_icrb0_c_regval;
+       struct {
+               uint64_t ic_source:15;
+               uint64_t ic_size:2;
+               uint64_t ic_ct:1;
+               uint64_t ic_bte_num:1;
+               uint64_t ic_gbr:1;
+               uint64_t ic_resprqd:1;
+               uint64_t ic_bo:1;
+               uint64_t ic_suppl:15;
+               uint64_t ic_rsvd:27;

        } ii_icrb0_c_fld_s;
 } ii_icrb0_c_u_t;
 
        } ii_icrb0_c_fld_s;
 } ii_icrb0_c_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *
  * registers (_A to _E) are required to read and write each entry.      *
  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *
  * registers (_A to _E) are required to read and write each entry.      *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_icrb0_d_u {
  ************************************************************************/
 
 typedef union ii_icrb0_d_u {

-       uint64_t        ii_icrb0_d_regval;
-       struct  {
-               uint64_t        id_pa_be                  :     43;
-               uint64_t        id_bte_op                 :      1;
-               uint64_t        id_pr_psc                 :      4;
-               uint64_t        id_pr_cnt                 :      4;
-               uint64_t        id_sleep                  :      1;
-               uint64_t        id_rsvd                   :     11;
+       uint64_t ii_icrb0_d_regval;
+       struct {
+               uint64_t id_pa_be:43;
+               uint64_t id_bte_op:1;
+               uint64_t id_pr_psc:4;
+               uint64_t id_pr_cnt:4;
+               uint64_t id_sleep:1;
+               uint64_t id_rsvd:11;

        } ii_icrb0_d_fld_s;
 } ii_icrb0_d_u_t;
 
        } ii_icrb0_d_fld_s;
 } ii_icrb0_d_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *
  * registers (_A to _E) are required to read and write each entry.      *
  * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
  * used for Crosstalk operations (both cacheline and partial            *
  * operations) or BTE/IO. Because the CRB entries are very wide, five   *
  * registers (_A to _E) are required to read and write each entry.      *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_icrb0_e_u {
  ************************************************************************/
 
 typedef union ii_icrb0_e_u {

-       uint64_t        ii_icrb0_e_regval;
-       struct  {
-               uint64_t        ie_timeout                :      8;
-               uint64_t        ie_context                :     15;
-               uint64_t        ie_rsvd                   :      1;
-               uint64_t        ie_tvld                   :      1;
-               uint64_t        ie_cvld                   :      1;
-               uint64_t        ie_rsvd_0                 :     38;
+       uint64_t ii_icrb0_e_regval;
+       struct {
+               uint64_t ie_timeout:8;
+               uint64_t ie_context:15;
+               uint64_t ie_rsvd:1;
+               uint64_t ie_tvld:1;
+               uint64_t ie_cvld:1;
+               uint64_t ie_rsvd_0:38;

        } ii_icrb0_e_fld_s;
 } ii_icrb0_e_u_t;
 
        } ii_icrb0_e_fld_s;
 } ii_icrb0_e_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register contains the lower 64 bits of the header of the       *
  * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
  * register is set.                                                     *
  *  This register contains the lower 64 bits of the header of the       *
  * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
  * register is set.                                                     *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_icsml_u {
  ************************************************************************/
 
 typedef union ii_icsml_u {

-       uint64_t        ii_icsml_regval;
-       struct  {
-               uint64_t        i_tt_addr                 :     47;
-               uint64_t        i_newsuppl_ex             :     14;
-               uint64_t        i_reserved                :      2;
-               uint64_t       i_overflow                :      1;
+       uint64_t ii_icsml_regval;
+       struct {
+               uint64_t i_tt_addr:47;
+               uint64_t i_newsuppl_ex:14;
+               uint64_t i_reserved:2;
+               uint64_t i_overflow:1;

        } ii_icsml_fld_s;
 } ii_icsml_u_t;
 
        } ii_icsml_fld_s;
 } ii_icsml_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register contains the middle 64 bits of the header of the      *
  * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
  * register is set.                                                     *
  *  This register contains the middle 64 bits of the header of the      *
  * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
  * register is set.                                                     *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_icsmm_u {
  ************************************************************************/
 
 typedef union ii_icsmm_u {

-       uint64_t        ii_icsmm_regval;
-       struct  {
-               uint64_t        i_tt_ack_cnt              :     11;
-               uint64_t        i_reserved                :     53;
+       uint64_t ii_icsmm_regval;
+       struct {
+               uint64_t i_tt_ack_cnt:11;
+               uint64_t i_reserved:53;

        } ii_icsmm_fld_s;
 } ii_icsmm_u_t;
 
        } ii_icsmm_fld_s;
 } ii_icsmm_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register contains the microscopic state, all the inputs to     *
  * the protocol table, captured with the spurious message. Valid when   *
  * the SP_MSG bit in the ICMR register is set.                          *
  *  This register contains the microscopic state, all the inputs to     *
  * the protocol table, captured with the spurious message. Valid when   *
  * the SP_MSG bit in the ICMR register is set.                          *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_icsmh_u {
  ************************************************************************/
 
 typedef union ii_icsmh_u {

-       uint64_t        ii_icsmh_regval;
-       struct  {
-               uint64_t        i_tt_vld                  :      1;
-               uint64_t        i_xerr                    :      1;
-               uint64_t        i_ft_cwact_o              :      1;
-               uint64_t        i_ft_wact_o               :      1;
-               uint64_t       i_ft_active_o             :      1;
-               uint64_t        i_sync                    :      1;
-               uint64_t        i_mnusg                   :      1;
-               uint64_t        i_mnusz                   :      1;
-               uint64_t        i_plusz                   :      1;
-               uint64_t        i_plusg                   :      1;
-               uint64_t        i_tt_exc                  :      5;
-               uint64_t        i_tt_wb                   :      1;
-               uint64_t        i_tt_hold                 :      1;
-               uint64_t        i_tt_ack                  :      1;
-               uint64_t        i_tt_resp                 :      1;
-               uint64_t        i_tt_intvn                :      1;
-               uint64_t        i_g_stall_bte1            :      1;
-               uint64_t        i_g_stall_bte0            :      1;
-               uint64_t        i_g_stall_il              :      1;
-               uint64_t        i_g_stall_ib              :      1;
-               uint64_t        i_tt_imsg                 :      8;
-               uint64_t        i_tt_imsgtype             :      2;
-               uint64_t        i_tt_use_old              :      1;
-               uint64_t        i_tt_respreqd             :      1;
-               uint64_t        i_tt_bte_num              :      1;
-               uint64_t        i_cbn                     :      1;
-               uint64_t        i_match                   :      1;
-               uint64_t        i_rpcnt_lt_34             :      1;
-               uint64_t        i_rpcnt_ge_34             :      1;
-               uint64_t        i_rpcnt_lt_18             :      1;
-               uint64_t        i_rpcnt_ge_18             :      1;
-               uint64_t       i_rpcnt_lt_2              :      1;
-               uint64_t        i_rpcnt_ge_2              :      1;
-               uint64_t        i_rqcnt_lt_18             :      1;
-               uint64_t        i_rqcnt_ge_18             :      1;
-               uint64_t        i_rqcnt_lt_2              :      1;
-               uint64_t        i_rqcnt_ge_2              :      1;
-               uint64_t        i_tt_device               :      7;
-               uint64_t        i_tt_init                 :      3;
-               uint64_t        i_reserved                :      5;
+       uint64_t ii_icsmh_regval;
+       struct {
+               uint64_t i_tt_vld:1;
+               uint64_t i_xerr:1;
+               uint64_t i_ft_cwact_o:1;
+               uint64_t i_ft_wact_o:1;
+               uint64_t i_ft_active_o:1;
+               uint64_t i_sync:1;
+               uint64_t i_mnusg:1;
+               uint64_t i_mnusz:1;
+               uint64_t i_plusz:1;
+               uint64_t i_plusg:1;
+               uint64_t i_tt_exc:5;
+               uint64_t i_tt_wb:1;
+               uint64_t i_tt_hold:1;
+               uint64_t i_tt_ack:1;
+               uint64_t i_tt_resp:1;
+               uint64_t i_tt_intvn:1;
+               uint64_t i_g_stall_bte1:1;
+               uint64_t i_g_stall_bte0:1;
+               uint64_t i_g_stall_il:1;
+               uint64_t i_g_stall_ib:1;
+               uint64_t i_tt_imsg:8;
+               uint64_t i_tt_imsgtype:2;
+               uint64_t i_tt_use_old:1;
+               uint64_t i_tt_respreqd:1;
+               uint64_t i_tt_bte_num:1;
+               uint64_t i_cbn:1;
+               uint64_t i_match:1;
+               uint64_t i_rpcnt_lt_34:1;
+               uint64_t i_rpcnt_ge_34:1;
+               uint64_t i_rpcnt_lt_18:1;
+               uint64_t i_rpcnt_ge_18:1;
+               uint64_t i_rpcnt_lt_2:1;
+               uint64_t i_rpcnt_ge_2:1;
+               uint64_t i_rqcnt_lt_18:1;
+               uint64_t i_rqcnt_ge_18:1;
+               uint64_t i_rqcnt_lt_2:1;
+               uint64_t i_rqcnt_ge_2:1;
+               uint64_t i_tt_device:7;
+               uint64_t i_tt_init:3;
+               uint64_t i_reserved:5;

        } ii_icsmh_fld_s;
 } ii_icsmh_u_t;
 
        } ii_icsmh_fld_s;
 } ii_icsmh_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  The Shub DEBUG unit provides a 3-bit selection signal to the        *
  * II core and a 3-bit selection signal to the fsbclk domain in the II  *
  * wrapper.                                                             *
  *  The Shub DEBUG unit provides a 3-bit selection signal to the        *
  * II core and a 3-bit selection signal to the fsbclk domain in the II  *
  * wrapper.                                                             *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_idbss_u {
  ************************************************************************/
 
 typedef union ii_idbss_u {

-       uint64_t        ii_idbss_regval;
-       struct  {
-               uint64_t        i_iioclk_core_submenu     :      3;
-               uint64_t        i_rsvd                    :      5;
-               uint64_t        i_fsbclk_wrapper_submenu  :      3;
-               uint64_t        i_rsvd_1                  :      5;
-               uint64_t        i_iioclk_menu             :      5;
-               uint64_t        i_rsvd_2                  :     43;
+       uint64_t ii_idbss_regval;
+       struct {
+               uint64_t i_iioclk_core_submenu:3;
+               uint64_t i_rsvd:5;
+               uint64_t i_fsbclk_wrapper_submenu:3;
+               uint64_t i_rsvd_1:5;
+               uint64_t i_iioclk_menu:5;
+               uint64_t i_rsvd_2:43;

        } ii_idbss_fld_s;
 } ii_idbss_u_t;
 
        } ii_idbss_fld_s;
 } ii_idbss_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  This register is used to set up the length for a       *
  * transfer and then to monitor the progress of that transfer. This     *
  * register needs to be initialized before a transfer is started. A     *
  * Description:  This register is used to set up the length for a       *
  * transfer and then to monitor the progress of that transfer. This     *
  * register needs to be initialized before a transfer is started. A     *


@@ -2553,63 +2462,60 @@ typedef union ii_idbss_u {
  * transfer completes, hardware will clear the Busy bit. The length     *
  * field will also contain the number of cache lines left to be         *
  * transferred.                                                         *
  * transfer completes, hardware will clear the Busy bit. The length     *
  * field will also contain the number of cache lines left to be         *
  * transferred.                                                         *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ibls0_u {
  ************************************************************************/
 
 typedef union ii_ibls0_u {

-       uint64_t        ii_ibls0_regval;
-       struct  {
-               uint64_t        i_length                  :     16;
-               uint64_t        i_error                   :      1;
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_busy                    :      1;
-               uint64_t       i_rsvd                    :     43;
+       uint64_t ii_ibls0_regval;
+       struct {
+               uint64_t i_length:16;
+               uint64_t i_error:1;
+               uint64_t i_rsvd_1:3;
+               uint64_t i_busy:1;
+               uint64_t i_rsvd:43;

        } ii_ibls0_fld_s;
 } ii_ibls0_u_t;
 
        } ii_ibls0_fld_s;
 } ii_ibls0_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register should be loaded before a transfer is started. The    *
  * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
  * address as described in Section 1.3, Figure2 and Figure3. Since      *
  * the bottom 7 bits of the address are always taken to be zero, BTE    *
  * transfers are always cacheline-aligned.                              *
  *  This register should be loaded before a transfer is started. The    *
  * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
  * address as described in Section 1.3, Figure2 and Figure3. Since      *
  * the bottom 7 bits of the address are always taken to be zero, BTE    *
  * transfers are always cacheline-aligned.                              *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ibsa0_u {
  ************************************************************************/
 
 typedef union ii_ibsa0_u {

-       uint64_t        ii_ibsa0_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :      7;
-               uint64_t        i_addr                    :     42;
-               uint64_t       i_rsvd                    :     15;
+       uint64_t ii_ibsa0_regval;
+       struct {
+               uint64_t i_rsvd_1:7;
+               uint64_t i_addr:42;
+               uint64_t i_rsvd:15;

        } ii_ibsa0_fld_s;
 } ii_ibsa0_u_t;
 
        } ii_ibsa0_fld_s;
 } ii_ibsa0_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register should be loaded before a transfer is started. The    *
  * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
  * address as described in Section 1.3, Figure2 and Figure3. Since      *
  * the bottom 7 bits of the address are always taken to be zero, BTE    *
  * transfers are always cacheline-aligned.                              *
  *  This register should be loaded before a transfer is started. The    *
  * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
  * address as described in Section 1.3, Figure2 and Figure3. Since      *
  * the bottom 7 bits of the address are always taken to be zero, BTE    *
  * transfers are always cacheline-aligned.                              *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ibda0_u {
  ************************************************************************/
 
 typedef union ii_ibda0_u {

-       uint64_t        ii_ibda0_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :      7;
-               uint64_t        i_addr                    :     42;
-               uint64_t        i_rsvd                    :     15;
+       uint64_t ii_ibda0_regval;
+       struct {
+               uint64_t i_rsvd_1:7;
+               uint64_t i_addr:42;
+               uint64_t i_rsvd:15;

        } ii_ibda0_fld_s;
 } ii_ibda0_u_t;
 
        } ii_ibda0_fld_s;
 } ii_ibda0_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  Writing to this register sets up the attributes of the transfer     *
  * and initiates the transfer operation. Reading this register has      *
  * the side effect of terminating any transfer in progress. Note:       *
  *  Writing to this register sets up the attributes of the transfer     *
  * and initiates the transfer operation. Reading this register has      *
  * the side effect of terminating any transfer in progress. Note:       *


@@ -2617,61 +2523,58 @@ typedef union ii_ibda0_u {
  * other BTE. If a BTE stream has to be stopped (due to error           *
  * handling for example), both BTE streams should be stopped and        *
  * their transfers discarded.                                           *
  * other BTE. If a BTE stream has to be stopped (due to error           *
  * handling for example), both BTE streams should be stopped and        *
  * their transfers discarded.                                           *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ibct0_u {
  ************************************************************************/
 
 typedef union ii_ibct0_u {

-       uint64_t        ii_ibct0_regval;
-       struct  {
-               uint64_t        i_zerofill                :      1;
-               uint64_t        i_rsvd_2                  :      3;
-               uint64_t        i_notify                  :      1;
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t       i_poison                  :      1;
-               uint64_t       i_rsvd                    :     55;
+       uint64_t ii_ibct0_regval;
+       struct {
+               uint64_t i_zerofill:1;
+               uint64_t i_rsvd_2:3;
+               uint64_t i_notify:1;
+               uint64_t i_rsvd_1:3;
+               uint64_t i_poison:1;
+               uint64_t i_rsvd:55;

        } ii_ibct0_fld_s;
 } ii_ibct0_u_t;
 
        } ii_ibct0_fld_s;
 } ii_ibct0_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register contains the address to which the WINV is sent.       *
  * This address has to be cache line aligned.                           *
  *  This register contains the address to which the WINV is sent.       *
  * This address has to be cache line aligned.                           *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ibna0_u {
  ************************************************************************/
 
 typedef union ii_ibna0_u {

-       uint64_t        ii_ibna0_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :      7;
-               uint64_t        i_addr                    :     42;
-               uint64_t        i_rsvd                    :     15;
+       uint64_t ii_ibna0_regval;
+       struct {
+               uint64_t i_rsvd_1:7;
+               uint64_t i_addr:42;
+               uint64_t i_rsvd:15;

        } ii_ibna0_fld_s;
 } ii_ibna0_u_t;
 
        } ii_ibna0_fld_s;
 } ii_ibna0_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register contains the programmable level as well as the node   *
  * ID and PI unit of the processor to which the interrupt will be       *
  *  This register contains the programmable level as well as the node   *
  * ID and PI unit of the processor to which the interrupt will be       *

- * sent.                                                                *
- *                                                                      *
+ * sent.                                                               *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ibia0_u {
  ************************************************************************/
 
 typedef union ii_ibia0_u {

-       uint64_t        ii_ibia0_regval;
-       struct  {
-               uint64_t        i_rsvd_2                   :     1;
-               uint64_t        i_node_id                 :     11;
-               uint64_t        i_rsvd_1                  :      4;
-               uint64_t        i_level                   :      7;
-               uint64_t       i_rsvd                    :     41;
+       uint64_t ii_ibia0_regval;
+       struct {
+               uint64_t i_rsvd_2:1;
+               uint64_t i_node_id:11;
+               uint64_t i_rsvd_1:4;
+               uint64_t i_level:7;
+               uint64_t i_rsvd:41;

        } ii_ibia0_fld_s;
 } ii_ibia0_u_t;
 
        } ii_ibia0_fld_s;
 } ii_ibia0_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  * Description:  This register is used to set up the length for a       *
  * transfer and then to monitor the progress of that transfer. This     *
  * register needs to be initialized before a transfer is started. A     *
  * Description:  This register is used to set up the length for a       *
  * transfer and then to monitor the progress of that transfer. This     *
  * register needs to be initialized before a transfer is started. A     *


@@ -2682,63 +2585,60 @@ typedef union ii_ibia0_u {
  * transfer completes, hardware will clear the Busy bit. The length     *
  * field will also contain the number of cache lines left to be         *
  * transferred.                                                         *
  * transfer completes, hardware will clear the Busy bit. The length     *
  * field will also contain the number of cache lines left to be         *
  * transferred.                                                         *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ibls1_u {
  ************************************************************************/
 
 typedef union ii_ibls1_u {

-       uint64_t        ii_ibls1_regval;
-       struct  {
-               uint64_t        i_length                  :     16;
-               uint64_t        i_error                   :      1;
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_busy                    :      1;
-               uint64_t       i_rsvd                    :     43;
+       uint64_t ii_ibls1_regval;
+       struct {
+               uint64_t i_length:16;
+               uint64_t i_error:1;
+               uint64_t i_rsvd_1:3;
+               uint64_t i_busy:1;
+               uint64_t i_rsvd:43;

        } ii_ibls1_fld_s;
 } ii_ibls1_u_t;
 
        } ii_ibls1_fld_s;
 } ii_ibls1_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register should be loaded before a transfer is started. The    *
  * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
  * address as described in Section 1.3, Figure2 and Figure3. Since      *
  * the bottom 7 bits of the address are always taken to be zero, BTE    *
  * transfers are always cacheline-aligned.                              *
  *  This register should be loaded before a transfer is started. The    *
  * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
  * address as described in Section 1.3, Figure2 and Figure3. Since      *
  * the bottom 7 bits of the address are always taken to be zero, BTE    *
  * transfers are always cacheline-aligned.                              *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ibsa1_u {
  ************************************************************************/
 
 typedef union ii_ibsa1_u {

-       uint64_t        ii_ibsa1_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :      7;
-               uint64_t        i_addr                    :     33;
-               uint64_t        i_rsvd                    :     24;
+       uint64_t ii_ibsa1_regval;
+       struct {
+               uint64_t i_rsvd_1:7;
+               uint64_t i_addr:33;
+               uint64_t i_rsvd:24;

        } ii_ibsa1_fld_s;
 } ii_ibsa1_u_t;
 
        } ii_ibsa1_fld_s;
 } ii_ibsa1_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register should be loaded before a transfer is started. The    *
  * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
  * address as described in Section 1.3, Figure2 and Figure3. Since      *
  * the bottom 7 bits of the address are always taken to be zero, BTE    *
  * transfers are always cacheline-aligned.                              *
  *  This register should be loaded before a transfer is started. The    *
  * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
  * address as described in Section 1.3, Figure2 and Figure3. Since      *
  * the bottom 7 bits of the address are always taken to be zero, BTE    *
  * transfers are always cacheline-aligned.                              *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ibda1_u {
  ************************************************************************/
 
 typedef union ii_ibda1_u {

-       uint64_t        ii_ibda1_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :      7;
-               uint64_t        i_addr                    :     33;
-               uint64_t        i_rsvd                    :     24;
+       uint64_t ii_ibda1_regval;
+       struct {
+               uint64_t i_rsvd_1:7;
+               uint64_t i_addr:33;
+               uint64_t i_rsvd:24;

        } ii_ibda1_fld_s;
 } ii_ibda1_u_t;
 
        } ii_ibda1_fld_s;
 } ii_ibda1_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  Writing to this register sets up the attributes of the transfer     *
  * and initiates the transfer operation. Reading this register has      *
  * the side effect of terminating any transfer in progress. Note:       *
  *  Writing to this register sets up the attributes of the transfer     *
  * and initiates the transfer operation. Reading this register has      *
  * the side effect of terminating any transfer in progress. Note:       *


@@ -2746,61 +2646,58 @@ typedef union ii_ibda1_u {
  * other BTE. If a BTE stream has to be stopped (due to error           *
  * handling for example), both BTE streams should be stopped and        *
  * their transfers discarded.                                           *
  * other BTE. If a BTE stream has to be stopped (due to error           *
  * handling for example), both BTE streams should be stopped and        *
  * their transfers discarded.                                           *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ibct1_u {
  ************************************************************************/
 
 typedef union ii_ibct1_u {

-       uint64_t        ii_ibct1_regval;
-       struct  {
-               uint64_t        i_zerofill                :      1;
-               uint64_t        i_rsvd_2                  :      3;
-               uint64_t        i_notify                  :      1;
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_poison                  :      1;
-               uint64_t        i_rsvd                    :     55;
+       uint64_t ii_ibct1_regval;
+       struct {
+               uint64_t i_zerofill:1;
+               uint64_t i_rsvd_2:3;
+               uint64_t i_notify:1;
+               uint64_t i_rsvd_1:3;
+               uint64_t i_poison:1;
+               uint64_t i_rsvd:55;

        } ii_ibct1_fld_s;
 } ii_ibct1_u_t;
 
        } ii_ibct1_fld_s;
 } ii_ibct1_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register contains the address to which the WINV is sent.       *
  * This address has to be cache line aligned.                           *
  *  This register contains the address to which the WINV is sent.       *
  * This address has to be cache line aligned.                           *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ibna1_u {
  ************************************************************************/
 
 typedef union ii_ibna1_u {

-       uint64_t        ii_ibna1_regval;
-       struct  {
-               uint64_t        i_rsvd_1                  :      7;
-               uint64_t        i_addr                    :     33;
-               uint64_t       i_rsvd                    :     24;
+       uint64_t ii_ibna1_regval;
+       struct {
+               uint64_t i_rsvd_1:7;
+               uint64_t i_addr:33;
+               uint64_t i_rsvd:24;

        } ii_ibna1_fld_s;
 } ii_ibna1_u_t;
 
        } ii_ibna1_fld_s;
 } ii_ibna1_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register contains the programmable level as well as the node   *
  * ID and PI unit of the processor to which the interrupt will be       *
  *  This register contains the programmable level as well as the node   *
  * ID and PI unit of the processor to which the interrupt will be       *

- * sent.                                                                *
- *                                                                      *
+ * sent.                                                               *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ibia1_u {
  ************************************************************************/
 
 typedef union ii_ibia1_u {

-       uint64_t        ii_ibia1_regval;
-       struct  {
-               uint64_t        i_pi_id                   :      1;
-               uint64_t        i_node_id                 :      8;
-               uint64_t        i_rsvd_1                  :      7;
-               uint64_t        i_level                   :      7;
-               uint64_t        i_rsvd                    :     41;
+       uint64_t ii_ibia1_regval;
+       struct {
+               uint64_t i_pi_id:1;
+               uint64_t i_node_id:8;
+               uint64_t i_rsvd_1:7;
+               uint64_t i_level:7;
+               uint64_t i_rsvd:41;

        } ii_ibia1_fld_s;
 } ii_ibia1_u_t;
 
        } ii_ibia1_fld_s;
 } ii_ibia1_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
+ *                                                                     *

  *  This register defines the resources that feed information into      *
  * the two performance counters located in the IO Performance           *
  * Profiling Register. There are 17 different quantities that can be    *
  *  This register defines the resources that feed information into      *
  * the two performance counters located in the IO Performance           *
  * Profiling Register. There are 17 different quantities that can be    *


@@ -2811,133 +2708,129 @@ typedef union ii_ibia1_u {
  * other is available from the other performance counter. Hence, the    *
  * II supports all 17*16=272 possible combinations of quantities to     *
  * measure.                                                             *
  * other is available from the other performance counter. Hence, the    *
  * II supports all 17*16=272 possible combinations of quantities to     *
  * measure.                                                             *

- *                                                                      *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ipcr_u {
  ************************************************************************/
 
 typedef union ii_ipcr_u {

-       uint64_t        ii_ipcr_regval;
-       struct  {
-               uint64_t        i_ippr0_c                 :      4;
-               uint64_t        i_ippr1_c                 :      4;
-               uint64_t        i_icct                    :      8;
-               uint64_t       i_rsvd                    :     48;
+       uint64_t ii_ipcr_regval;
+       struct {
+               uint64_t i_ippr0_c:4;
+               uint64_t i_ippr1_c:4;
+               uint64_t i_icct:8;
+               uint64_t i_rsvd:48;

        } ii_ipcr_fld_s;
 } ii_ipcr_u_t;
 
        } ii_ipcr_fld_s;
 } ii_ipcr_u_t;
 

-

 /************************************************************************
 /************************************************************************

- *                                                                      *
- *                                                                      *
- *                                                                      *
+ *                                                                     *
+ *                                                                     *
+ *                                                                     *

  ************************************************************************/
 
 typedef union ii_ippr_u {
  ************************************************************************/
 
 typedef union ii_ippr_u {

-       uint64_t        ii_ippr_regval;
-       struct  {
-               uint64_t        i_ippr0                   :     32;
-               uint64_t        i_ippr1                   :     32;
+       uint64_t ii_ippr_regval;
+       struct {
+               uint64_t i_ippr0:32;
+               uint64_t i_ippr1:32;

        } ii_ippr_fld_s;
 } ii_ippr_u_t;
 
        } ii_ippr_fld_s;
 } ii_ippr_u_t;
 

-
-
-/**************************************************************************
- *                                                                        *
- * The following defines which were not formed into structures are        *
- * probably indentical to another register, and the name of the           *
- * register is provided against each of these registers. This             *
- * information needs to be checked carefully                              *
- *                                                                        *
- *           IIO_ICRB1_A                IIO_ICRB0_A                       *
- *           IIO_ICRB1_B                IIO_ICRB0_B                       *
- *           IIO_ICRB1_C                IIO_ICRB0_C                       *
- *           IIO_ICRB1_D                IIO_ICRB0_D                       *
- *           IIO_ICRB1_E                IIO_ICRB0_E                       *
- *           IIO_ICRB2_A                IIO_ICRB0_A                       *
- *           IIO_ICRB2_B                IIO_ICRB0_B                       *
- *           IIO_ICRB2_C                IIO_ICRB0_C                       *
- *           IIO_ICRB2_D                IIO_ICRB0_D                       *
- *           IIO_ICRB2_E                IIO_ICRB0_E                       *
- *           IIO_ICRB3_A                IIO_ICRB0_A                       *
- *           IIO_ICRB3_B                IIO_ICRB0_B                       *
- *           IIO_ICRB3_C                IIO_ICRB0_C                       *
- *           IIO_ICRB3_D                IIO_ICRB0_D                       *
- *           IIO_ICRB3_E                IIO_ICRB0_E                       *
- *           IIO_ICRB4_A                IIO_ICRB0_A                       *
- *           IIO_ICRB4_B                IIO_ICRB0_B                       *
- *           IIO_ICRB4_C                IIO_ICRB0_C                       *
- *           IIO_ICRB4_D                IIO_ICRB0_D                       *
- *           IIO_ICRB4_E                IIO_ICRB0_E                       *
- *           IIO_ICRB5_A                IIO_ICRB0_A                       *
- *           IIO_ICRB5_B                IIO_ICRB0_B                       *
- *           IIO_ICRB5_C                IIO_ICRB0_C                       *
- *           IIO_ICRB5_D                IIO_ICRB0_D                       *
- *           IIO_ICRB5_E                IIO_ICRB0_E                       *
- *           IIO_ICRB6_A                IIO_ICRB0_A                       *
- *           IIO_ICRB6_B                IIO_ICRB0_B                       *
- *           IIO_ICRB6_C                IIO_ICRB0_C                       *
- *           IIO_ICRB6_D                IIO_ICRB0_D                       *
- *           IIO_ICRB6_E                IIO_ICRB0_E                       *
- *           IIO_ICRB7_A                IIO_ICRB0_A                       *
- *           IIO_ICRB7_B                IIO_ICRB0_B                       *
- *           IIO_ICRB7_C                IIO_ICRB0_C                       *
- *           IIO_ICRB7_D                IIO_ICRB0_D                       *
- *           IIO_ICRB7_E                IIO_ICRB0_E                       *
- *           IIO_ICRB8_A                IIO_ICRB0_A                       *
- *           IIO_ICRB8_B                IIO_ICRB0_B                       *
- *           IIO_ICRB8_C                IIO_ICRB0_C                       *
- *           IIO_ICRB8_D                IIO_ICRB0_D                       *
- *           IIO_ICRB8_E                IIO_ICRB0_E                       *
- *           IIO_ICRB9_A                IIO_ICRB0_A                       *
- *           IIO_ICRB9_B                IIO_ICRB0_B                       *
- *           IIO_ICRB9_C                IIO_ICRB0_C                       *
- *           IIO_ICRB9_D                IIO_ICRB0_D                       *
- *           IIO_ICRB9_E                IIO_ICRB0_E                       *
- *           IIO_ICRBA_A                IIO_ICRB0_A                       *
- *           IIO_ICRBA_B                IIO_ICRB0_B                       *
- *           IIO_ICRBA_C                IIO_ICRB0_C                       *
- *           IIO_ICRBA_D                IIO_ICRB0_D                       *
- *           IIO_ICRBA_E                IIO_ICRB0_E                       *
- *           IIO_ICRBB_A                IIO_ICRB0_A                       *
- *           IIO_ICRBB_B                IIO_ICRB0_B                       *
- *           IIO_ICRBB_C                IIO_ICRB0_C                       *
- *           IIO_ICRBB_D                IIO_ICRB0_D                       *
- *           IIO_ICRBB_E                IIO_ICRB0_E                       *
- *           IIO_ICRBC_A                IIO_ICRB0_A                       *
- *           IIO_ICRBC_B                IIO_ICRB0_B                       *
- *           IIO_ICRBC_C                IIO_ICRB0_C                       *
- *           IIO_ICRBC_D                IIO_ICRB0_D                       *
- *           IIO_ICRBC_E                IIO_ICRB0_E                       *
- *           IIO_ICRBD_A                IIO_ICRB0_A                       *
- *           IIO_ICRBD_B                IIO_ICRB0_B                       *
- *           IIO_ICRBD_C                IIO_ICRB0_C                       *
- *           IIO_ICRBD_D                IIO_ICRB0_D                       *
- *           IIO_ICRBD_E                IIO_ICRB0_E                       *
- *           IIO_ICRBE_A                IIO_ICRB0_A                       *
- *           IIO_ICRBE_B                IIO_ICRB0_B                       *
- *           IIO_ICRBE_C                IIO_ICRB0_C                       *
- *           IIO_ICRBE_D                IIO_ICRB0_D                       *
- *           IIO_ICRBE_E                IIO_ICRB0_E                       *
- *                                                                        *
- **************************************************************************/
-
+/************************************************************************
+ *                                                                     *
+ * The following defines which were not formed into structures are     *
+ * probably indentical to another register, and the name of the                *
+ * register is provided against each of these registers. This          *
+ * information needs to be checked carefully                           *
+ *                                                                     *
+ *             IIO_ICRB1_A             IIO_ICRB0_A                     *
+ *             IIO_ICRB1_B             IIO_ICRB0_B                     *
+ *             IIO_ICRB1_C             IIO_ICRB0_C                     *
+ *             IIO_ICRB1_D             IIO_ICRB0_D                     *
+ *             IIO_ICRB1_E             IIO_ICRB0_E                     *
+ *             IIO_ICRB2_A             IIO_ICRB0_A                     *
+ *             IIO_ICRB2_B             IIO_ICRB0_B                     *
+ *             IIO_ICRB2_C             IIO_ICRB0_C                     *
+ *             IIO_ICRB2_D             IIO_ICRB0_D                     *
+ *             IIO_ICRB2_E             IIO_ICRB0_E                     *
+ *             IIO_ICRB3_A             IIO_ICRB0_A                     *
+ *             IIO_ICRB3_B             IIO_ICRB0_B                     *
+ *             IIO_ICRB3_C             IIO_ICRB0_C                     *
+ *             IIO_ICRB3_D             IIO_ICRB0_D                     *
+ *             IIO_ICRB3_E             IIO_ICRB0_E                     *
+ *             IIO_ICRB4_A             IIO_ICRB0_A                     *
+ *             IIO_ICRB4_B             IIO_ICRB0_B                     *
+ *             IIO_ICRB4_C             IIO_ICRB0_C                     *
+ *             IIO_ICRB4_D             IIO_ICRB0_D                     *
+ *             IIO_ICRB4_E             IIO_ICRB0_E                     *
+ *             IIO_ICRB5_A             IIO_ICRB0_A                     *
+ *             IIO_ICRB5_B             IIO_ICRB0_B                     *
+ *             IIO_ICRB5_C             IIO_ICRB0_C                     *
+ *             IIO_ICRB5_D             IIO_ICRB0_D                     *
+ *             IIO_ICRB5_E             IIO_ICRB0_E                     *
+ *             IIO_ICRB6_A             IIO_ICRB0_A                     *
+ *             IIO_ICRB6_B             IIO_ICRB0_B                     *
+ *             IIO_ICRB6_C             IIO_ICRB0_C                     *
+ *             IIO_ICRB6_D             IIO_ICRB0_D                     *
+ *             IIO_ICRB6_E             IIO_ICRB0_E                     *
+ *             IIO_ICRB7_A             IIO_ICRB0_A                     *
+ *             IIO_ICRB7_B             IIO_ICRB0_B                     *
+ *             IIO_ICRB7_C             IIO_ICRB0_C                     *
+ *             IIO_ICRB7_D             IIO_ICRB0_D                     *
+ *             IIO_ICRB7_E             IIO_ICRB0_E                     *
+ *             IIO_ICRB8_A             IIO_ICRB0_A                     *
+ *             IIO_ICRB8_B             IIO_ICRB0_B                     *
+ *             IIO_ICRB8_C             IIO_ICRB0_C                     *
+ *             IIO_ICRB8_D             IIO_ICRB0_D                     *
+ *             IIO_ICRB8_E             IIO_ICRB0_E                     *
+ *             IIO_ICRB9_A             IIO_ICRB0_A                     *
+ *             IIO_ICRB9_B             IIO_ICRB0_B                     *
+ *             IIO_ICRB9_C             IIO_ICRB0_C                     *
+ *             IIO_ICRB9_D             IIO_ICRB0_D                     *
+ *             IIO_ICRB9_E             IIO_ICRB0_E                     *
+ *             IIO_ICRBA_A             IIO_ICRB0_A                     *
+ *             IIO_ICRBA_B             IIO_ICRB0_B                     *
+ *             IIO_ICRBA_C             IIO_ICRB0_C                     *
+ *             IIO_ICRBA_D             IIO_ICRB0_D                     *
+ *             IIO_ICRBA_E             IIO_ICRB0_E                     *
+ *             IIO_ICRBB_A             IIO_ICRB0_A                     *
+ *             IIO_ICRBB_B             IIO_ICRB0_B                     *
+ *             IIO_ICRBB_C             IIO_ICRB0_C                     *
+ *             IIO_ICRBB_D             IIO_ICRB0_D                     *
+ *             IIO_ICRBB_E             IIO_ICRB0_E                     *
+ *             IIO_ICRBC_A             IIO_ICRB0_A                     *
+ *             IIO_ICRBC_B             IIO_ICRB0_B                     *
+ *             IIO_ICRBC_C             IIO_ICRB0_C                     *
+ *             IIO_ICRBC_D             IIO_ICRB0_D                     *
+ *             IIO_ICRBC_E             IIO_ICRB0_E                     *
+ *             IIO_ICRBD_A             IIO_ICRB0_A                     *
+ *             IIO_ICRBD_B             IIO_ICRB0_B                     *
+ *             IIO_ICRBD_C             IIO_ICRB0_C                     *
+ *             IIO_ICRBD_D             IIO_ICRB0_D                     *
+ *             IIO_ICRBD_E             IIO_ICRB0_E                     *
+ *             IIO_ICRBE_A             IIO_ICRB0_A                     *
+ *             IIO_ICRBE_B             IIO_ICRB0_B                     *
+ *             IIO_ICRBE_C             IIO_ICRB0_C                     *
+ *             IIO_ICRBE_D             IIO_ICRB0_D                     *
+ *             IIO_ICRBE_E             IIO_ICRB0_E                     *
+ *                                                                     *
+ ************************************************************************/

 
 /*
  * Slightly friendlier names for some common registers.
  */
 
 /*
  * Slightly friendlier names for some common registers.
  */

-#define IIO_WIDGET              IIO_WID      /* Widget identification */
-#define IIO_WIDGET_STAT         IIO_WSTAT    /* Widget status register */
-#define IIO_WIDGET_CTRL         IIO_WCR      /* Widget control register */
-#define IIO_PROTECT             IIO_ILAPR    /* IO interface protection */
-#define IIO_PROTECT_OVRRD       IIO_ILAPO    /* IO protect override */
-#define IIO_OUTWIDGET_ACCESS    IIO_IOWA     /* Outbound widget access */
-#define IIO_INWIDGET_ACCESS     IIO_IIWA     /* Inbound widget access */
-#define IIO_INDEV_ERR_MASK      IIO_IIDEM    /* Inbound device error mask */
-#define IIO_LLP_CSR             IIO_ILCSR    /* LLP control and status */
-#define IIO_LLP_LOG             IIO_ILLR     /* LLP log */
-#define IIO_XTALKCC_TOUT        IIO_IXCC     /* Xtalk credit count timeout*/
-#define IIO_XTALKTT_TOUT        IIO_IXTT     /* Xtalk tail timeout */
-#define IIO_IO_ERR_CLR          IIO_IECLR    /* IO error clear */
+#define IIO_WIDGET              IIO_WID                /* Widget identification */
+#define IIO_WIDGET_STAT         IIO_WSTAT      /* Widget status register */
+#define IIO_WIDGET_CTRL         IIO_WCR                /* Widget control register */
+#define IIO_PROTECT             IIO_ILAPR      /* IO interface protection */
+#define IIO_PROTECT_OVRRD       IIO_ILAPO      /* IO protect override */
+#define IIO_OUTWIDGET_ACCESS    IIO_IOWA       /* Outbound widget access */
+#define IIO_INWIDGET_ACCESS     IIO_IIWA       /* Inbound widget access */
+#define IIO_INDEV_ERR_MASK      IIO_IIDEM      /* Inbound device error mask */
+#define IIO_LLP_CSR             IIO_ILCSR      /* LLP control and status */
+#define IIO_LLP_LOG             IIO_ILLR       /* LLP log */
+#define IIO_XTALKCC_TOUT        IIO_IXCC       /* Xtalk credit count timeout */
+#define IIO_XTALKTT_TOUT        IIO_IXTT       /* Xtalk tail timeout */
+#define IIO_IO_ERR_CLR          IIO_IECLR      /* IO error clear */

 #define IIO_IGFX_0             IIO_IGFX0
 #define IIO_IGFX_1             IIO_IGFX1
 #define IIO_IBCT_0             IIO_IBCT0
 #define IIO_IGFX_0             IIO_IGFX0
 #define IIO_IGFX_1             IIO_IGFX1
 #define IIO_IBCT_0             IIO_IBCT0


@@ -2957,12 +2850,12 @@ typedef union ii_ippr_u {
 #define IIO_PRTE_A(_x)         (IIO_IPRTE0_A + (8 * (_x)))
 #define IIO_PRTE_B(_x)         (IIO_IPRTE0_B + (8 * (_x)))
 #define IIO_NUM_PRTES          8       /* Total number of PRB table entries */
 #define IIO_PRTE_A(_x)         (IIO_IPRTE0_A + (8 * (_x)))
 #define IIO_PRTE_B(_x)         (IIO_IPRTE0_B + (8 * (_x)))
 #define IIO_NUM_PRTES          8       /* Total number of PRB table entries */

-#define IIO_WIDPRTE_A(x)       IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
-#define IIO_WIDPRTE_B(x)       IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
+#define IIO_WIDPRTE_A(x)       IIO_PRTE_A(((x) - 8))   /* widget ID to its PRTE num */
+#define IIO_WIDPRTE_B(x)       IIO_PRTE_B(((x) - 8))   /* widget ID to its PRTE num */

 
 

-#define IIO_NUM_IPRBS          (9) 
+#define IIO_NUM_IPRBS          9

 
 

-#define IIO_LLP_CSR_IS_UP               0x00002000
+#define IIO_LLP_CSR_IS_UP              0x00002000

 #define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
 #define IIO_LLP_CSR_LLP_STAT_SHFT       12
 
 #define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
 #define IIO_LLP_CSR_LLP_STAT_SHFT       12
 


@@ -2970,30 +2863,29 @@ typedef union ii_ippr_u {
 #define IIO_LLP_SN_MAX  0xffff /* in ILLR SN_CNT, Max Sequence Number errors */
 
 /* key to IIO_PROTECT_OVRRD */
 #define IIO_LLP_SN_MAX  0xffff /* in ILLR SN_CNT, Max Sequence Number errors */
 
 /* key to IIO_PROTECT_OVRRD */

-#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
+#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull  /* "SGIrules" */

 
 /* BTE register names */
 
 /* BTE register names */

-#define IIO_BTE_STAT_0          IIO_IBLS_0   /* Also BTE length/status 0 */
-#define IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE source address  0 */
-#define IIO_BTE_DEST_0          IIO_IBDA_0   /* Also BTE dest. address 0 */
-#define IIO_BTE_CTRL_0          IIO_IBCT_0   /* Also BTE control/terminate 0 */
-#define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
-#define IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE interrupt 0 */
-#define IIO_BTE_OFF_0           0            /* Base offset from BTE 0 regs. */
-#define IIO_BTE_OFF_1          (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */
+#define IIO_BTE_STAT_0          IIO_IBLS_0     /* Also BTE length/status 0 */
+#define IIO_BTE_SRC_0           IIO_IBSA_0     /* Also BTE source address  0 */
+#define IIO_BTE_DEST_0          IIO_IBDA_0     /* Also BTE dest. address 0 */
+#define IIO_BTE_CTRL_0          IIO_IBCT_0     /* Also BTE control/terminate 0 */
+#define IIO_BTE_NOTIFY_0        IIO_IBNA_0     /* Also BTE notification 0 */
+#define IIO_BTE_INT_0           IIO_IBIA_0     /* Also BTE interrupt 0 */
+#define IIO_BTE_OFF_0           0      /* Base offset from BTE 0 regs. */
+#define IIO_BTE_OFF_1          (IIO_IBLS_1 - IIO_IBLS_0)       /* Offset from base to BTE 1 */

 
 /* BTE register offsets from base */
 #define BTEOFF_STAT             0
 
 /* BTE register offsets from base */
 #define BTEOFF_STAT             0

-#define BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
-#define BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
-#define BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
-#define BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
-#define BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
-
+#define BTEOFF_SRC             (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
+#define BTEOFF_DEST            (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
+#define BTEOFF_CTRL            (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
+#define BTEOFF_NOTIFY          (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
+#define BTEOFF_INT             (IIO_BTE_INT_0 - IIO_BTE_STAT_0)

 
 /* names used in shub diags */
 
 /* names used in shub diags */

-#define IIO_BASE_BTE0   IIO_IBLS_0             
-#define IIO_BASE_BTE1   IIO_IBLS_1             
+#define IIO_BASE_BTE0   IIO_IBLS_0
+#define IIO_BASE_BTE1   IIO_IBLS_1

 
 /*
  * Macro which takes the widget number, and returns the
 
 /*
  * Macro which takes the widget number, and returns the


@@ -3001,10 +2893,9 @@ typedef union ii_ippr_u {
  * value _x is expected to be a widget number in the range
  * 0, 8 - 0xF
  */
  * value _x is expected to be a widget number in the range
  * 0, 8 - 0xF
  */

-#define IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
-                        (_x) : \
-                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
-
+#define IIO_IOPRB(_x)  (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+                       (_x) : \
+                       (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )

 
 /* GFX Flow Control Node/Widget Register */
 #define IIO_IGFX_W_NUM_BITS    4       /* size of widget num field */
 
 /* GFX Flow Control Node/Widget Register */
 #define IIO_IGFX_W_NUM_BITS    4       /* size of widget num field */


@@ -3025,7 +2916,6 @@ typedef union ii_ippr_u {
        (((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |     \
        (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
 
        (((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |     \
        (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
 

-

 /* Scratch registers (all bits available) */
 #define IIO_SCRATCH_REG0        IIO_ISCR0
 #define IIO_SCRATCH_REG1        IIO_ISCR1
 /* Scratch registers (all bits available) */
 #define IIO_SCRATCH_REG0        IIO_ISCR0
 #define IIO_SCRATCH_REG1        IIO_ISCR1


@@ -3046,21 +2936,21 @@ typedef union ii_ippr_u {
 #define IIO_SCRATCH_BIT1_0      0x0000000000000001UL
 #define IIO_SCRATCH_BIT1_1      0x0000000000000002UL
 /* IO Translation Table Entries */
 #define IIO_SCRATCH_BIT1_0      0x0000000000000001UL
 #define IIO_SCRATCH_BIT1_1      0x0000000000000002UL
 /* IO Translation Table Entries */

-#define IIO_NUM_ITTES   7               /* ITTEs numbered 0..6 */
-                                        /* Hw manuals number them 1..7! */
+#define IIO_NUM_ITTES   7      /* ITTEs numbered 0..6 */
+                                       /* Hw manuals number them 1..7! */

 /*
  * IIO_IMEM Register fields.
  */
 /*
  * IIO_IMEM Register fields.
  */

-#define IIO_IMEM_W0ESD  0x1UL             /* Widget 0 shut down due to error */
-#define IIO_IMEM_B0ESD  (1UL << 4)        /* BTE 0 shut down due to error */
-#define IIO_IMEM_B1ESD  (1UL << 8)        /* BTE 1 Shut down due to error */
+#define IIO_IMEM_W0ESD  0x1UL  /* Widget 0 shut down due to error */
+#define IIO_IMEM_B0ESD (1UL << 4)      /* BTE 0 shut down due to error */
+#define IIO_IMEM_B1ESD (1UL << 8)      /* BTE 1 Shut down due to error */

 
 /*
  * As a permanent workaround for a bug in the PI side of the shub, we've
  * redefined big window 7 as small window 0.
  XXX does this still apply for SN1??
  */
 
 /*
  * As a permanent workaround for a bug in the PI side of the shub, we've
  * redefined big window 7 as small window 0.
  XXX does this still apply for SN1??
  */

-#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
+#define HUB_NUM_BIG_WINDOW     (IIO_NUM_ITTES - 1)

 
 /*
  * Use the top big window as a surrogate for the first small window
 
 /*
  * Use the top big window as a surrogate for the first small window


@@ -3071,11 +2961,11 @@ typedef union ii_ippr_u {
 
 /*
  * CRB manipulation macros
 
 /*
  * CRB manipulation macros

- *      The CRB macros are slightly complicated, since there are up to
- *      four registers associated with each CRB entry.
+ *     The CRB macros are slightly complicated, since there are up to
+ *     four registers associated with each CRB entry.

  */
  */

-#define IIO_NUM_CRBS            15      /* Number of CRBs */
-#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
+#define IIO_NUM_CRBS            15     /* Number of CRBs */
+#define IIO_NUM_PC_CRBS         4      /* Number of partial cache CRBs */

 #define IIO_ICRB_OFFSET         8
 #define IIO_ICRB_0              IIO_ICRB0_A
 #define IIO_ICRB_ADDR_SHFT     2       /* Shift to get proper address */
 #define IIO_ICRB_OFFSET         8
 #define IIO_ICRB_0              IIO_ICRB0_A
 #define IIO_ICRB_ADDR_SHFT     2       /* Shift to get proper address */


@@ -3083,43 +2973,43 @@ typedef union ii_ippr_u {
         #define IIO_FIRST_PC_ENTRY 12
  */
 
         #define IIO_FIRST_PC_ENTRY 12
  */
 

-#define IIO_ICRB_A(_x)  ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))
-#define IIO_ICRB_B(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))
-#define IIO_ICRB_C(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))
-#define IIO_ICRB_D(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))
-#define IIO_ICRB_E(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))
+#define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))
+#define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))
+#define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))
+#define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))
+#define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))

 
 #define TNUM_TO_WIDGET_DEV(_tnum)      (_tnum & 0x7)
 
 /*
  * values for "ecode" field
  */
 
 #define TNUM_TO_WIDGET_DEV(_tnum)      (_tnum & 0x7)
 
 /*
  * values for "ecode" field
  */

-#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
-#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
-#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
-                                         * e.g. WINV to a Read only line. */
-#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
-#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
-#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
-#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
-#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
+#define IIO_ICRB_ECODE_DERR     0      /* Directory error due to IIO access */
+#define IIO_ICRB_ECODE_PERR     1      /* Poison error on IO access */
+#define IIO_ICRB_ECODE_WERR     2      /* Write error by IIO access
+                                        * e.g. WINV to a Read only line. */
+#define IIO_ICRB_ECODE_AERR     3      /* Access error caused by IIO access */
+#define IIO_ICRB_ECODE_PWERR    4      /* Error on partial write */
+#define IIO_ICRB_ECODE_PRERR    5      /* Error on partial read  */
+#define IIO_ICRB_ECODE_TOUT     6      /* CRB timeout before deallocating */
+#define IIO_ICRB_ECODE_XTERR    7      /* Incoming xtalk pkt had error bit */

 
 /*
  * Values for field imsgtype
  */
 
 /*
  * Values for field imsgtype
  */

-#define IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage from Xtalk */
-#define IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
-#define IIO_ICRB_IMSGT_SN1NET   2       /* Incoming message from SN1 net */
-#define IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
+#define IIO_ICRB_IMSGT_XTALK    0      /* Incoming Meessage from Xtalk */
+#define IIO_ICRB_IMSGT_BTE      1      /* Incoming message from BTE    */
+#define IIO_ICRB_IMSGT_SN1NET   2      /* Incoming message from SN1 net */
+#define IIO_ICRB_IMSGT_CRB      3      /* Incoming message from CRB ???  */

 
 /*
  * values for field initiator.
  */
 
 /*
  * values for field initiator.
  */

-#define IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
-#define IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
-#define IIO_ICRB_INIT_SN1NET    0x2     /* Message originated in SN1net */
-#define IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
-#define IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
+#define IIO_ICRB_INIT_XTALK     0      /* Message originated in xtalk  */
+#define IIO_ICRB_INIT_BTE0      0x1    /* Message originated in BTE 0  */
+#define IIO_ICRB_INIT_SN1NET    0x2    /* Message originated in SN1net */
+#define IIO_ICRB_INIT_CRB       0x3    /* Message originated in CRB ?  */
+#define IIO_ICRB_INIT_BTE1      0x5    /* MEssage originated in BTE 1  */

 
 /*
  * Number of credits Hub widget has while sending req/response to
 
 /*
  * Number of credits Hub widget has while sending req/response to


@@ -3127,8 +3017,8 @@ typedef union ii_ippr_u {
  * Value of 3 is required by Xbow 1.1
  * We may be able to increase this to 4 with Xbow 1.2.
  */
  * Value of 3 is required by Xbow 1.1
  * We may be able to increase this to 4 with Xbow 1.2.
  */

-#define       HUBII_XBOW_CREDIT       3
-#define       HUBII_XBOW_REV2_CREDIT  4
+#define                   HUBII_XBOW_CREDIT       3
+#define                   HUBII_XBOW_REV2_CREDIT  4

 
 /*
  * Number of credits that xtalk devices should use when communicating
 
 /*
  * Number of credits that xtalk devices should use when communicating


@@ -3159,28 +3049,28 @@ typedef union ii_ippr_u {
  */
 
 #define IIO_ICMR_CRB_VLD_SHFT   20
  */
 
 #define IIO_ICMR_CRB_VLD_SHFT   20

-#define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
+#define IIO_ICMR_CRB_VLD_MASK  (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)

 
 #define IIO_ICMR_FC_CNT_SHFT    16
 
 #define IIO_ICMR_FC_CNT_SHFT    16

-#define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
+#define IIO_ICMR_FC_CNT_MASK   (0xf << IIO_ICMR_FC_CNT_SHFT)

 
 #define IIO_ICMR_C_CNT_SHFT     4
 
 #define IIO_ICMR_C_CNT_SHFT     4

-#define IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)
+#define IIO_ICMR_C_CNT_MASK    (0xf << IIO_ICMR_C_CNT_SHFT)

 
 

-#define IIO_ICMR_PRECISE        (1UL << 52)
-#define IIO_ICMR_CLR_RPPD       (1UL << 13)
-#define IIO_ICMR_CLR_RQPD       (1UL << 12)
+#define IIO_ICMR_PRECISE       (1UL << 52)
+#define IIO_ICMR_CLR_RPPD      (1UL << 13)
+#define IIO_ICMR_CLR_RQPD      (1UL << 12)

 
 /*
  * IIO PIO Deallocation register field masks : (IIO_IPDR)
  XXX present but not needed in bedrock?  See the manual.
  */
 
 /*
  * IIO PIO Deallocation register field masks : (IIO_IPDR)
  XXX present but not needed in bedrock?  See the manual.
  */

-#define IIO_IPDR_PND    (1 << 4)
+#define IIO_IPDR_PND           (1 << 4)

 
 /*
  * IIO CRB deallocation register field masks: (IIO_ICDR)
  */
 
 /*
  * IIO CRB deallocation register field masks: (IIO_ICDR)
  */

-#define IIO_ICDR_PND    (1 << 4)
+#define IIO_ICDR_PND           (1 << 4)

 
 /* 
  * IO BTE Length/Status (IIO_IBLS) register bit field definitions
 
 /* 
  * IO BTE Length/Status (IIO_IBLS) register bit field definitions


@@ -3223,35 +3113,35 @@ typedef union ii_ippr_u {
 /*
  * IO Error Clear register bit field definitions
  */
 /*
  * IO Error Clear register bit field definitions
  */

-#define IECLR_PI1_FWD_INT      (1UL << 31)  /* clear PI1_FORWARD_INT in iidsr */
-#define IECLR_PI0_FWD_INT      (1UL << 30)  /* clear PI0_FORWARD_INT in iidsr */
-#define IECLR_SPUR_RD_HDR      (1UL << 29)  /* clear valid bit in ixss reg */
-#define IECLR_BTE1             (1UL << 18)  /* clear bte error 1 */
-#define IECLR_BTE0             (1UL << 17)  /* clear bte error 0 */
-#define IECLR_CRAZY            (1UL << 16)  /* clear crazy bit in wstat reg */
-#define IECLR_PRB_F            (1UL << 15)  /* clear err bit in PRB_F reg */
-#define IECLR_PRB_E            (1UL << 14)  /* clear err bit in PRB_E reg */
-#define IECLR_PRB_D            (1UL << 13)  /* clear err bit in PRB_D reg */
-#define IECLR_PRB_C            (1UL << 12)  /* clear err bit in PRB_C reg */
-#define IECLR_PRB_B            (1UL << 11)  /* clear err bit in PRB_B reg */
-#define IECLR_PRB_A            (1UL << 10)  /* clear err bit in PRB_A reg */
-#define IECLR_PRB_9            (1UL << 9)   /* clear err bit in PRB_9 reg */
-#define IECLR_PRB_8            (1UL << 8)   /* clear err bit in PRB_8 reg */
-#define IECLR_PRB_0            (1UL << 0)   /* clear err bit in PRB_0 reg */
+#define IECLR_PI1_FWD_INT      (1UL << 31)     /* clear PI1_FORWARD_INT in iidsr */
+#define IECLR_PI0_FWD_INT      (1UL << 30)     /* clear PI0_FORWARD_INT in iidsr */
+#define IECLR_SPUR_RD_HDR      (1UL << 29)     /* clear valid bit in ixss reg */
+#define IECLR_BTE1             (1UL << 18)     /* clear bte error 1 */
+#define IECLR_BTE0             (1UL << 17)     /* clear bte error 0 */
+#define IECLR_CRAZY            (1UL << 16)     /* clear crazy bit in wstat reg */
+#define IECLR_PRB_F            (1UL << 15)     /* clear err bit in PRB_F reg */
+#define IECLR_PRB_E            (1UL << 14)     /* clear err bit in PRB_E reg */
+#define IECLR_PRB_D            (1UL << 13)     /* clear err bit in PRB_D reg */
+#define IECLR_PRB_C            (1UL << 12)     /* clear err bit in PRB_C reg */
+#define IECLR_PRB_B            (1UL << 11)     /* clear err bit in PRB_B reg */
+#define IECLR_PRB_A            (1UL << 10)     /* clear err bit in PRB_A reg */
+#define IECLR_PRB_9            (1UL << 9)      /* clear err bit in PRB_9 reg */
+#define IECLR_PRB_8            (1UL << 8)      /* clear err bit in PRB_8 reg */
+#define IECLR_PRB_0            (1UL << 0)      /* clear err bit in PRB_0 reg */

 
 /*
  * IIO CRB control register Fields: IIO_ICCR 
  */
 
 /*
  * IIO CRB control register Fields: IIO_ICCR 
  */

-#define        IIO_ICCR_PENDING        (0x10000)
-#define        IIO_ICCR_CMD_MASK       (0xFF)
-#define        IIO_ICCR_CMD_SHFT       (7)
-#define        IIO_ICCR_CMD_NOP        (0x0)   /* No Op */
-#define        IIO_ICCR_CMD_WAKE       (0x100) /* Reactivate CRB entry and process */
-#define        IIO_ICCR_CMD_TIMEOUT    (0x200) /* Make CRB timeout & mark invalid */
-#define        IIO_ICCR_CMD_EJECT      (0x400) /* Contents of entry written to memory 
+#define        IIO_ICCR_PENDING        0x10000
+#define        IIO_ICCR_CMD_MASK       0xFF
+#define        IIO_ICCR_CMD_SHFT       7
+#define        IIO_ICCR_CMD_NOP        0x0     /* No Op */
+#define        IIO_ICCR_CMD_WAKE       0x100   /* Reactivate CRB entry and process */
+#define        IIO_ICCR_CMD_TIMEOUT    0x200   /* Make CRB timeout & mark invalid */
+#define        IIO_ICCR_CMD_EJECT      0x400   /* Contents of entry written to memory

                                         * via a WB
                                         */
                                         * via a WB
                                         */

-#define        IIO_ICCR_CMD_FLUSH      (0x800)
+#define        IIO_ICCR_CMD_FLUSH      0x800

 
 /*
  *
 
 /*
  *


@@ -3283,8 +3173,8 @@ typedef union ii_ippr_u {
  * Easy access macros for CRBs, all 5 registers (A-E)
  */
 typedef ii_icrb0_a_u_t icrba_t;
  * Easy access macros for CRBs, all 5 registers (A-E)
  */
 typedef ii_icrb0_a_u_t icrba_t;

-#define a_sidn          ii_icrb0_a_fld_s.ia_sidn
-#define a_tnum          ii_icrb0_a_fld_s.ia_tnum
+#define a_sidn         ii_icrb0_a_fld_s.ia_sidn
+#define a_tnum         ii_icrb0_a_fld_s.ia_tnum

 #define a_addr          ii_icrb0_a_fld_s.ia_addr
 #define a_valid         ii_icrb0_a_fld_s.ia_vld
 #define a_iow           ii_icrb0_a_fld_s.ia_iow
 #define a_addr          ii_icrb0_a_fld_s.ia_addr
 #define a_valid         ii_icrb0_a_fld_s.ia_vld
 #define a_iow           ii_icrb0_a_fld_s.ia_iow


@@ -3324,14 +3214,13 @@ typedef ii_icrb0_c_u_t icrbc_t;
 #define c_source        ii_icrb0_c_fld_s.ic_source
 #define c_regvalue     ii_icrb0_c_regval
 
 #define c_source        ii_icrb0_c_fld_s.ic_source
 #define c_regvalue     ii_icrb0_c_regval
 

-

 typedef ii_icrb0_d_u_t icrbd_t;
 #define d_sleep         ii_icrb0_d_fld_s.id_sleep
 #define d_pricnt        ii_icrb0_d_fld_s.id_pr_cnt
 #define d_pripsc        ii_icrb0_d_fld_s.id_pr_psc
 #define d_bteop         ii_icrb0_d_fld_s.id_bte_op
 typedef ii_icrb0_d_u_t icrbd_t;
 #define d_sleep         ii_icrb0_d_fld_s.id_sleep
 #define d_pricnt        ii_icrb0_d_fld_s.id_pr_cnt
 #define d_pripsc        ii_icrb0_d_fld_s.id_pr_psc
 #define d_bteop         ii_icrb0_d_fld_s.id_bte_op

-#define d_bteaddr       ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/
-#define d_benable       ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/
+#define d_bteaddr       ii_icrb0_d_fld_s.id_pa_be      /* ic_pa_be fld has 2 names */
+#define d_benable       ii_icrb0_d_fld_s.id_pa_be      /* ic_pa_be fld has 2 names */

 #define d_regvalue     ii_icrb0_d_regval
 
 typedef ii_icrb0_e_u_t icrbe_t;
 #define d_regvalue     ii_icrb0_d_regval
 
 typedef ii_icrb0_e_u_t icrbe_t;


@@ -3341,7 +3230,6 @@ typedef ii_icrb0_e_u_t icrbe_t;
 #define icrbe_timeout   ii_icrb0_e_fld_s.ie_timeout
 #define e_regvalue     ii_icrb0_e_regval
 
 #define icrbe_timeout   ii_icrb0_e_fld_s.ie_timeout
 #define e_regvalue     ii_icrb0_e_regval
 

-

 /* Number of widgets supported by shub */
 #define HUB_NUM_WIDGET          9
 #define HUB_WIDGET_ID_MIN       0x8
 /* Number of widgets supported by shub */
 #define HUB_NUM_WIDGET          9
 #define HUB_WIDGET_ID_MIN       0x8


@@ -3367,27 +3255,27 @@ typedef ii_icrb0_e_u_t icrbe_t;
 
 #define LNK_STAT_WORKING        0x2            /* LLP is working */
 
 
 #define LNK_STAT_WORKING        0x2            /* LLP is working */
 

-#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
-#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
-#define IIO_WSTAT_TXRETRY_MASK  (0x7F)   /* should be 0xFF?? */
-#define IIO_WSTAT_TXRETRY_SHFT  (16)
-#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
-                                          IIO_WSTAT_TXRETRY_MASK)
+#define IIO_WSTAT_ECRAZY       (1ULL << 32)    /* Hub gone crazy */
+#define IIO_WSTAT_TXRETRY      (1ULL << 9)     /* Hub Tx Retry timeout */
+#define IIO_WSTAT_TXRETRY_MASK  0x7F           /* should be 0xFF?? */
+#define IIO_WSTAT_TXRETRY_SHFT  16
+#define IIO_WSTAT_TXRETRY_CNT(w)       (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
+                                       IIO_WSTAT_TXRETRY_MASK)

 
 /* Number of II perf. counters we can multiplex at once */
 
 #define IO_PERF_SETS   32
 
 /* Bit for the widget in inbound access register */
 
 /* Number of II perf. counters we can multiplex at once */
 
 #define IO_PERF_SETS   32
 
 /* Bit for the widget in inbound access register */

-#define IIO_IIWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
+#define IIO_IIWA_WIDGET(_w)    ((uint64_t)(1ULL << _w))

 /* Bit for the widget in outbound access register */
 /* Bit for the widget in outbound access register */

-#define IIO_IOWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
+#define IIO_IOWA_WIDGET(_w)    ((uint64_t)(1ULL << _w))

 
 /* NOTE: The following define assumes that we are going to get
  * widget numbers from 8 thru F and the device numbers within
  * widget from 0 thru 7.
  */
 
 /* NOTE: The following define assumes that we are going to get
  * widget numbers from 8 thru F and the device numbers within
  * widget from 0 thru 7.
  */

-#define IIO_IIDEM_WIDGETDEV_MASK(w, d)  ((uint64_t)(1ULL << (8 * ((w) - 8) + (d))))
+#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d))))

 
 /* IO Interrupt Destination Register */
 #define IIO_IIDSR_SENT_SHIFT    28
 
 /* IO Interrupt Destination Register */
 #define IIO_IIDSR_SENT_SHIFT    28


@@ -3402,11 +3290,11 @@ typedef ii_icrb0_e_u_t icrbe_t;
 #define IIO_IIDSR_LVL_MASK      0x000000ff
 
 /* Xtalk timeout threshhold register (IIO_IXTT) */
 #define IIO_IIDSR_LVL_MASK      0x000000ff
 
 /* Xtalk timeout threshhold register (IIO_IXTT) */

-#define IXTT_RRSP_TO_SHFT      55         /* read response timeout */
+#define IXTT_RRSP_TO_SHFT      55      /* read response timeout */

 #define IXTT_RRSP_TO_MASK      (0x1FULL << IXTT_RRSP_TO_SHFT)
 #define IXTT_RRSP_TO_MASK      (0x1FULL << IXTT_RRSP_TO_SHFT)

-#define IXTT_RRSP_PS_SHFT      32         /* read responsed TO prescalar */
+#define IXTT_RRSP_PS_SHFT      32      /* read responsed TO prescalar */

 #define IXTT_RRSP_PS_MASK      (0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
 #define IXTT_RRSP_PS_MASK      (0x7FFFFFULL << IXTT_RRSP_PS_SHFT)

-#define IXTT_TAIL_TO_SHFT      0          /* tail timeout counter threshold */
+#define IXTT_TAIL_TO_SHFT      0       /* tail timeout counter threshold */

 #define IXTT_TAIL_TO_MASK      (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
 
 /*
 #define IXTT_TAIL_TO_MASK      (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
 
 /*


@@ -3414,17 +3302,17 @@ typedef ii_icrb0_e_u_t icrbe_t;
  */
 
 typedef union hubii_wcr_u {
  */
 
 typedef union hubii_wcr_u {

-        uint64_t      wcr_reg_value;
-        struct {
-         uint64_t      wcr_widget_id:   4,     /* LLP crossbar credit */
-                       wcr_tag_mode:    1,     /* Tag mode */
-                       wcr_rsvd1:       8,     /* Reserved */
-                       wcr_xbar_crd:    3,     /* LLP crossbar credit */
-                       wcr_f_bad_pkt:   1,     /* Force bad llp pkt enable */
-                       wcr_dir_con:     1,     /* widget direct connect */
-                       wcr_e_thresh:    5,     /* elasticity threshold */
-                       wcr_rsvd:       41;     /* unused */
-        } wcr_fields_s;
+       uint64_t wcr_reg_value;
+       struct {
+               uint64_t wcr_widget_id:4,       /* LLP crossbar credit */
+                wcr_tag_mode:1,        /* Tag mode */
+                wcr_rsvd1:8,   /* Reserved */
+                wcr_xbar_crd:3,        /* LLP crossbar credit */
+                wcr_f_bad_pkt:1,       /* Force bad llp pkt enable */
+                wcr_dir_con:1, /* widget direct connect */
+                wcr_e_thresh:5,        /* elasticity threshold */
+                wcr_rsvd:41;   /* unused */
+       } wcr_fields_s;

 } hubii_wcr_t;
 
 #define iwcr_dir_con    wcr_fields_s.wcr_dir_con
 } hubii_wcr_t;
 
 #define iwcr_dir_con    wcr_fields_s.wcr_dir_con


@@ -3436,41 +3324,35 @@ performance registers */
    performed */
 
 typedef union io_perf_sel {
    performed */
 
 typedef union io_perf_sel {

-        uint64_t perf_sel_reg;
-        struct {
-               uint64_t        perf_ippr0 :  4,
-                               perf_ippr1 :  4,
-                               perf_icct  :  8,
-                               perf_rsvd  : 48;
-        } perf_sel_bits;
+       uint64_t perf_sel_reg;
+       struct {
+               uint64_t perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48;
+       } perf_sel_bits;

 } io_perf_sel_t;
 
 /* io_perf_cnt is to extract the count from the shub registers. Due to
    hardware problems there is only one counter, not two. */
 
 typedef union io_perf_cnt {
 } io_perf_sel_t;
 
 /* io_perf_cnt is to extract the count from the shub registers. Due to
    hardware problems there is only one counter, not two. */
 
 typedef union io_perf_cnt {

-        uint64_t      perf_cnt;
-        struct {
-               uint64_t        perf_cnt   : 20,
-                               perf_rsvd2 : 12,
-                               perf_rsvd1 : 32;
-        } perf_cnt_bits;
+       uint64_t perf_cnt;
+       struct {
+               uint64_t perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32;
+       } perf_cnt_bits;

 
 } io_perf_cnt_t;
 
 typedef union iprte_a {
 
 } io_perf_cnt_t;
 
 typedef union iprte_a {

-       uint64_t        entry;
-       struct {
-               uint64_t        i_rsvd_1                  :      3;
-               uint64_t        i_addr                    :     38;
-               uint64_t        i_init                    :      3;
-               uint64_t        i_source                  :      8;
-               uint64_t        i_rsvd                    :      2;
-               uint64_t        i_widget                  :      4;
-               uint64_t        i_to_cnt                  :      5;
-               uint64_t       i_vld                     :      1;
+       uint64_t entry;
+       struct {
+               uint64_t i_rsvd_1:3;
+               uint64_t i_addr:38;
+               uint64_t i_init:3;
+               uint64_t i_source:8;
+               uint64_t i_rsvd:2;
+               uint64_t i_widget:4;
+               uint64_t i_to_cnt:5;
+               uint64_t i_vld:1;

        } iprte_fields;
 } iprte_a_t;
 
        } iprte_fields;
 } iprte_a_t;
 

-#endif /* _ASM_IA64_SN_SHUBIO_H */
-
+#endif                         /* _ASM_IA64_SN_SHUBIO_H */

diff --git a/include/asm-parisc/unwind.h b/include/asm-parisc/unwind.h
index ff9396b..2f7e6e5 100644 (file)
--- a/include/asm-parisc/unwind.h
+++ b/include/asm-parisc/unwind.h
@@ -1,6 +1,8 @@
 #ifndef _UNWIND_H_
 #define _UNWIND_H_
 
 #ifndef _UNWIND_H_
 #define _UNWIND_H_
 

+#include <linux/list.h>
+

 /* From ABI specifications */
 struct unwind_table_entry {
        unsigned int region_start;
 /* From ABI specifications */
 struct unwind_table_entry {
        unsigned int region_start;


@@ -39,7 +41,7 @@ struct unwind_table_entry {
 };
 
 struct unwind_table {
 };
 
 struct unwind_table {

-       struct unwind_table *next;
+       struct list_head list;

        const char *name;
        unsigned long gp;
        unsigned long base_addr;
        const char *name;
        unsigned long gp;
        unsigned long base_addr;


@@ -55,15 +57,18 @@ struct unwind_frame_info {
           available; but for now we only try to get the sp and ip for each
           frame */
        /* struct pt_regs regs; */
           available; but for now we only try to get the sp and ip for each
           frame */
        /* struct pt_regs regs; */

-       unsigned long sp, ip, rp;
+       unsigned long sp, ip, rp, r31;

        unsigned long prev_sp, prev_ip;
 };
 
        unsigned long prev_sp, prev_ip;
 };
 

-void * unwind_table_add(const char *name, unsigned long base_addr, 
-                unsigned long gp,
-                 void *start, void *end);
+struct unwind_table *
+unwind_table_add(const char *name, unsigned long base_addr, 
+                unsigned long gp, void *start, void *end);
+void
+unwind_table_remove(struct unwind_table *table);
+

 void unwind_frame_init(struct unwind_frame_info *info, struct task_struct *t, 
 void unwind_frame_init(struct unwind_frame_info *info, struct task_struct *t, 

-                      unsigned long sp, unsigned long ip, unsigned long rp);
+                      struct pt_regs *regs);

 void unwind_frame_init_from_blocked_task(struct unwind_frame_info *info, struct task_struct *t);
 void unwind_frame_init_running(struct unwind_frame_info *info, struct pt_regs *regs);
 int unwind_once(struct unwind_frame_info *info);
 void unwind_frame_init_from_blocked_task(struct unwind_frame_info *info, struct task_struct *t);
 void unwind_frame_init_running(struct unwind_frame_info *info, struct pt_regs *regs);
 int unwind_once(struct unwind_frame_info *info);

diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h
index 163a6b9..bf9e05d 100644 (file)
--- a/include/asm-ppc/m8260_pci.h
+++ b/include/asm-ppc/m8260_pci.h
@@ -19,6 +19,7 @@
  * Define the vendor/device ID for the MPC8265.
  */
 #define        PCI_DEVICE_ID_MPC8265   ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
  * Define the vendor/device ID for the MPC8265.
  */
 #define        PCI_DEVICE_ID_MPC8265   ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)

+#define        PCI_DEVICE_ID_MPC8272   ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)

 
 #define M8265_PCIBR0   0x101ac
 #define M8265_PCIBR1   0x101b0
 
 #define M8265_PCIBR0   0x101ac
 #define M8265_PCIBR1   0x101b0

diff --git a/include/asm-s390/cputime.h b/include/asm-s390/cputime.h
index 216d861..4b3ef7c 100644 (file)
--- a/include/asm-s390/cputime.h
+++ b/include/asm-s390/cputime.h
@@ -9,6 +9,8 @@
 #ifndef _S390_CPUTIME_H
 #define _S390_CPUTIME_H
 
 #ifndef _S390_CPUTIME_H
 #define _S390_CPUTIME_H
 

+#include <asm/div64.h>
+

 /* We want to use micro-second resolution. */
 
 typedef unsigned long long cputime_t;
 /* We want to use micro-second resolution. */
 
 typedef unsigned long long cputime_t;


@@ -40,6 +42,12 @@ __div(unsigned long long n, unsigned int base)
 #define cputime_max                    ((~0UL >> 1) - 1)
 #define cputime_add(__a, __b)          ((__a) +  (__b))
 #define cputime_sub(__a, __b)          ((__a) -  (__b))
 #define cputime_max                    ((~0UL >> 1) - 1)
 #define cputime_add(__a, __b)          ((__a) +  (__b))
 #define cputime_sub(__a, __b)          ((__a) -  (__b))

+#define cputime_div(__a, __n) ({               \
+       unsigned long long __div = (__a);       \
+       do_div(__div,__n);                      \
+       __div;                                  \
+})
+#define cputime_halve(__a)             ((__a) >> 1)

 #define cputime_eq(__a, __b)           ((__a) == (__b))
 #define cputime_gt(__a, __b)           ((__a) >  (__b))
 #define cputime_ge(__a, __b)           ((__a) >= (__b))
 #define cputime_eq(__a, __b)           ((__a) == (__b))
 #define cputime_gt(__a, __b)           ((__a) >  (__b))
 #define cputime_ge(__a, __b)           ((__a) >= (__b))

diff --git a/include/asm-sh64/elf.h b/include/asm-sh64/elf.h
index bc48366..f994286 100644 (file)
--- a/include/asm-sh64/elf.h
+++ b/include/asm-sh64/elf.h
@@ -53,6 +53,12 @@ typedef struct user_fpu_struct elf_fpregset_t;
 
 #define ELF_ET_DYN_BASE         (2 * TASK_SIZE / 3)
 
 
 #define ELF_ET_DYN_BASE         (2 * TASK_SIZE / 3)
 

+#define        R_SH_DIR32              1
+#define        R_SH_REL32              2
+#define        R_SH_IMM_LOW16          246
+#define        R_SH_IMM_LOW16_PCREL    247
+#define        R_SH_IMM_MEDLOW16       248
+#define        R_SH_IMM_MEDLOW16_PCREL 249

 
 #define ELF_CORE_COPY_REGS(_dest,_regs)                                \
        memcpy((char *) &_dest, (char *) _regs,                 \
 
 #define ELF_CORE_COPY_REGS(_dest,_regs)                                \
        memcpy((char *) &_dest, (char *) _regs,                 \

diff --git a/include/asm-sh64/hardware.h b/include/asm-sh64/hardware.h
index a2e6112..931c1ad 100644 (file)
--- a/include/asm-sh64/hardware.h
+++ b/include/asm-sh64/hardware.h
@@ -17,29 +17,6 @@
 #define        PHYS_PERIPHERAL_BLOCK   0x09000000
 #define PHYS_DMAC_BLOCK                0x0e000000
 #define PHYS_PCI_BLOCK         0x60000000
 #define        PHYS_PERIPHERAL_BLOCK   0x09000000
 #define PHYS_DMAC_BLOCK                0x0e000000
 #define PHYS_PCI_BLOCK         0x60000000

-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#include <asm/io.h>
-
-struct vcr_info {
-       u8      perr_flags;     /* P-port Error flags */
-       u8      merr_flags;     /* Module Error flags */
-       u16     mod_vers;       /* Module Version */
-       u16     mod_id;         /* Module ID */
-       u8      bot_mb;         /* Bottom Memory block */
-       u8      top_mb;         /* Top Memory block */
-};
-
-static inline struct vcr_info sh64_get_vcr_info(unsigned long base)
-{
-       unsigned long long tmp;
-
-       tmp = sh64_in64(base);
-
-       return *((struct vcr_info *)&tmp);
-}
-
-#endif /* __ASSEMBLY__ */
+#define PHYS_EMI_BLOCK         0xff000000

 
 #endif /* __ASM_SH64_HARDWARE_H */
 
 #endif /* __ASM_SH64_HARDWARE_H */

diff --git a/include/asm-sh64/ioctls.h b/include/asm-sh64/ioctls.h
index e5d5562..08f3c1f 100644 (file)
--- a/include/asm-sh64/ioctls.h
+++ b/include/asm-sh64/ioctls.h
@@ -9,103 +9,108 @@
  * include/asm-sh64/ioctls.h
  *
  * Copyright (C) 2000, 2001  Paolo Alberelli
  * include/asm-sh64/ioctls.h
  *
  * Copyright (C) 2000, 2001  Paolo Alberelli

+ * Copyright (C) 2004  Richard Curnow

  *
  */
 
 #include <asm/ioctl.h>
 
  *
  */
 
 #include <asm/ioctl.h>
 

-#define FIOCLEX                _IO('f', 1)
-#define FIONCLEX       _IO('f', 2)
-#define FIOASYNC       _IOW('f', 125, int)
-#define FIONBIO                _IOW('f', 126, int)
-#define FIONREAD       _IOR('f', 127, int)
+#define FIOCLEX                0x6601          /* _IO('f', 1) */
+#define FIONCLEX       0x6602          /* _IO('f', 2) */
+#define FIOASYNC       0x4004667d      /* _IOW('f', 125, int) */
+#define FIONBIO                0x4004667e      /* _IOW('f', 126, int) */
+#define FIONREAD       0x8004667f      /* _IOW('f', 127, int) */

 #define TIOCINQ                FIONREAD
 #define TIOCINQ                FIONREAD

-#define FIOQSIZE       _IOR('f', 128, loff_t)
+#define FIOQSIZE       0x80086680      /* _IOR('f', 128, loff_t) */

 
 #define TCGETS         0x5401
 #define TCSETS         0x5402
 #define TCSETSW                0x5403
 #define TCSETSF                0x5404
 
 
 #define TCGETS         0x5401
 #define TCSETS         0x5402
 #define TCSETSW                0x5403
 #define TCSETSF                0x5404
 

-#define TCGETA         _IOR('t', 23, struct termio)
-#define TCSETA         _IOW('t', 24, struct termio)
-#define TCSETAW                _IOW('t', 25, struct termio)
-#define TCSETAF                _IOW('t', 28, struct termio)
-
-#define TCSBRK         _IO('t', 29)
-#define TCXONC         _IO('t', 30)
-#define TCFLSH         _IO('t', 31)
-
-#define TIOCSWINSZ     _IOW('t', 103, struct winsize)
-#define TIOCGWINSZ     _IOR('t', 104, struct winsize)
-#define        TIOCSTART       _IO('t', 110)           /* start output, like ^Q */
-#define        TIOCSTOP        _IO('t', 111)           /* stop output, like ^S */
-#define TIOCOUTQ        _IOR('t', 115, int)     /* output queue size */
-
-#define TIOCSPGRP      _IOW('t', 118, int)
-#define TIOCGPGRP      _IOR('t', 119, int)
-
-#define TIOCEXCL       _IO('T', 12) /* 0x540C */
-#define TIOCNXCL       _IO('T', 13) /* 0x540D */
-#define TIOCSCTTY      _IO('T', 14) /* 0x540E */
-
-#define TIOCSTI                _IOW('T', 18, char) /* 0x5412 */
-#define TIOCMGET       _IOR('T', 21, unsigned int) /* 0x5415 */
-#define TIOCMBIS       _IOW('T', 22, unsigned int) /* 0x5416 */
-#define TIOCMBIC       _IOW('T', 23, unsigned int) /* 0x5417 */
-#define TIOCMSET       _IOW('T', 24, unsigned int) /* 0x5418 */
-# define TIOCM_LE      0x001
-# define TIOCM_DTR     0x002
-# define TIOCM_RTS     0x004
-# define TIOCM_ST      0x008
-# define TIOCM_SR      0x010
-# define TIOCM_CTS     0x020
-# define TIOCM_CAR     0x040
-# define TIOCM_RNG     0x080
-# define TIOCM_DSR     0x100
-# define TIOCM_CD      TIOCM_CAR
-# define TIOCM_RI      TIOCM_RNG
-
-#define TIOCGSOFTCAR   _IOR('T', 25, unsigned int) /* 0x5419 */
-#define TIOCSSOFTCAR   _IOW('T', 26, unsigned int) /* 0x541A */
-#define TIOCLINUX      _IOW('T', 28, char) /* 0x541C */
-#define TIOCCONS       _IO('T', 29) /* 0x541D */
-#define TIOCGSERIAL    _IOR('T', 30, struct serial_struct) /* 0x541E */
-#define TIOCSSERIAL    _IOW('T', 31, struct serial_struct) /* 0x541F */
-#define TIOCPKT                _IOW('T', 32, int) /* 0x5420 */
-# define TIOCPKT_DATA           0
-# define TIOCPKT_FLUSHREAD      1
-# define TIOCPKT_FLUSHWRITE     2
-# define TIOCPKT_STOP           4
-# define TIOCPKT_START          8
-# define TIOCPKT_NOSTOP                16
-# define TIOCPKT_DOSTOP                32
-
-
-#define TIOCNOTTY      _IO('T', 34) /* 0x5422 */
-#define TIOCSETD       _IOW('T', 35, int) /* 0x5423 */
-#define TIOCGETD       _IOR('T', 36, int) /* 0x5424 */
-#define TCSBRKP                _IOW('T', 37, int) /* 0x5425 */ /* Needed for POSIX tcsendbreak() */
-#define TIOCTTYGSTRUCT _IOR('T', 38, struct tty_struct) /* 0x5426 */ /* For debugging only */
-#define TIOCSBRK       _IO('T', 39) /* 0x5427 */ /* BSD compatibility */
-#define TIOCCBRK       _IO('T', 40) /* 0x5428 */ /* BSD compatibility */
-#define TIOCGSID       _IOR('T', 41, pid_t) /* 0x5429 */ /* Return the session ID of FD */
-#define TIOCGPTN       _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
-#define TIOCSPTLCK     _IOW('T',0x31, int)  /* Lock/unlock Pty */
-
-#define TIOCSERCONFIG  _IO('T', 83) /* 0x5453 */
-#define TIOCSERGWILD   _IOR('T', 84,  int) /* 0x5454 */
-#define TIOCSERSWILD   _IOW('T', 85,  int) /* 0x5455 */
+#define TCGETA         0x80127417      /* _IOR('t', 23, struct termio) */
+#define TCSETA         0x40127418      /* _IOW('t', 24, struct termio) */
+#define TCSETAW                0x40127419      /* _IOW('t', 25, struct termio) */
+#define TCSETAF                0x4012741c      /* _IOW('t', 28, struct termio) */
+
+#define TCSBRK         0x741d          /* _IO('t', 29) */
+#define TCXONC         0x741e          /* _IO('t', 30) */
+#define TCFLSH         0x741f          /* _IO('t', 31) */
+
+#define TIOCSWINSZ     0x40087467      /* _IOW('t', 103, struct winsize) */
+#define TIOCGWINSZ     0x80087468      /* _IOR('t', 104, struct winsize) */
+#define        TIOCSTART       0x746e          /* _IO('t', 110)  start output, like ^Q */
+#define        TIOCSTOP        0x746f          /* _IO('t', 111)  stop output, like ^S */
+#define TIOCOUTQ        0x80047473     /* _IOR('t', 115, int) output queue size */
+
+#define TIOCSPGRP      0x40047476      /* _IOW('t', 118, int) */
+#define TIOCGPGRP      0x80047477      /* _IOR('t', 119, int) */
+
+#define TIOCEXCL       0x540c          /* _IO('T', 12) */
+#define TIOCNXCL       0x540d          /* _IO('T', 13) */
+#define TIOCSCTTY      0x540e          /* _IO('T', 14) */
+
+#define TIOCSTI                0x40015412      /* _IOW('T', 18, char) 0x5412 */
+#define TIOCMGET       0x80045415      /* _IOR('T', 21, unsigned int) 0x5415 */
+#define TIOCMBIS       0x40045416      /* _IOW('T', 22, unsigned int) 0x5416 */
+#define TIOCMBIC       0x40045417      /* _IOW('T', 23, unsigned int) 0x5417 */
+#define TIOCMSET       0x40045418      /* _IOW('T', 24, unsigned int) 0x5418 */
+
+#define TIOCM_LE       0x001
+#define TIOCM_DTR      0x002
+#define TIOCM_RTS      0x004
+#define TIOCM_ST       0x008
+#define TIOCM_SR       0x010
+#define TIOCM_CTS      0x020
+#define TIOCM_CAR      0x040
+#define TIOCM_RNG      0x080
+#define TIOCM_DSR      0x100
+#define TIOCM_CD       TIOCM_CAR
+#define TIOCM_RI       TIOCM_RNG
+
+#define TIOCGSOFTCAR   0x80045419      /* _IOR('T', 25, unsigned int) 0x5419 */
+#define TIOCSSOFTCAR   0x4004541a      /* _IOW('T', 26, unsigned int) 0x541A */
+#define TIOCLINUX      0x4004541c      /* _IOW('T', 28, char) 0x541C */
+#define TIOCCONS       0x541d          /* _IO('T', 29) */
+#define TIOCGSERIAL    0x803c541e      /* _IOR('T', 30, struct serial_struct) 0x541E */
+#define TIOCSSERIAL    0x403c541f      /* _IOW('T', 31, struct serial_struct) 0x541F */
+#define TIOCPKT                0x40045420      /* _IOW('T', 32, int) 0x5420 */
+
+#define TIOCPKT_DATA            0
+#define TIOCPKT_FLUSHREAD       1
+#define TIOCPKT_FLUSHWRITE      2
+#define TIOCPKT_STOP            4
+#define TIOCPKT_START           8
+#define TIOCPKT_NOSTOP         16
+#define TIOCPKT_DOSTOP         32
+
+
+#define TIOCNOTTY      0x5422          /* _IO('T', 34) */
+#define TIOCSETD       0x40045423      /* _IOW('T', 35, int) 0x5423 */
+#define TIOCGETD       0x80045424      /* _IOR('T', 36, int) 0x5424 */
+#define TCSBRKP                0x40045424      /* _IOW('T', 37, int) 0x5425 */ /* Needed for POSIX tcsendbreak() */
+#define TIOCTTYGSTRUCT 0x8c105426      /* _IOR('T', 38, struct tty_struct) 0x5426 */ /* For debugging only */
+#define TIOCSBRK       0x5427          /* _IO('T', 39) */ /* BSD compatibility */
+#define TIOCCBRK       0x5428          /* _IO('T', 40) */ /* BSD compatibility */
+#define TIOCGSID       0x80045429      /* _IOR('T', 41, pid_t) 0x5429 */ /* Return the session ID of FD */
+#define TIOCGPTN       0x80045430      /* _IOR('T',0x30, unsigned int) 0x5430 Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK     0x40045431      /* _IOW('T',0x31, int) Lock/unlock Pty */
+
+#define TIOCSERCONFIG  0x5453          /* _IO('T', 83) */
+#define TIOCSERGWILD   0x80045454      /* _IOR('T', 84,  int) 0x5454 */
+#define TIOCSERSWILD   0x40045455      /* _IOW('T', 85,  int) 0x5455 */

 #define TIOCGLCKTRMIOS 0x5456
 #define TIOCSLCKTRMIOS 0x5457
 #define TIOCGLCKTRMIOS 0x5456
 #define TIOCSLCKTRMIOS 0x5457

-#define TIOCSERGSTRUCT _IOR('T', 88, struct async_struct) /* 0x5458 */ /* For debugging only */
-#define TIOCSERGETLSR   _IOR('T', 89, unsigned int) /* 0x5459 */ /* Get line status register */
-  /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-# define TIOCSER_TEMT    0x01  /* Transmitter physically empty */
-#define TIOCSERGETMULTI _IOR('T', 90, struct serial_multiport_struct) /* 0x545A */ /* Get multiport config  */
-#define TIOCSERSETMULTI _IOW('T', 91, struct serial_multiport_struct) /* 0x545B */ /* Set multiport config */
-
-#define TIOCMIWAIT     _IO('T', 92) /* 0x545C */       /* wait for a change on serial input line(s) */
-#define TIOCGICOUNT    _IOR('T', 93, struct async_icount) /* 0x545D */ /* read serial port inline interrupt counts */
+#define TIOCSERGSTRUCT 0x80d85458      /* _IOR('T', 88, struct async_struct) 0x5458 */ /* For debugging only */
+#define TIOCSERGETLSR   0x80045459     /* _IOR('T', 89, unsigned int) 0x5459 */ /* Get line status register */
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+#define TIOCSER_TEMT    0x01   /* Transmitter physically empty */
+
+#define TIOCSERGETMULTI 0x80a8545a     /* _IOR('T', 90, struct serial_multiport_struct) 0x545A */ /* Get multiport config  */
+#define TIOCSERSETMULTI 0x40a8545b     /* _IOW('T', 91, struct serial_multiport_struct) 0x545B */ /* Set multiport config */
+
+#define TIOCMIWAIT     0x545c          /* _IO('T', 92) wait for a change on serial input line(s) */
+#define TIOCGICOUNT    0x802c545d      /* _IOR('T', 93, struct async_icount) 0x545D */ /* read serial port inline interrupt counts */

 
 #endif /* __ASM_SH64_IOCTLS_H */
 
 #endif /* __ASM_SH64_IOCTLS_H */

diff --git a/include/asm-sh64/ipc.h b/include/asm-sh64/ipc.h
index d8d9389..a46e3d9 100644 (file)
--- a/include/asm-sh64/ipc.h
+++ b/include/asm-sh64/ipc.h
@@ -1,6 +1 @@
-#ifndef __ASM_SH64_IPC_H
-#define __ASM_SH64_IPC_H
-
-#include <asm-sh/ipc.h>
-
-#endif /* __ASM_SH64_IPC_H */
+#include <asm-generic/ipc.h>

diff --git a/include/asm-sh64/module.h b/include/asm-sh64/module.h
index bf382bc..c313650 100644 (file)
--- a/include/asm-sh64/module.h
+++ b/include/asm-sh64/module.h
@@ -4,6 +4,14 @@
  * This file contains the SH architecture specific module code.
  */
 
  * This file contains the SH architecture specific module code.
  */
 

+struct mod_arch_specific {
+       /* empty */
+};
+
+#define Elf_Shdr               Elf32_Shdr
+#define Elf_Sym                        Elf32_Sym
+#define Elf_Ehdr               Elf32_Ehdr
+

 #define module_map(x)          vmalloc(x)
 #define module_unmap(x)                vfree(x)
 #define module_arch_init(x)    (0)
 #define module_map(x)          vmalloc(x)
 #define module_unmap(x)                vfree(x)
 #define module_arch_init(x)    (0)

diff --git a/include/asm-sh64/thread_info.h b/include/asm-sh64/thread_info.h
index 99e7c92..8a32d6b 100644 (file)
--- a/include/asm-sh64/thread_info.h
+++ b/include/asm-sh64/thread_info.h
@@ -61,14 +61,19 @@ static inline struct thread_info *current_thread_info(void)
 }
 
 /* thread information allocation */
 }
 
 /* thread information allocation */

-#define alloc_thread_info(ti) ((struct thread_info *) __get_free_pages(GFP_KERNEL,2))
+
+
+
+#define alloc_thread_info(ti) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1))

 #define free_thread_info(ti) free_pages((unsigned long) (ti), 1)
 #define get_thread_info(ti) get_task_struct((ti)->task)
 #define put_thread_info(ti) put_task_struct((ti)->task)
 
 #endif /* __ASSEMBLY__ */
 
 #define free_thread_info(ti) free_pages((unsigned long) (ti), 1)
 #define get_thread_info(ti) get_task_struct((ti)->task)
 #define put_thread_info(ti) put_task_struct((ti)->task)
 
 #endif /* __ASSEMBLY__ */
 

-#define PREEMPT_ACTIVE         0x4000000
+#define THREAD_SIZE  8192
+
+#define PREEMPT_ACTIVE         0x10000000

 
 /* thread information flags */
 #define TIF_SYSCALL_TRACE      0       /* syscall trace active */
 
 /* thread information flags */
 #define TIF_SYSCALL_TRACE      0       /* syscall trace active */


@@ -76,7 +81,6 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_NEED_RESCHED       3       /* rescheduling necessary */
 #define TIF_MEMDIE             4
 
 #define TIF_NEED_RESCHED       3       /* rescheduling necessary */
 #define TIF_MEMDIE             4
 

-#define THREAD_SIZE    16384

 
 #endif /* __KERNEL__ */
 
 
 #endif /* __KERNEL__ */
 

diff --git a/include/asm-sh64/unaligned.h b/include/asm-sh64/unaligned.h
index ad22487..74481b1 100644 (file)
--- a/include/asm-sh64/unaligned.h
+++ b/include/asm-sh64/unaligned.h
@@ -12,17 +12,6 @@
  *
  */
 
  *
  */
 

-#include <linux/string.h>
-
-
-/* Use memmove here, so gcc does not insert a __builtin_memcpy. */
-
-#define get_unaligned(ptr) \
-  ({ __typeof__(*(ptr)) __tmp; memmove(&__tmp, (ptr), sizeof(*(ptr))); __tmp; })
-
-#define put_unaligned(val, ptr)                                \
-  ({ __typeof__(*(ptr)) __tmp = (val);                 \
-     memmove((ptr), &__tmp, sizeof(*(ptr)));           \
-     (void)0; })
+#include <asm-generic/unaligned.h>

 
 #endif /* __ASM_SH64_UNALIGNED_H */
 
 #endif /* __ASM_SH64_UNALIGNED_H */

diff --git a/include/asm-um/archparam-x86_64.h b/include/asm-um/archparam-x86_64.h
index 96321c4..270ed95 100644 (file)
--- a/include/asm-um/archparam-x86_64.h
+++ b/include/asm-um/archparam-x86_64.h
@@ -7,42 +7,6 @@
 #ifndef __UM_ARCHPARAM_X86_64_H
 #define __UM_ARCHPARAM_X86_64_H
 
 #ifndef __UM_ARCHPARAM_X86_64_H
 #define __UM_ARCHPARAM_X86_64_H
 

-#include <asm/user.h>
-
-#define ELF_PLATFORM "x86_64"
-
-#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
-
-typedef unsigned long elf_greg_t;
-typedef struct { } elf_fpregset_t;
-
-#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-#define ELF_DATA        ELFDATA2LSB
-#define ELF_ARCH        EM_X86_64
-
-#define ELF_PLAT_INIT(regs, load_addr)    do { \
-       PT_REGS_RBX(regs) = 0; \
-       PT_REGS_RCX(regs) = 0; \
-       PT_REGS_RDX(regs) = 0; \
-       PT_REGS_RSI(regs) = 0; \
-       PT_REGS_RDI(regs) = 0; \
-       PT_REGS_RBP(regs) = 0; \
-       PT_REGS_RAX(regs) = 0; \
-       PT_REGS_R8(regs) = 0; \
-       PT_REGS_R9(regs) = 0; \
-       PT_REGS_R10(regs) = 0; \
-       PT_REGS_R11(regs) = 0; \
-       PT_REGS_R12(regs) = 0; \
-       PT_REGS_R13(regs) = 0; \
-       PT_REGS_R14(regs) = 0; \
-       PT_REGS_R15(regs) = 0; \
-} while (0)
-
-#ifdef TIF_IA32 /* XXX */
-        clear_thread_flag(TIF_IA32);
-#endif

 
 /* No user-accessible fixmap addresses, i.e. vsyscall */
 #define FIXADDR_USER_START     0
 
 /* No user-accessible fixmap addresses, i.e. vsyscall */
 #define FIXADDR_USER_START     0

diff --git a/include/asm-um/setup.h b/include/asm-um/setup.h
index e5787bb..99f0863 100644 (file)
--- a/include/asm-um/setup.h
+++ b/include/asm-um/setup.h
@@ -1,6 +1,10 @@
 #ifndef SETUP_H_INCLUDED
 #define SETUP_H_INCLUDED
 
 #ifndef SETUP_H_INCLUDED
 #define SETUP_H_INCLUDED
 

-#define COMMAND_LINE_SIZE 512
+/* POSIX mandated with _POSIX_ARG_MAX that we can rely on 4096 chars in the
+ * command line, so this choice is ok.
+ */
+
+#define COMMAND_LINE_SIZE 4096

 
 #endif         /* SETUP_H_INCLUDED */
 
 #endif         /* SETUP_H_INCLUDED */

diff --git a/include/linux/transport_class.h b/include/linux/transport_class.h
index 57e6020..87d98d1 100644 (file)
--- a/include/linux/transport_class.h
+++ b/include/linux/transport_class.h
@@ -48,6 +48,14 @@ struct anon_transport_class cls = {                          \
 #define class_to_transport_class(x) \
        container_of(x, struct transport_class, class)
 
 #define class_to_transport_class(x) \
        container_of(x, struct transport_class, class)
 

+struct transport_container {
+       struct attribute_container ac;
+       struct attribute_group *statistics;
+};
+
+#define attribute_container_to_transport_container(x) \
+       container_of(x, struct transport_container, ac)
+

 void transport_remove_device(struct device *);
 void transport_add_device(struct device *);
 void transport_setup_device(struct device *);
 void transport_remove_device(struct device *);
 void transport_add_device(struct device *);
 void transport_setup_device(struct device *);


@@ -68,6 +76,16 @@ transport_unregister_device(struct device *dev)
        transport_destroy_device(dev);
 }
 
        transport_destroy_device(dev);
 }
 

+static inline int transport_container_register(struct transport_container *tc)
+{
+       return attribute_container_register(&tc->ac);
+}
+
+static inline int transport_container_unregister(struct transport_container *tc)
+{
+       return attribute_container_unregister(&tc->ac);
+}
+

 int transport_class_register(struct transport_class *);
 int anon_transport_class_register(struct anon_transport_class *);
 void transport_class_unregister(struct transport_class *);
 int transport_class_register(struct transport_class *);
 int anon_transport_class_register(struct anon_transport_class *);
 void transport_class_unregister(struct transport_class *);

diff --git a/net/bridge/br_sysfs_if.c b/net/bridge/br_sysfs_if.c
index 567249b..f6a19d5 100644 (file)
--- a/net/bridge/br_sysfs_if.c
+++ b/net/bridge/br_sysfs_if.c
@@ -248,6 +248,7 @@ int br_sysfs_addif(struct net_bridge_port *p)
        if (err)
                goto out2;
 
        if (err)
                goto out2;
 

+       kobject_hotplug(&p->kobj, KOBJ_ADD);

        return 0;
  out2:
        kobject_del(&p->kobj);
        return 0;
  out2:
        kobject_del(&p->kobj);


@@ -259,6 +260,7 @@ void br_sysfs_removeif(struct net_bridge_port *p)
 {
        pr_debug("br_sysfs_removeif\n");
        sysfs_remove_link(&p->br->ifobj, p->dev->name);
 {
        pr_debug("br_sysfs_removeif\n");
        sysfs_remove_link(&p->br->ifobj, p->dev->name);

+       kobject_hotplug(&p->kobj, KOBJ_REMOVE);

        kobject_del(&p->kobj);
 }
 
        kobject_del(&p->kobj);
 }
 

diff --git a/sound/pci/emu10k1/timer.c b/sound/pci/emu10k1/timer.c
index c9c421a..d2e3646 100644 (file)
--- a/sound/pci/emu10k1/timer.c
+++ b/sound/pci/emu10k1/timer.c
@@ -1,10 +1,8 @@
 /*
  *  Copyright (c) by Lee Revell <rlrevell@joe-job.com>
 /*
  *  Copyright (c) by Lee Revell <rlrevell@joe-job.com>

- *  
+ *                   Clemens Ladisch <clemens@ladisch.de>

  *  Routines for control of EMU10K1 chips
  *
  *  Routines for control of EMU10K1 chips
  *

- *  Copied from similar code by Clemens Ladisch in the ymfpci driver
- * 

  *  BUGS:
  *    --
  *
  *  BUGS:
  *    --
  *