- sync with fedora branch

diff --git a/include/asm-arm/arch-iop3xx/iop310-irqs.h b/include/asm-arm/arch-iop3xx/iop310-irqs.h
deleted file mode 100644 (file)
index f468a28..0000000
--- a/include/asm-arm/arch-iop3xx/iop310-irqs.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * linux/include/asm-arm/arch-iop310/irqs.h
- *
- * Author:     Nicolas Pitre
- * Copyright:  (C) 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * 06/13/01: Added 80310 on-chip interrupt sources <dsaxena@mvista.com>
- *
- */
-#include <linux/config.h>
-
-/*
- * XS80200 specific IRQs
- */
-#define IRQ_XS80200_BCU                0       /* Bus Control Unit */
-#define IRQ_XS80200_PMU                1       /* Performance Monitoring Unit */
-#define IRQ_XS80200_EXTIRQ     2       /* external IRQ signal */
-#define IRQ_XS80200_EXTFIQ     3       /* external IRQ signal */
-
-#define NR_XS80200_IRQS                4
-
-#define XSCALE_PMU_IRQ         IRQ_XS80200_PMU
-
-/*
- * IOP80310 chipset interrupts
- */
-#define IOP310_IRQ_OFS         NR_XS80200_IRQS
-#define IOP310_IRQ(x)          (IOP310_IRQ_OFS + (x))
-
-/*
- * On FIQ1ISR register
- */
-#define IRQ_IOP310_DMA0                IOP310_IRQ(0)   /* DMA Channel 0 */
-#define IRQ_IOP310_DMA1                IOP310_IRQ(1)   /* DMA Channel 1 */
-#define IRQ_IOP310_DMA2                IOP310_IRQ(2)   /* DMA Channel 2 */
-#define IRQ_IOP310_PMON                IOP310_IRQ(3)   /* Bus performance Unit */
-#define IRQ_IOP310_AAU         IOP310_IRQ(4)   /* Application Accelator Unit */
-
-/*
- * On FIQ2ISR register
- */
-#define IRQ_IOP310_I2C         IOP310_IRQ(5)   /* I2C unit */
-#define IRQ_IOP310_MU          IOP310_IRQ(6)   /* messaging unit */
-
-#define NR_IOP310_IRQS         (IOP310_IRQ(6) + 1)
-
-#define NR_IRQS                        NR_IOP310_IRQS
-
-
-/*
- * Interrupts available on the Cyclone IQ80310 board
- */
-#ifdef CONFIG_ARCH_IQ80310
-
-#define IQ80310_IRQ_OFS                NR_IOP310_IRQS
-#define IQ80310_IRQ(y)         ((IQ80310_IRQ_OFS) + (y))
-
-#define IRQ_IQ80310_TIMER      IQ80310_IRQ(0)  /* Timer Interrupt */
-#define IRQ_IQ80310_I82559     IQ80310_IRQ(1)  /* I82559 Ethernet Interrupt */
-#define IRQ_IQ80310_UART1      IQ80310_IRQ(2)  /* UART1 Interrupt */
-#define IRQ_IQ80310_UART2      IQ80310_IRQ(3)  /* UART2 Interrupt */
-#define IRQ_IQ80310_INTD       IQ80310_IRQ(4)  /* PCI INTD */
-
-
-/*
- * ONLY AVAILABLE ON REV F OR NEWER BOARDS!
- */
-#define        IRQ_IQ80310_INTA        IQ80310_IRQ(5)  /* PCI INTA */
-#define        IRQ_IQ80310_INTB        IQ80310_IRQ(6)  /* PCI INTB */
-#define        IRQ_IQ80310_INTC        IQ80310_IRQ(7)  /* PCI INTC */
-
-#undef NR_IRQS
-#define NR_IRQS                        (IQ80310_IRQ(7) + 1)
-
-#endif // CONFIG_ARCH_IQ80310
-

diff --git a/include/asm-arm/arch-iop3xx/iop310.h b/include/asm-arm/arch-iop3xx/iop310.h
deleted file mode 100644 (file)
index a68ac48..0000000
--- a/include/asm-arm/arch-iop3xx/iop310.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * linux/include/asm/arch-iop3xx/iop310.h
- *
- * Intel IOP310 Companion Chip definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _IOP310_HW_H_
-#define _IOP310_HW_H_
-
-/*
- * This is needed for mixed drivers that need to work on all
- * IOP3xx variants but behave slightly differently on each.
- */
-#ifndef __ASSEMBLY__
-#define iop_is_310() ((processor_id & 0xffffe3f0) == 0x69052000)
-#endif
-
-/*
- * IOP310 I/O and Mem space regions for PCI autoconfiguration
- */
-#define IOP310_PCISEC_LOWER_IO         0x90010000
-#define IOP310_PCISEC_UPPER_IO         0x9001ffff
-#define IOP310_PCISEC_LOWER_MEM                0x88000000
-#define IOP310_PCISEC_UPPER_MEM                0x8bffffff
-
-#define IOP310_PCIPRI_LOWER_IO         0x90000000
-#define IOP310_PCIPRI_UPPER_IO         0x9000ffff
-#define IOP310_PCIPRI_LOWER_MEM                0x80000000
-#define IOP310_PCIPRI_UPPER_MEM                0x83ffffff
-
-#define IOP310_PCI_WINDOW_SIZE         64 * 0x100000
-
-/*
- * IOP310 chipset registers
- */
-#define IOP310_VIRT_MEM_BASE 0xe8001000  /* chip virtual mem address*/
-#define IOP310_PHY_MEM_BASE  0x00001000  /* chip physical memory address */
-#define IOP310_REG_ADDR(reg) (IOP310_VIRT_MEM_BASE | IOP310_PHY_MEM_BASE | (reg))
-
-/* PCI-to-PCI Bridge Unit 0x00001000 through 0x000010FF */
-#define IOP310_VIDR    (volatile u16 *)IOP310_REG_ADDR(0x00001000)
-#define IOP310_DIDR    (volatile u16 *)IOP310_REG_ADDR(0x00001002)
-#define IOP310_PCR     (volatile u16 *)IOP310_REG_ADDR(0x00001004)
-#define IOP310_PSR     (volatile u16 *)IOP310_REG_ADDR(0x00001006)
-#define IOP310_RIDR    (volatile u8  *)IOP310_REG_ADDR(0x00001008)
-#define IOP310_CCR     (volatile u32 *)IOP310_REG_ADDR(0x00001009)
-#define IOP310_CLSR    (volatile u8  *)IOP310_REG_ADDR(0x0000100C)
-#define IOP310_PLTR    (volatile u8  *)IOP310_REG_ADDR(0x0000100D)
-#define IOP310_HTR     (volatile u8  *)IOP310_REG_ADDR(0x0000100E)
-/* Reserved 0x0000100F through  0x00001017 */
-#define IOP310_PBNR    (volatile u8  *)IOP310_REG_ADDR(0x00001018)
-#define IOP310_SBNR    (volatile u8  *)IOP310_REG_ADDR(0x00001019)
-#define IOP310_SUBBNR  (volatile u8  *)IOP310_REG_ADDR(0x0000101A)
-#define IOP310_SLTR    (volatile u8  *)IOP310_REG_ADDR(0x0000101B)
-#define IOP310_IOBR    (volatile u8  *)IOP310_REG_ADDR(0x0000101C)
-#define IOP310_IOLR    (volatile u8  *)IOP310_REG_ADDR(0x0000101D)
-#define IOP310_SSR     (volatile u16 *)IOP310_REG_ADDR(0x0000101E)
-#define IOP310_MBR     (volatile u16 *)IOP310_REG_ADDR(0x00001020)
-#define IOP310_MLR     (volatile u16 *)IOP310_REG_ADDR(0x00001022)
-#define IOP310_PMBR    (volatile u16 *)IOP310_REG_ADDR(0x00001024)
-#define IOP310_PMLR    (volatile u16 *)IOP310_REG_ADDR(0x00001026)
-/* Reserved 0x00001028 through 0x00001033 */
-#define IOP310_CAPR    (volatile u8  *)IOP310_REG_ADDR(0x00001034)
-/* Reserved 0x00001035 through 0x0000103D */
-#define IOP310_BCR     (volatile u16 *)IOP310_REG_ADDR(0x0000103E)
-#define IOP310_EBCR    (volatile u16 *)IOP310_REG_ADDR(0x00001040)
-#define IOP310_SISR    (volatile u16 *)IOP310_REG_ADDR(0x00001042)
-#define IOP310_PBISR   (volatile u32 *)IOP310_REG_ADDR(0x00001044)
-#define IOP310_SBISR   (volatile u32 *)IOP310_REG_ADDR(0x00001048)
-#define IOP310_SACR    (volatile u32 *)IOP310_REG_ADDR(0x0000104C)
-#define IOP310_PIRSR   (volatile u32 *)IOP310_REG_ADDR(0x00001050)
-#define IOP310_SIOBR   (volatile u8  *)IOP310_REG_ADDR(0x00001054)
-#define IOP310_SIOLR   (volatile u8  *)IOP310_REG_ADDR(0x00001055)
-#define IOP310_SCDR    (volatile u8  *)IOP310_REG_ADDR(0x00001056)
-
-#define IOP310_SMBR    (volatile u16 *)IOP310_REG_ADDR(0x00001058)
-#define IOP310_SMLR    (volatile u16 *)IOP310_REG_ADDR(0x0000105A)
-#define IOP310_SDER    (volatile u16 *)IOP310_REG_ADDR(0x0000105C)
-#define IOP310_QCR     (volatile u16 *)IOP310_REG_ADDR(0x0000105E)
-#define IOP310_CAPID   (volatile u8  *)IOP310_REG_ADDR(0x00001068)
-#define IOP310_NIPTR   (volatile u8  *)IOP310_REG_ADDR(0x00001069)
-#define IOP310_PMCR    (volatile u16 *)IOP310_REG_ADDR(0x0000106A)
-#define IOP310_PMCSR   (volatile u16 *)IOP310_REG_ADDR(0x0000106C)
-#define IOP310_PMCSRBSE (volatile u8 *)IOP310_REG_ADDR(0x0000106E)
-/* Reserved 0x00001064 through 0x000010FFH */
-
-/* Performance monitoring unit  0x00001100 through 0x000011FF*/
-#define IOP310_PMONGTMR    (volatile u32 *)IOP310_REG_ADDR(0x00001100)
-#define IOP310_PMONESR     (volatile u32 *)IOP310_REG_ADDR(0x00001104)
-#define IOP310_PMONEMISR   (volatile u32 *)IOP310_REG_ADDR(0x00001108)
-#define IOP310_PMONGTSR    (volatile u32 *)IOP310_REG_ADDR(0x00001110)
-#define IOP310_PMONPECR1   (volatile u32 *)IOP310_REG_ADDR(0x00001114)
-#define IOP310_PMONPECR2   (volatile u32 *)IOP310_REG_ADDR(0x00001118)
-#define IOP310_PMONPECR3   (volatile u32 *)IOP310_REG_ADDR(0x0000111C)
-#define IOP310_PMONPECR4   (volatile u32 *)IOP310_REG_ADDR(0x00001120)
-#define IOP310_PMONPECR5   (volatile u32 *)IOP310_REG_ADDR(0x00001124)
-#define IOP310_PMONPECR6   (volatile u32 *)IOP310_REG_ADDR(0x00001128)
-#define IOP310_PMONPECR7   (volatile u32 *)IOP310_REG_ADDR(0x0000112C)
-#define IOP310_PMONPECR8   (volatile u32 *)IOP310_REG_ADDR(0x00001130)
-#define IOP310_PMONPECR9   (volatile u32 *)IOP310_REG_ADDR(0x00001134)
-#define IOP310_PMONPECR10  (volatile u32 *)IOP310_REG_ADDR(0x00001138)
-#define IOP310_PMONPECR11  (volatile u32 *)IOP310_REG_ADDR(0x0000113C)
-#define IOP310_PMONPECR12  (volatile u32 *)IOP310_REG_ADDR(0x00001140)
-#define IOP310_PMONPECR13  (volatile u32 *)IOP310_REG_ADDR(0x00001144)
-#define IOP310_PMONPECR14  (volatile u32 *)IOP310_REG_ADDR(0x00001148)
-
-/* Address Translation Unit 0x00001200 through 0x000012FF */
-#define IOP310_ATUVID     (volatile u16 *)IOP310_REG_ADDR(0x00001200)
-#define IOP310_ATUDID     (volatile u16 *)IOP310_REG_ADDR(0x00001202)
-#define IOP310_PATUCMD    (volatile u16 *)IOP310_REG_ADDR(0x00001204)
-#define IOP310_PATUSR     (volatile u16 *)IOP310_REG_ADDR(0x00001206)
-#define IOP310_ATURID     (volatile u8  *)IOP310_REG_ADDR(0x00001208)
-#define IOP310_ATUCCR     (volatile u32 *)IOP310_REG_ADDR(0x00001209)
-#define IOP310_ATUCLSR    (volatile u8  *)IOP310_REG_ADDR(0x0000120C)
-#define IOP310_ATULT      (volatile u8  *)IOP310_REG_ADDR(0x0000120D)
-#define IOP310_ATUHTR     (volatile u8  *)IOP310_REG_ADDR(0x0000120E)
-
-#define IOP310_PIABAR     (volatile u32 *)IOP310_REG_ADDR(0x00001210)
-/* Reserved 0x00001214 through 0x0000122B */
-#define IOP310_ASVIR      (volatile u16 *)IOP310_REG_ADDR(0x0000122C)
-#define IOP310_ASIR       (volatile u16 *)IOP310_REG_ADDR(0x0000122E)
-#define IOP310_ERBAR      (volatile u32 *)IOP310_REG_ADDR(0x00001230)
-#define IOP310_ATUCAPPTR  (volatile u8  *)IOP310_REG_ADDR(0x00001234)
-/* Reserved 0x00001235 through 0x0000123B */
-#define IOP310_ATUILR     (volatile u8  *)IOP310_REG_ADDR(0x0000123C)
-#define IOP310_ATUIPR     (volatile u8  *)IOP310_REG_ADDR(0x0000123D)
-#define IOP310_ATUMGNT    (volatile u8  *)IOP310_REG_ADDR(0x0000123E)
-#define IOP310_ATUMLAT    (volatile u8  *)IOP310_REG_ADDR(0x0000123F)
-#define IOP310_PIALR      (volatile u32 *)IOP310_REG_ADDR(0x00001240)
-#define IOP310_PIATVR     (volatile u32 *)IOP310_REG_ADDR(0x00001244)
-#define IOP310_SIABAR     (volatile u32 *)IOP310_REG_ADDR(0x00001248)
-#define IOP310_SIALR      (volatile u32 *)IOP310_REG_ADDR(0x0000124C)
-#define IOP310_SIATVR     (volatile u32 *)IOP310_REG_ADDR(0x00001250)
-#define IOP310_POMWVR     (volatile u32 *)IOP310_REG_ADDR(0x00001254)
-/* Reserved 0x00001258 through 0x0000125B */
-#define IOP310_POIOWVR    (volatile u32 *)IOP310_REG_ADDR(0x0000125C)
-#define IOP310_PODWVR     (volatile u32 *)IOP310_REG_ADDR(0x00001260)
-#define IOP310_POUDR      (volatile u32 *)IOP310_REG_ADDR(0x00001264)
-#define IOP310_SOMWVR     (volatile u32 *)IOP310_REG_ADDR(0x00001268)
-#define IOP310_SOIOWVR    (volatile u32 *)IOP310_REG_ADDR(0x0000126C)
-/* Reserved 0x00001270 through 0x00001273*/
-#define IOP310_ERLR       (volatile u32 *)IOP310_REG_ADDR(0x00001274)
-#define IOP310_ERTVR      (volatile u32 *)IOP310_REG_ADDR(0x00001278)
-/* Reserved 0x00001279 through 0x0000127C*/
-#define IOP310_ATUCAPID   (volatile u8  *)IOP310_REG_ADDR(0x00001280)
-#define IOP310_ATUNIPTR   (volatile u8  *)IOP310_REG_ADDR(0x00001281)
-#define IOP310_APMCR      (volatile u16 *)IOP310_REG_ADDR(0x00001282)
-#define IOP310_APMCSR     (volatile u16 *)IOP310_REG_ADDR(0x00001284)
-/* Reserved 0x00001286 through 0x00001287 */
-#define IOP310_ATUCR      (volatile u32 *)IOP310_REG_ADDR(0x00001288)
-/* Reserved 0x00001289  through 0x0000128C*/
-#define IOP310_PATUISR    (volatile u32 *)IOP310_REG_ADDR(0x00001290)
-#define IOP310_SATUISR    (volatile u32 *)IOP310_REG_ADDR(0x00001294)
-#define IOP310_SATUCMD    (volatile u16 *)IOP310_REG_ADDR(0x00001298)
-#define IOP310_SATUSR     (volatile u16 *)IOP310_REG_ADDR(0x0000129A)
-#define IOP310_SODWVR     (volatile u32 *)IOP310_REG_ADDR(0x0000129C)
-#define IOP310_SOUDR      (volatile u32 *)IOP310_REG_ADDR(0x000012A0)
-#define IOP310_POCCAR     (volatile u32 *)IOP310_REG_ADDR(0x000012A4)
-#define IOP310_SOCCAR     (volatile u32 *)IOP310_REG_ADDR(0x000012A8)
-#define IOP310_POCCDR     (volatile u32 *)IOP310_REG_ADDR(0x000012AC)
-#define IOP310_SOCCDR     (volatile u32 *)IOP310_REG_ADDR(0x000012B0)
-#define IOP310_PAQCR      (volatile u32 *)IOP310_REG_ADDR(0x000012B4)
-#define IOP310_SAQCR      (volatile u32 *)IOP310_REG_ADDR(0x000012B8)
-#define IOP310_PATUIMR    (volatile u32 *)IOP310_REG_ADDR(0x000012BC)
-#define IOP310_SATUIMR    (volatile u32 *)IOP310_REG_ADDR(0x000012C0)
-/* Reserved 0x000012C4 through 0x000012FF */
-/* Messaging Unit 0x00001300 through 0x000013FF */
-#define IOP310_MUIMR0       (volatile u32 *)IOP310_REG_ADDR(0x00001310)
-#define IOP310_MUIMR1       (volatile u32 *)IOP310_REG_ADDR(0x00001314)
-#define IOP310_MUOMR0       (volatile u32 *)IOP310_REG_ADDR(0x00001318)
-#define IOP310_MUOMR1       (volatile u32 *)IOP310_REG_ADDR(0x0000131C)
-#define IOP310_MUIDR        (volatile u32 *)IOP310_REG_ADDR(0x00001320)
-#define IOP310_MUIISR       (volatile u32 *)IOP310_REG_ADDR(0x00001324)
-#define IOP310_MUIIMR       (volatile u32 *)IOP310_REG_ADDR(0x00001328)
-#define IOP310_MUODR        (volatile u32 *)IOP310_REG_ADDR(0x0000132C)
-#define IOP310_MUOISR       (volatile u32 *)IOP310_REG_ADDR(0x00001330)
-#define IOP310_MUOIMR       (volatile u32 *)IOP310_REG_ADDR(0x00001334)
-#define IOP310_MUMUCR       (volatile u32 *)IOP310_REG_ADDR(0x00001350)
-#define IOP310_MUQBAR       (volatile u32 *)IOP310_REG_ADDR(0x00001354)
-#define IOP310_MUIFHPR      (volatile u32 *)IOP310_REG_ADDR(0x00001360)
-#define IOP310_MUIFTPR      (volatile u32 *)IOP310_REG_ADDR(0x00001364)
-#define IOP310_MUIPHPR      (volatile u32 *)IOP310_REG_ADDR(0x00001368)
-#define IOP310_MUIPTPR      (volatile u32 *)IOP310_REG_ADDR(0x0000136C)
-#define IOP310_MUOFHPR      (volatile u32 *)IOP310_REG_ADDR(0x00001370)
-#define IOP310_MUOFTPR      (volatile u32 *)IOP310_REG_ADDR(0x00001374)
-#define IOP310_MUOPHPR      (volatile u32 *)IOP310_REG_ADDR(0x00001378)
-#define IOP310_MUOPTPR      (volatile u32 *)IOP310_REG_ADDR(0x0000137C)
-#define IOP310_MUIAR        (volatile u32 *)IOP310_REG_ADDR(0x00001380)
-/* DMA Controller 0x00001400 through 0x000014FF */
-#define IOP310_DMA0CCR     (volatile u32 *)IOP310_REG_ADDR(0x00001400)
-#define IOP310_DMA0CSR     (volatile u32 *)IOP310_REG_ADDR(0x00001404)
-/* Reserved 0x001408 through 0x00140B */
-#define IOP310_DMA0DAR     (volatile u32 *)IOP310_REG_ADDR(0x0000140C)
-#define IOP310_DMA0NDAR    (volatile u32 *)IOP310_REG_ADDR(0x00001410)
-#define IOP310_DMA0PADR    (volatile u32 *)IOP310_REG_ADDR(0x00001414)
-#define IOP310_DMA0PUADR   (volatile u32 *)IOP310_REG_ADDR(0x00001418)
-#define IOP310_DMA0LADR    (volatile u32 *)IOP310_REG_ADDR(0x0000141C)
-#define IOP310_DMA0BCR     (volatile u32 *)IOP310_REG_ADDR(0x00001420)
-#define IOP310_DMA0DCR     (volatile u32 *)IOP310_REG_ADDR(0x00001424)
-/* Reserved 0x00001428 through 0x0000143F */
-#define IOP310_DMA1CCR     (volatile u32 *)IOP310_REG_ADDR(0x00001440)
-#define IOP310_DMA1CSR     (volatile u32 *)IOP310_REG_ADDR(0x00001444)
-/* Reserved 0x00001448 through 0x0000144B */
-#define IOP310_DMA1DAR     (volatile u32 *)IOP310_REG_ADDR(0x0000144C)
-#define IOP310_DMA1NDAR    (volatile u32 *)IOP310_REG_ADDR(0x00001450)
-#define IOP310_DMA1PADR    (volatile u32 *)IOP310_REG_ADDR(0x00001454)
-#define IOP310_DMA1PUADR   (volatile u32 *)IOP310_REG_ADDR(0x00001458)
-#define IOP310_DMA1LADR    (volatile u32 *)IOP310_REG_ADDR(0x0000145C)
-#define IOP310_DMA1BCR     (volatile u32 *)IOP310_REG_ADDR(0x00001460)
-#define IOP310_DMA1DCR     (volatile u32 *)IOP310_REG_ADDR(0x00001464)
-/* Reserved 0x00001468 through 0x0000147F */
-#define IOP310_DMA2CCR     (volatile u32 *)IOP310_REG_ADDR(0x00001480)
-#define IOP310_DMA2CSR     (volatile u32 *)IOP310_REG_ADDR(0x00001484)
-/* Reserved 0x00001488 through 0x0000148B */
-#define IOP310_DMA2DAR     (volatile u32 *)IOP310_REG_ADDR(0x0000148C)
-#define IOP310_DMA2NDAR    (volatile u32 *)IOP310_REG_ADDR(0x00001490)
-#define IOP310_DMA2PADR    (volatile u32 *)IOP310_REG_ADDR(0x00001494)
-#define IOP310_DMA2PUADR   (volatile u32 *)IOP310_REG_ADDR(0x00001498)
-#define IOP310_DMA2LADR    (volatile u32 *)IOP310_REG_ADDR(0x0000149C)
-#define IOP310_DMA2BCR     (volatile u32 *)IOP310_REG_ADDR(0x000014A0)
-#define IOP310_DMA2DCR     (volatile u32 *)IOP310_REG_ADDR(0x000014A4)
-
-/* Memory controller 0x00001500 through 0x0015FF */
-
-/* core interface unit 0x00001640 - 0x0000167F */
-#define IOP310_CIUISR     (volatile u32 *)IOP310_REG_ADDR(0x00001644)
-
-/* PCI and Peripheral Interrupt Controller 0x00001700 - 0x0000171B */
-#define IOP310_IRQISR     (volatile u32 *)IOP310_REG_ADDR(0x00001700)
-#define IOP310_FIQ2ISR    (volatile u32 *)IOP310_REG_ADDR(0x00001704)
-#define IOP310_FIQ1ISR    (volatile u32 *)IOP310_REG_ADDR(0x00001708)
-#define IOP310_PDIDR      (volatile u32 *)IOP310_REG_ADDR(0x00001710)
-
-/* AAU registers. DJ 0x00001800 - 0x00001838 */
-#define IOP310_AAUACR    (volatile u32 *)IOP310_REG_ADDR(0x00001800)
-#define IOP310_AAUASR    (volatile u32 *)IOP310_REG_ADDR(0x00001804)
-#define IOP310_AAUADAR   (volatile u32 *)IOP310_REG_ADDR(0x00001808)
-#define IOP310_AAUANDAR  (volatile u32 *)IOP310_REG_ADDR(0x0000180C)
-#define IOP310_AAUSAR1   (volatile u32 *)IOP310_REG_ADDR(0x00001810)
-#define IOP310_AAUSAR2   (volatile u32 *)IOP310_REG_ADDR(0x00001814)
-#define IOP310_AAUSAR3   (volatile u32 *)IOP310_REG_ADDR(0x00001818)
-#define IOP310_AAUSAR4   (volatile u32 *)IOP310_REG_ADDR(0x0000181C)
-#define IOP310_AAUDAR    (volatile u32 *)IOP310_REG_ADDR(0x00001820)
-#define IOP310_AAUABCR   (volatile u32 *)IOP310_REG_ADDR(0x00001824)
-#define IOP310_AAUADCR   (volatile u32 *)IOP310_REG_ADDR(0x00001828)
-#define IOP310_AAUSAR5   (volatile u32 *)IOP310_REG_ADDR(0x0000182C)
-#define IOP310_AAUSAR6   (volatile u32 *)IOP310_REG_ADDR(0x00001830)
-#define IOP310_AAUSAR7   (volatile u32 *)IOP310_REG_ADDR(0x00001834)
-#define IOP310_AAUSAR8   (volatile u32 *)IOP310_REG_ADDR(0x00001838)
-
-#endif // _IOP310_HW_H_

diff --git a/include/asm-arm/arch-iop3xx/iq80310.h b/include/asm-arm/arch-iop3xx/iq80310.h
deleted file mode 100644 (file)
index 85dbda8..0000000
--- a/include/asm-arm/arch-iop3xx/iq80310.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * linux/include/asm/arch-iop80310/iq80310.h
- *
- * Intel IQ-80310 evaluation board registers
- */
-
-#ifndef _IQ80310_H_
-#define _IQ80310_H_
-
-#define IQ80310_RAMBASE      0xa0000000
-#define IQ80310_UART1        0xfe800000    /* UART #1 */
-#define IQ80310_UART2        0xfe810000    /* UART #2 */
-#define IQ80310_INT_STAT     0xfe820000    /* Interrupt (XINT3#) Status */
-#define IQ80310_BOARD_REV    0xfe830000    /* Board revision register */
-#define IQ80310_CPLD_REV     0xfe840000    /* CPLD revision register */
-#define IQ80310_7SEG_1       0xfe840000    /* 7-Segment MSB */
-#define IQ80310_7SEG_0       0xfe850000    /* 7-Segment LSB (WO) */
-#define IQ80310_PCI_INT_STAT 0xfe850000    /* PCI Interrupt  Status */
-#define IQ80310_INT_MASK     0xfe860000    /* Interrupt (XINT3#) Mask */
-#define IQ80310_BACKPLANE    0xfe870000    /* Backplane Detect */
-#define IQ80310_TIMER_LA0    0xfe880000    /* Timer LA0 */
-#define IQ80310_TIMER_LA1    0xfe890000    /* Timer LA1 */
-#define IQ80310_TIMER_LA2    0xfe8a0000    /* Timer LA2 */
-#define IQ80310_TIMER_LA3    0xfe8b0000    /* Timer LA3 */
-#define IQ80310_TIMER_EN     0xfe8c0000    /* Timer Enable */
-#define IQ80310_ROTARY_SW    0xfe8d0000    /* Rotary Switch */
-#define IQ80310_JTAG         0xfe8e0000    /* JTAG Port Access */
-#define IQ80310_BATT_STAT    0xfe8f0000    /* Battery Status */
-
-#endif // _IQ80310_H_

diff --git a/include/asm-arm/arch-iop3xx/pmon.h b/include/asm-arm/arch-iop3xx/pmon.h
deleted file mode 100644 (file)
index 7f93c10..0000000
--- a/include/asm-arm/arch-iop3xx/pmon.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Definitions for XScale 80312 PMON
- * (C) 2001 Intel Corporation
- * Author: Chen Chen(chen.chen@intel.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _IOP310_PMON_H_
-#define _IOP310_PMON_H_
-
-/*
- *  Different modes for Event Select Register for intel 80312
- */
-
-#define IOP310_PMON_MODE0                0x00000000
-#define IOP310_PMON_MODE1                0x00000001
-#define IOP310_PMON_MODE2                0x00000002
-#define IOP310_PMON_MODE3                0x00000003
-#define IOP310_PMON_MODE4                0x00000004
-#define IOP310_PMON_MODE5                0x00000005
-#define IOP310_PMON_MODE6                0x00000006
-#define IOP310_PMON_MODE7                0x00000007
-
-typedef struct _iop310_pmon_result
-{
-       u32 timestamp;                  /* Global Time Stamp Register */
-       u32 timestamp_overflow;         /* Time Stamp overflow count */
-       u32 event_count[14];            /* Programmable Event Counter
-                                          Registers 1-14 */
-       u32 event_overflow[14];         /* Overflow counter for PECR1-14 */
-} iop310_pmon_res_t;
-
-/* function prototypes */
-
-/* Claim IQ80312 PMON for usage */
-int iop310_pmon_claim(void);
-
-/* Start IQ80312 PMON */
-int iop310_pmon_start(int, int);
-
-/* Stop Performance Monitor Unit */
-int iop310_pmon_stop(iop310_pmon_res_t *);
-
-/* Release IQ80312 PMON */
-int iop310_pmon_release(int);
-
-#endif

diff --git a/include/asm-arm/arch-omap/bus.h b/include/asm-arm/arch-omap/bus.h
deleted file mode 100644 (file)
index afb61f8..0000000
--- a/include/asm-arm/arch-omap/bus.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/bus.h
- *
- * Virtual bus for OMAP. Allows better power management, such as managing
- * shared clocks, and mapping of bus addresses to Local Bus addresses.
- *
- * See drivers/usb/host/ohci-omap.c or drivers/video/omap/omapfb.c for
- * examples on how to register drivers to this bus.
- *
- * Copyright (C) 2003 - 2004 Nokia Corporation
- * Written by Tony Lindgren <tony@atomide.com>
- * Portions of code based on sa1111.c.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARM_ARCH_OMAP_BUS_H
-#define __ASM_ARM_ARCH_OMAP_BUS_H
-
-extern struct bus_type omap_bus_types[];
-
-/*
- * Description for physical device
- */
-struct omap_dev {
-       struct device   dev;            /* Standard device description */
-       char            *name;
-       unsigned int    devid;          /* OMAP device id */
-       unsigned int    busid;          /* OMAP virtual busid */
-       struct resource res;            /* Standard resource description */
-       void            *mapbase;       /* OMAP physical address */
-       unsigned int    irq[6];         /* OMAP interrupts */
-       u64             *dma_mask;      /* Used by USB OHCI only */
-       u64             coherent_dma_mask;      /* Used by USB OHCI only */
-};
-
-#define OMAP_DEV(_d)   container_of((_d), struct omap_dev, dev)
-
-#define omap_get_drvdata(d)    dev_get_drvdata(&(d)->dev)
-#define omap_set_drvdata(d,p)  dev_set_drvdata(&(d)->dev, p)
-
-/*
- * Description for device driver
- */
-struct omap_driver {
-       struct device_driver    drv;    /* Standard driver description */
-       unsigned int            devid;  /* OMAP device id for bus */
-       unsigned int            busid;  /* OMAP virtual busid */
-       unsigned int            clocks; /* OMAP shared clocks */
-       int (*probe)(struct omap_dev *);
-       int (*remove)(struct omap_dev *);
-       int (*suspend)(struct omap_dev *, u32);
-       int (*resume)(struct omap_dev *);
-};
-
-#define OMAP_DRV(_d)   container_of((_d), struct omap_driver, drv)
-#define OMAP_DRIVER_NAME(_omapdev) ((_omapdev)->dev.driver->name)
-
-/*
- * Device ID numbers for bus types
- */
-#define OMAP_OCP_DEVID_USB     0
-
-#define OMAP_TIPB_DEVID_OHCI   0
-#define OMAP_TIPB_DEVID_LCD    1
-#define OMAP_TIPB_DEVID_MMC    2
-#define OMAP_TIPB_DEVID_OTG    3
-#define OMAP_TIPB_DEVID_UDC    4
-
-/*
- * Virtual bus definitions for OMAP
- */
-#define OMAP_NR_BUSES  2
-
-#define OMAP_BUS_NAME_TIPB     "tipb"
-#define OMAP_BUS_NAME_LBUS     "lbus"
-
-enum {
-       OMAP_BUS_TIPB = 0,
-       OMAP_BUS_LBUS,
-};
-
-/* See arch/arm/mach-omap/bus.c for the rest of the bus definitions. */
-
-extern int omap_driver_register(struct omap_driver *driver);
-extern void omap_driver_unregister(struct omap_driver *driver);
-extern int omap_device_register(struct omap_dev *odev);
-extern void omap_device_unregister(struct omap_dev *odev);
-
-#endif

diff --git a/include/asm-h8300/softirq.h b/include/asm-h8300/softirq.h
deleted file mode 100644 (file)
index d944be9..0000000
--- a/include/asm-h8300/softirq.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __ASM_SOFTIRQ_H
-#define __ASM_SOFTIRQ_H
-
-#include <linux/preempt.h>
-#include <asm/hardirq.h>
-
-#define local_bh_disable() \
-               do { preempt_count() += SOFTIRQ_OFFSET; barrier(); } while (0)
-#define __local_bh_enable() \
-               do { barrier(); preempt_count() -= SOFTIRQ_OFFSET; } while (0)
-
-#define local_bh_enable()                                              \
-do {                                                                   \
-       __local_bh_enable();                                            \
-       if (unlikely(!in_interrupt() && softirq_pending(smp_processor_id()))) \
-               do_softirq();                                           \
-       preempt_check_resched();                                        \
-} while (0)
-
-#endif /* __ASM_SOFTIRQ_H */

diff --git a/include/asm-i386/atomic_kmap.h b/include/asm-i386/atomic_kmap.h
deleted file mode 100644 (file)
index 150ffb9..0000000
--- a/include/asm-i386/atomic_kmap.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * atomic_kmap.h: temporary virtual kernel memory mappings
- *
- * Copyright (C) 2003 Ingo Molnar <mingo@redhat.com>
- */
-
-#ifndef _ASM_ATOMIC_KMAP_H
-#define _ASM_ATOMIC_KMAP_H
-
-#ifdef __KERNEL__
-
-#include <linux/config.h>
-#include <asm/tlbflush.h>
-
-#ifdef CONFIG_DEBUG_HIGHMEM
-#define HIGHMEM_DEBUG 1
-#else
-#define HIGHMEM_DEBUG 0
-#endif
-
-extern pte_t *kmap_pte;
-#define kmap_prot PAGE_KERNEL
-
-#define PKMAP_BASE (0xff000000UL)
-#define NR_SHARED_PMDS ((0xffffffff-PKMAP_BASE+1)/PMD_SIZE)
-
-static inline unsigned long __kmap_atomic_vaddr(enum km_type type)
-{
-       enum fixed_addresses idx;
-
-       idx = type + KM_TYPE_NR*smp_processor_id();
-       return __fix_to_virt(FIX_KMAP_BEGIN + idx);
-}
-
-static inline void *__kmap_atomic_noflush(struct page *page, enum km_type type)
-{
-       enum fixed_addresses idx;
-       unsigned long vaddr;
-
-       idx = type + KM_TYPE_NR*smp_processor_id();
-       vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
-       /*
-        * NOTE: entries that rely on some secondary TLB-flush
-        * effect must not be global:
-        */
-       set_pte(kmap_pte-idx, mk_pte(page, PAGE_KERNEL));
-
-       return (void*) vaddr;
-}
-
-static inline void *__kmap_atomic(struct page *page, enum km_type type)
-{
-       enum fixed_addresses idx;
-       unsigned long vaddr;
-
-       idx = type + KM_TYPE_NR*smp_processor_id();
-       vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
-#if HIGHMEM_DEBUG
-       BUG_ON(!pte_none(*(kmap_pte-idx)));
-#else
-       /*
-        * Performance optimization - do not flush if the new
-        * pte is the same as the old one:
-        */
-       if (pte_val(*(kmap_pte-idx)) == pte_val(mk_pte(page, kmap_prot)))
-               return (void *) vaddr;
-#endif
-       set_pte(kmap_pte-idx, mk_pte(page, kmap_prot));
-       __flush_tlb_one(vaddr);
-
-       return (void*) vaddr;
-}
-
-static inline void __kunmap_atomic(void *kvaddr, enum km_type type)
-{
-#if HIGHMEM_DEBUG
-       unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
-       enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id();
-
-       BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN+idx));
-       /*
-        * force other mappings to Oops if they'll try to access
-        * this pte without first remap it
-        */
-       pte_clear(kmap_pte-idx);
-       __flush_tlb_one(vaddr);
-#endif
-}
-
-#define __kunmap_atomic_type(type) \
-               __kunmap_atomic((void *)__kmap_atomic_vaddr(type), (type))
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_ATOMIC_KMAP_H */