This commit was generated by cvs2svn to compensate for changes in r665,
authorMarc Fiuczynski <mef@cs.princeton.edu>
Mon, 8 Aug 2005 21:12:01 +0000 (21:12 +0000)
committerMarc Fiuczynski <mef@cs.princeton.edu>
Mon, 8 Aug 2005 21:12:01 +0000 (21:12 +0000)
which included commits to RCS files with non-trunk default branches.

22 files changed:
arch/arm/mach-ixp4xx/coyote-setup.c
arch/arm/mach-ixp4xx/ixdp425-setup.c
arch/arm/mach-versatile/clock.c
arch/arm/mach-versatile/clock.h
arch/mips/pci/fixup-jaguar.c
arch/mips/pci/fixup-ocelot-c.c
arch/mips/pci/fixup-ocelot-g.c
arch/mips/pci/fixup-tb0219.c
arch/mips/pmc-sierra/yosemite/dbg_io.c
arch/mips/pmc-sierra/yosemite/py-console.c
arch/s390/mm/mmap.c
arch/sh/cchips/voyagergx/consistent.c
drivers/mtd/chips/cfi_util.c
drivers/s390/net/ctcdbug.h
drivers/w1/w1_int.h
fs/ntfs/collate.c
include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
include/asm-ia64/sn/shub_mmr.h
include/asm-ppc/immap_cpm2.h
include/asm-sh/adc.h
include/linux/crc-ccitt.h
mm/prio_tree.c

index 03ad0b7..a4b5443 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-ixp4xx/coyote-setup.c
  *
- * ADI Engineering Coyote board-setup 
+ * Board setup for ADI Engineering and IXDGP425 boards
  *
  * Copyright (C) 2003-2004 MontaVista Software, Inc.
  *
@@ -30,7 +30,7 @@
 #endif
 
 /*
- * Only one serial port is connected on the Coyote.
+ * Only one serial port is connected on the Coyote & IXDPG425
  */
 static struct uart_port coyote_serial_port = {
        .membase        = (char*)(IXP4XX_UART2_BASE_VIRT + REG_OFFSET),
@@ -47,6 +47,13 @@ static struct uart_port coyote_serial_port = {
 
 void __init coyote_map_io(void)
 {
+       if (machine_is_ixdpg425()) {
+               coyote_serial_port.membase =
+                       (char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET);
+               coyote_serial_port.mapbase = IXP4XX_UART1_BASE_PHYS;
+               coyote_serial_port.irq = IRQ_IXP4XX_UART1;
+       }
+
        early_serial_setup(&coyote_serial_port);
 
        ixp4xx_map_io();
@@ -79,17 +86,39 @@ static struct platform_device *coyote_devices[] __initdata = {
 
 static void __init coyote_init(void)
 {
+       *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
+       *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
+
        platform_add_devices(&coyote_devices, ARRAY_SIZE(coyote_devices));
 }
 
-MACHINE_START(ADI_COYOTE, "ADI Engineering IXP4XX Coyote Development Platform")
+#ifdef CONFIG_ARCH_ADI_COYOTE
+MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
         MAINTAINER("MontaVista Software, Inc.")
         BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
                 IXP4XX_PERIPHERAL_BASE_VIRT)
         MAPIO(coyote_map_io)
         INITIRQ(ixp4xx_init_irq)
-       INITTIME(ixp4xx_init_time)
+       .timer          = &ixp4xx_timer,
         BOOT_PARAMS(0x0100)
        INIT_MACHINE(coyote_init)
 MACHINE_END
+#endif
+
+/*
+ * IXDPG425 is identical to Coyote except for which serial port
+ * is connected.
+ */
+#ifdef CONFIG_MACH_IXDPG425
+MACHINE_START(IXDPG425, "Intel IXDPG425")
+        MAINTAINER("MontaVista Software, Inc.")
+        BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
+                IXP4XX_PERIPHERAL_BASE_VIRT)
+        MAPIO(coyote_map_io)
+        INITIRQ(ixp4xx_init_irq)
+       .timer          = &ixp4xx_timer,
+        BOOT_PARAMS(0x0100)
+       INIT_MACHINE(coyote_init)
+MACHINE_END
+#endif
 
index dbcaa46..9c299f9 100644 (file)
@@ -117,7 +117,7 @@ MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
                IXP4XX_PERIPHERAL_BASE_VIRT)
        MAPIO(ixdp425_map_io)
        INITIRQ(ixp4xx_init_irq)
-       INITTIME(ixp4xx_init_time)
+       .timer          = &ixp4xx_timer,
        BOOT_PARAMS(0x0100)
        INIT_MACHINE(ixdp425_init)
 MACHINE_END
@@ -128,7 +128,7 @@ MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
                IXP4XX_PERIPHERAL_BASE_VIRT)
        MAPIO(ixdp425_map_io)
        INITIRQ(ixp4xx_init_irq)
-       INITTIME(ixp4xx_init_time)
+       .timer          = &ixp4xx_timer,
        BOOT_PARAMS(0x0100)
        INIT_MACHINE(ixdp425_init)
 MACHINE_END
@@ -146,7 +146,7 @@ MACHINE_START(AVILA, "Gateworks Avila Network Platform")
                IXP4XX_PERIPHERAL_BASE_VIRT)
        MAPIO(ixdp425_map_io)
        INITIRQ(ixp4xx_init_irq)
-       INITTIME(ixp4xx_init_time)
+       .timer          = &ixp4xx_timer,
        BOOT_PARAMS(0x0100)
        INIT_MACHINE(ixdp425_init)
 MACHINE_END
index 24f12bd..48025c2 100644 (file)
@@ -16,7 +16,7 @@
 
 #include <asm/semaphore.h>
 #include <asm/hardware/clock.h>
-#include <asm/hardware/icst525.h>
+#include <asm/hardware/icst307.h>
 
 #include "clock.h"
 
@@ -83,12 +83,12 @@ EXPORT_SYMBOL(clk_round_rate);
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
        int ret = -EIO;
-#if 0 // Not yet
+
        if (clk->setvco) {
-               struct icst525_vco vco;
+               struct icst307_vco vco;
 
-               vco = icst525_khz_to_vco(clk->params, rate / 1000);
-               clk->rate = icst525_khz(clk->params, vco) * 1000;
+               vco = icst307_khz_to_vco(clk->params, rate / 1000);
+               clk->rate = icst307_khz(clk->params, vco) * 1000;
 
                printk("Clock %s: setting VCO reg params: S=%d R=%d V=%d\n",
                        clk->name, vco.s, vco.r, vco.v);
@@ -96,7 +96,6 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
                clk->setvco(clk, vco);
                ret = 0;
        }
-#endif
        return ret;
 }
 EXPORT_SYMBOL(clk_set_rate);
index 12e68ec..8b0b61d 100644 (file)
@@ -9,16 +9,16 @@
  * published by the Free Software Foundation.
  */
 struct module;
-struct icst525_params;
+struct icst307_params;
 
 struct clk {
        struct list_head        node;
        unsigned long           rate;
        struct module           *owner;
        const char              *name;
-       const struct icst525_params *params;
+       const struct icst307_params *params;
        void                    *data;
-       void                    (*setvco)(struct clk *, struct icst525_vco vco);
+       void                    (*setvco)(struct clk *, struct icst307_vco vco);
 };
 
 int clk_register(struct clk *clk);
index 29b6a46..6c5e1d4 100644 (file)
@@ -8,14 +8,13 @@
  * Marvell wants an NDA for their docs so this was written without
  * documentation.  You've been warned.
  *
- * Copyright (C) 2004 Ralf Baechle
+ * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/pci.h>
 
 #include <asm/mipsregs.h>
-#include <asm/pci_channel.h>
 
 /*
  * WARNING: Example of how _NOT_ to do it.
@@ -36,3 +35,9 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 return 0;
        panic("Whooops in pcibios_map_irq");
 }
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+       return 0;
+}
index 9edc059..d454948 100644 (file)
@@ -33,3 +33,9 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 return 0;
        panic("Whooops in pcibios_map_irq");
 }
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+       return 0;
+}
index a79fc4a..d7a652e 100644 (file)
@@ -29,3 +29,9 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 
        return -1;
 }
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+       return 0;
+}
index 4d62bce..850a900 100644 (file)
@@ -58,3 +58,9 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 
        return irq;
 }
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+       return 0;
+}
index 1ff8d95..abaff96 100644 (file)
@@ -33,7 +33,7 @@
 
 #include <linux/config.h>
 
-#if defined(CONFIG_KGDB)
+#ifdef CONFIG_KGDB
 #include <asm/serial.h>
 
 /*
index 22c336f..abc0435 100644 (file)
@@ -48,8 +48,6 @@ struct yo_uartregs {
 #define iu_iir u3.iir
 #define iu_fcr u3.fcr
 
-extern unsigned long uart_base;
-
 #define IO_BASE_64     0x9000000000000000ULL
 
 static unsigned char readb_outer_space(unsigned long phys)
@@ -110,11 +108,6 @@ static void writeb_outer_space(unsigned long phys, unsigned char c)
        __asm__("sll    $0, $0, 2\n");
 }
 
-static inline struct yo_uartregs *console_uart(void)
-{
-       return (struct yo_uartregs *) (uart_base + 8);
-}
-
 void prom_putchar(char c)
 {
        unsigned long lsr = 0xfd000008UL + offsetof(struct yo_uartregs, iu_lsr);
index 1039196..ebe73af 100644 (file)
@@ -37,7 +37,7 @@
 
 static inline unsigned long mmap_base(void)
 {
-       unsigned long gap = current->rlim[RLIMIT_STACK].rlim_cur;
+       unsigned long gap = current->signal->rlim[RLIMIT_STACK].rlim_cur;
 
        if (gap < MIN_GAP)
                gap = MIN_GAP;
@@ -58,7 +58,7 @@ static inline int mmap_is_legacy(void)
 #endif
        return sysctl_legacy_va_layout ||
            (current->personality & ADDR_COMPAT_LAYOUT) ||
-           current->rlim[RLIMIT_STACK].rlim_cur == RLIM_INFINITY;
+           current->signal->rlim[RLIMIT_STACK].rlim_cur == RLIM_INFINITY;
 }
 
 /*
index 95a309d..921d12b 100644 (file)
@@ -49,13 +49,13 @@ void *voyagergx_consistent_alloc(struct device *dev, size_t size,
        if (!dev || dev->bus != &sh_bus_types[SH_BUS_VIRT] ||
                   (dev->bus == &sh_bus_types[SH_BUS_VIRT] &&
                    shdev->dev_id != SH_DEV_ID_USB_OHCI))
-               return consistent_alloc(flag, size, handle);
+               return NULL;
 
        start = OHCI_SRAM_START + OHCI_HCCA_SIZE;
 
        entry = kmalloc(sizeof(struct voya_alloc_entry), GFP_ATOMIC);
        if (!entry)
-               return NULL;
+               return ERR_PTR(-ENOMEM);
 
        entry->len = (size + 15) & ~15;
 
@@ -91,11 +91,11 @@ out:
        kfree(entry);
        spin_unlock_irqrestore(&voya_list_lock, flags);
 
-       return NULL;
+       return ERR_PTR(-EINVAL);
 }
 
-void voyagergx_consistent_free(struct device *dev, size_t size,
-                              void *vaddr, dma_addr_t handle)
+int voyagergx_consistent_free(struct device *dev, size_t size,
+                             void *vaddr, dma_addr_t handle)
 {
        struct voya_alloc_entry *entry;
        struct sh_dev *shdev = to_sh_dev(dev);
@@ -103,10 +103,8 @@ void voyagergx_consistent_free(struct device *dev, size_t size,
 
        if (!dev || dev->bus != &sh_bus_types[SH_BUS_VIRT] ||
                   (dev->bus == &sh_bus_types[SH_BUS_VIRT] &&
-                   shdev->dev_id != SH_DEV_ID_USB_OHCI)) {
-               consistent_free(vaddr, size);
-               return;
-       }
+                   shdev->dev_id != SH_DEV_ID_USB_OHCI))
+               return -EINVAL;
 
        spin_lock_irqsave(&voya_list_lock, flags);
        list_for_each_entry(entry, &voya_alloc_list, list) {
@@ -119,6 +117,8 @@ void voyagergx_consistent_free(struct device *dev, size_t size,
                break;
        }
        spin_unlock_irqrestore(&voya_list_lock, flags);
+
+       return 0;
 }
 
 EXPORT_SYMBOL(voyagergx_consistent_alloc);
index d1a7856..49c97bc 100644 (file)
@@ -7,7 +7,7 @@
  *
  * This code is covered by the GPL.
  *
- * $Id: cfi_util.c,v 1.4 2004/07/14 08:38:44 dwmw2 Exp $
+ * $Id: cfi_util.c,v 1.5 2004/08/12 06:40:23 eric Exp $
  *
  */
 
@@ -22,6 +22,7 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
+#include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/cfi.h>
 #include <linux/mtd/compatmac.h>
@@ -74,19 +75,114 @@ out:
 
 EXPORT_SYMBOL(cfi_read_pri);
 
-void cfi_fixup(struct map_info *map, struct cfi_fixup* fixups)
+void cfi_fixup(struct mtd_info *mtd, struct cfi_fixup *fixups)
 {
+       struct map_info *map = mtd->priv;
        struct cfi_private *cfi = map->fldrv_priv;
        struct cfi_fixup *f;
 
        for (f=fixups; f->fixup; f++) {
                if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi->mfr)) &&
                    ((f->id  == CFI_ID_ANY)  || (f->id  == cfi->id))) {
-                       f->fixup(map, f->param);
+                       f->fixup(mtd, f->param);
                }
        }
 }
 
 EXPORT_SYMBOL(cfi_fixup);
 
+int cfi_varsize_frob(struct mtd_info *mtd, varsize_frob_t frob,
+                                    loff_t ofs, size_t len, void *thunk)
+{
+       struct map_info *map = mtd->priv;
+       struct cfi_private *cfi = map->fldrv_priv;
+       unsigned long adr;
+       int chipnum, ret = 0;
+       int i, first;
+       struct mtd_erase_region_info *regions = mtd->eraseregions;
+
+       if (ofs > mtd->size)
+               return -EINVAL;
+
+       if ((len + ofs) > mtd->size)
+               return -EINVAL;
+
+       /* Check that both start and end of the requested erase are
+        * aligned with the erasesize at the appropriate addresses.
+        */
+
+       i = 0;
+
+       /* Skip all erase regions which are ended before the start of 
+          the requested erase. Actually, to save on the calculations,
+          we skip to the first erase region which starts after the
+          start of the requested erase, and then go back one.
+       */
+       
+       while (i < mtd->numeraseregions && ofs >= regions[i].offset)
+              i++;
+       i--;
+
+       /* OK, now i is pointing at the erase region in which this 
+          erase request starts. Check the start of the requested
+          erase range is aligned with the erase size which is in
+          effect here.
+       */
+
+       if (ofs & (regions[i].erasesize-1))
+               return -EINVAL;
+
+       /* Remember the erase region we start on */
+       first = i;
+
+       /* Next, check that the end of the requested erase is aligned
+        * with the erase region at that address.
+        */
+
+       while (i<mtd->numeraseregions && (ofs + len) >= regions[i].offset)
+               i++;
+
+       /* As before, drop back one to point at the region in which
+          the address actually falls
+       */
+       i--;
+       
+       if ((ofs + len) & (regions[i].erasesize-1))
+               return -EINVAL;
+
+       chipnum = ofs >> cfi->chipshift;
+       adr = ofs - (chipnum << cfi->chipshift);
+
+       i=first;
+
+       while(len) {
+               unsigned long chipmask;
+               int size = regions[i].erasesize;
+
+               ret = (*frob)(map, &cfi->chips[chipnum], adr, size, thunk);
+               
+               if (ret)
+                       return ret;
+
+               adr += size;
+               len -= size;
+
+               chipmask = (1 << cfi->chipshift) - 1;
+               if ((adr & chipmask) == ((regions[i].offset + size * regions[i].numblocks) & chipmask))
+                       i++;
+
+               if (adr >> cfi->chipshift) {
+                       adr = 0;
+                       chipnum++;
+                       
+                       if (chipnum >= cfi->numchips)
+                       break;
+               }
+       }
+
+       return 0;
+}
+
+EXPORT_SYMBOL(cfi_varsize_frob);
+
 MODULE_LICENSE("GPL");
index 5c0fcfc..ef88839 100644 (file)
@@ -1,6 +1,6 @@
 /*
  *
- * linux/drivers/s390/net/ctcdbug.h ($Revision: 1.3 $)
+ * linux/drivers/s390/net/ctcdbug.h ($Revision: 1.4 $)
  *
  * CTC / ESCON network driver - s390 dbf exploit.
  *
@@ -9,7 +9,7 @@
  *    Author(s): Original Code written by
  *                       Peter Tiedemann (ptiedem@de.ibm.com)
  *
- *    $Revision: 1.3 $  $Date: 2004/07/28 12:27:54 $
+ *    $Revision: 1.4 $  $Date: 2004/10/15 09:26:58 $
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -59,7 +59,7 @@
                debug_event(ctc_dbf_##name,level,(void*)(addr),len); \
        } while (0)
 
-extern DEFINE_PER_CPU(char[256], ctc_dbf_txt_buf);
+DECLARE_PER_CPU(char[256], ctc_dbf_txt_buf);
 extern debug_info_t *ctc_dbf_setup;
 extern debug_info_t *ctc_dbf_data;
 extern debug_info_t *ctc_dbf_trace;
index a5aeb76..fdb531e 100644 (file)
@@ -27,7 +27,7 @@
 
 #include "w1.h"
 
-struct w1_master * w1_alloc_dev(int, struct device_driver *, struct device *);
+struct w1_master * w1_alloc_dev(u32, int, int, struct device_driver *, struct device *);
 void w1_free_dev(struct w1_master *dev);
 int w1_add_master_device(struct w1_bus_master *);
 void w1_remove_master_device(struct w1_bus_master *);
index 31dd894..4a28ab3 100644 (file)
@@ -19,8 +19,9 @@
  * Foundation,Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#include "ntfs.h"
 #include "collate.h"
+#include "debug.h"
+#include "ntfs.h"
 
 static int ntfs_collate_binary(ntfs_volume *vol,
                const void *data1, const int data1_len,
index b5810b2..0f352ac 100644 (file)
@@ -55,7 +55,7 @@
  * PCI Config registers
  */
 #define IXP4XX_PCI_CFG_BASE_PHYS       (0xC0000000)
-#define        IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFD000)
+#define        IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFE000)
 #define IXP4XX_PCI_CFG_REGION_SIZE     (0x00001000)
 
 /*
index 430c50f..ddb265c 100644 (file)
 #define SH_PTC_1_START_SHFT                      63
 #define SH_PTC_1_START_MASK                      0x8000000000000000
 
+/*
+ * Register definitions
+ */
+
+/* ==================================================================== */
+/*                    Register "SH_RTC1_INT_CONFIG"                     */
+/*                SHub RTC 1 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC1_INT_CONFIG                       0x0000000110001480
+#define SH_RTC1_INT_CONFIG_MASK                  0x0ff3ffffffefffff
+#define SH_RTC1_INT_CONFIG_INIT                  0x0000000000000000
+
+/*   SH_RTC1_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC1_INT_CONFIG_TYPE_SHFT             0
+#define SH_RTC1_INT_CONFIG_TYPE_MASK             0x0000000000000007
+
+/*   SH_RTC1_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC1_INT_CONFIG_AGT_SHFT              3
+#define SH_RTC1_INT_CONFIG_AGT_MASK              0x0000000000000008
+
+/*   SH_RTC1_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC1_INT_CONFIG_PID_SHFT              4
+#define SH_RTC1_INT_CONFIG_PID_MASK              0x00000000000ffff0
+
+/*   SH_RTC1_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC1_INT_CONFIG_BASE_SHFT             21
+#define SH_RTC1_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+
+/*   SH_RTC1_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC1_INT_CONFIG_IDX_SHFT              52
+#define SH_RTC1_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC1_INT_ENABLE"                     */
+/*                SHub RTC 1 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC1_INT_ENABLE                       0x0000000110001500
+#define SH_RTC1_INT_ENABLE_MASK                  0x0000000000000001
+#define SH_RTC1_INT_ENABLE_INIT                  0x0000000000000000
+
+/*   SH_RTC1_INT_ENABLE_RTC1_ENABLE                                     */
+/*   Description:  Enable RTC 1 Interrupt                               */
+#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT      0
+#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                    Register "SH_RTC2_INT_CONFIG"                     */
+/*                SHub RTC 2 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC2_INT_CONFIG                       0x0000000110001580
+#define SH_RTC2_INT_CONFIG_MASK                  0x0ff3ffffffefffff
+#define SH_RTC2_INT_CONFIG_INIT                  0x0000000000000000
+
+/*   SH_RTC2_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC2_INT_CONFIG_TYPE_SHFT             0
+#define SH_RTC2_INT_CONFIG_TYPE_MASK             0x0000000000000007
+
+/*   SH_RTC2_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC2_INT_CONFIG_AGT_SHFT              3
+#define SH_RTC2_INT_CONFIG_AGT_MASK              0x0000000000000008
+
+/*   SH_RTC2_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC2_INT_CONFIG_PID_SHFT              4
+#define SH_RTC2_INT_CONFIG_PID_MASK              0x00000000000ffff0
+
+/*   SH_RTC2_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC2_INT_CONFIG_BASE_SHFT             21
+#define SH_RTC2_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+
+/*   SH_RTC2_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC2_INT_CONFIG_IDX_SHFT              52
+#define SH_RTC2_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC2_INT_ENABLE"                     */
+/*                SHub RTC 2 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC2_INT_ENABLE                       0x0000000110001600
+#define SH_RTC2_INT_ENABLE_MASK                  0x0000000000000001
+#define SH_RTC2_INT_ENABLE_INIT                  0x0000000000000000
+
+/*   SH_RTC2_INT_ENABLE_RTC2_ENABLE                                     */
+/*   Description:  Enable RTC 2 Interrupt                               */
+#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT      0
+#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                    Register "SH_RTC3_INT_CONFIG"                     */
+/*                SHub RTC 3 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC3_INT_CONFIG                       0x0000000110001680
+#define SH_RTC3_INT_CONFIG_MASK                  0x0ff3ffffffefffff
+#define SH_RTC3_INT_CONFIG_INIT                  0x0000000000000000
+
+/*   SH_RTC3_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC3_INT_CONFIG_TYPE_SHFT             0
+#define SH_RTC3_INT_CONFIG_TYPE_MASK             0x0000000000000007
+
+/*   SH_RTC3_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC3_INT_CONFIG_AGT_SHFT              3
+#define SH_RTC3_INT_CONFIG_AGT_MASK              0x0000000000000008
+
+/*   SH_RTC3_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC3_INT_CONFIG_PID_SHFT              4
+#define SH_RTC3_INT_CONFIG_PID_MASK              0x00000000000ffff0
+
+/*   SH_RTC3_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC3_INT_CONFIG_BASE_SHFT             21
+#define SH_RTC3_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+
+/*   SH_RTC3_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC3_INT_CONFIG_IDX_SHFT              52
+#define SH_RTC3_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC3_INT_ENABLE"                     */
+/*                SHub RTC 3 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC3_INT_ENABLE                       0x0000000110001700
+#define SH_RTC3_INT_ENABLE_MASK                  0x0000000000000001
+#define SH_RTC3_INT_ENABLE_INIT                  0x0000000000000000
+
+/*   SH_RTC3_INT_ENABLE_RTC3_ENABLE                                     */
+/*   Description:  Enable RTC 3 Interrupt                               */
+#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT      0
+#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK      0x0000000000000001
+
+/*   SH_EVENT_OCCURRED_RTC1_INT                                         */
+/*   Description:  Pending RTC 1 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC1_INT_SHFT          24
+#define SH_EVENT_OCCURRED_RTC1_INT_MASK          0x0000000001000000
+
+/*   SH_EVENT_OCCURRED_RTC2_INT                                         */
+/*   Description:  Pending RTC 2 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC2_INT_SHFT          25
+#define SH_EVENT_OCCURRED_RTC2_INT_MASK          0x0000000002000000
+
+/*   SH_EVENT_OCCURRED_RTC3_INT                                         */
+/*   Description:  Pending RTC 3 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC3_INT_SHFT          26
+#define SH_EVENT_OCCURRED_RTC3_INT_MASK          0x0000000004000000
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPB"                        */
+/*                  RTC Compare Value for Processor B                   */
+/* ==================================================================== */
+
+#define SH_INT_CMPB                              0x00000001101b0080
+#define SH_INT_CMPB_MASK                         0x007fffffffffffff
+#define SH_INT_CMPB_INIT                         0x0000000000000000
+
+/*   SH_INT_CMPB_REAL_TIME_CMPB                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT          0
+#define SH_INT_CMPB_REAL_TIME_CMPB_MASK          0x007fffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPC"                        */
+/*                  RTC Compare Value for Processor C                   */
+/* ==================================================================== */
+
+#define SH_INT_CMPC                              0x00000001101b0100
+#define SH_INT_CMPC_MASK                         0x007fffffffffffff
+#define SH_INT_CMPC_INIT                         0x0000000000000000
+
+/*   SH_INT_CMPC_REAL_TIME_CMPC                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT          0
+#define SH_INT_CMPC_REAL_TIME_CMPC_MASK          0x007fffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPD"                        */
+/*                  RTC Compare Value for Processor D                   */
+/* ==================================================================== */
+
+#define SH_INT_CMPD                              0x00000001101b0180
+#define SH_INT_CMPD_MASK                         0x007fffffffffffff
+#define SH_INT_CMPD_INIT                         0x0000000000000000
+
+/*   SH_INT_CMPD_REAL_TIME_CMPD                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT          0
+#define SH_INT_CMPD_REAL_TIME_CMPD_MASK          0x007fffffffffffff
+
 #endif /* _ASM_IA64_SN_SHUB_MMR_H */
index 4d56515..3c23d9c 100644 (file)
@@ -133,7 +133,7 @@ typedef struct      sys_int_timers {
        u8      res5[2];
        u32     sit_pitc;
        u32     sit_pitr;
-       u8      res6[92];
+       u8      res6[94];
        u8      res7[390];
 } sit_cpm2_t;
 
index 64747dc..5f85cf7 100644 (file)
@@ -1,6 +1,6 @@
 #ifndef __ASM_ADC_H
 #define __ASM_ADC_H
-
+#ifdef __KERNEL__
 /*
  * Copyright (C) 2004  Andriy Skulysh
  */
@@ -9,4 +9,5 @@
 
 int adc_single(unsigned int channel);
 
+#endif /* __KERNEL__ */
 #endif /* __ASM_ADC_H */
index f52696a..9003761 100644 (file)
@@ -1,5 +1,6 @@
 #ifndef _LINUX_CRC_CCITT_H
 #define _LINUX_CRC_CCITT_H
+#ifdef __KERNEL__
 
 #include <linux/types.h>
 
@@ -12,4 +13,5 @@ static inline u16 crc_ccitt_byte(u16 crc, const u8 c)
        return (crc >> 8) ^ crc_ccitt_table[(crc ^ c) & 0xff];
 }
 
+#endif /* __KERNEL__ */
 #endif /* _LINUX_CRC_CCITT_H */
index 2a1d02f..3bd8d5a 100644 (file)
@@ -245,7 +245,7 @@ static struct prio_tree_node *prio_tree_insert(struct prio_tree_root *root,
                mask >>= 1;
 
                if (!mask) {
-                       mask = 1UL << (root->index_bits - 1);
+                       mask = 1UL << (BITS_PER_LONG - 1);
                        size_flag = 1;
                }
        }
@@ -334,7 +334,7 @@ static struct prio_tree_node *prio_tree_left(struct prio_tree_iter *iter,
                                iter->mask = ULONG_MAX;
                        } else {
                                iter->size_level = 1;
-                               iter->mask = 1UL << (iter->root->index_bits - 1);
+                               iter->mask = 1UL << (BITS_PER_LONG - 1);
                        }
                }
                return iter->cur;
@@ -376,7 +376,7 @@ static struct prio_tree_node *prio_tree_right(struct prio_tree_iter *iter,
                                iter->mask = ULONG_MAX;
                        } else {
                                iter->size_level = 1;
-                               iter->mask = 1UL << (iter->root->index_bits - 1);
+                               iter->mask = 1UL << (BITS_PER_LONG - 1);
                        }
                }
                return iter->cur;