From 8bcf446b40b9e42b463f500ebbe9aca3188238c5 Mon Sep 17 00:00:00 2001 From: Marc Fiuczynski Date: Mon, 8 Aug 2005 21:12:48 +0000 Subject: [PATCH] This commit was generated by cvs2svn to compensate for changes in r713, which included commits to RCS files with non-trunk default branches. --- arch/arm/mach-ixp4xx/coyote-setup.c | 4 +- arch/arm/mach-ixp4xx/ixdp425-setup.c | 23 +- arch/ia64/sn/kernel/bte_error.c | 14 +- arch/mips/pmc-sierra/yosemite/dbg_io.c | 4 - arch/mips/pmc-sierra/yosemite/py-console.c | 41 +- arch/ppc/platforms/85xx/Makefile | 6 +- arch/s390/mm/mmap.c | 3 + arch/sh/cchips/voyagergx/consistent.c | 2 +- arch/sh64/kernel/fpu.c | 4 +- drivers/char/lcd.h | 2 + drivers/mtd/chips/cfi_util.c | 40 +- drivers/pcmcia/pd6729.h | 6 +- drivers/pcmcia/soc_common.h | 2 +- fs/xfs/linux-2.6/xfs_stats.h | 12 +- include/asm-arm/arch-ixp4xx/hardware.h | 7 + include/asm-arm/arch-ixp4xx/irqs.h | 20 +- include/asm-arm/arch-ixp4xx/ixp4xx-regs.h | 44 +- include/asm-ia64/cpu.h | 5 + include/asm-ia64/sn/shub_mmr.h | 221 ++++++---- include/asm-mips/pmon.h | 39 +- include/asm-sh64/thread_info.h | 1 + include/linux/prio_tree.h | 48 ++- mm/prio_tree.c | 471 +-------------------- net/bluetooth/hidp/hidp.h | 45 ++ 24 files changed, 434 insertions(+), 630 deletions(-) diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c index a4b54430f..1d06d364c 100644 --- a/arch/arm/mach-ixp4xx/coyote-setup.c +++ b/arch/arm/mach-ixp4xx/coyote-setup.c @@ -8,6 +8,7 @@ * Author: Deepak Saxena */ +#include #include #include #include @@ -89,7 +90,8 @@ static void __init coyote_init(void) *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; - platform_add_devices(&coyote_devices, ARRAY_SIZE(coyote_devices)); + ixp4xx_sys_init(); + platform_add_devices(coyote_devices, ARRAY_SIZE(coyote_devices)); } #ifdef CONFIG_ARCH_ADI_COYOTE diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c index 9c299f92a..77006d96a 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c @@ -8,6 +8,7 @@ * Author: Deepak Saxena */ +#include #include #include #include @@ -108,7 +109,16 @@ static struct platform_device *ixdp425_devices[] __initdata = { static void __init ixdp425_init(void) { - platform_add_devices(&ixdp425_devices, ARRAY_SIZE(ixdp425_devices)); + ixp4xx_sys_init(); + + /* + * IXP465 has 32MB window + */ + if (machine_is_ixdp465()) { + ixdp425_flash_resource.end += IXDP425_FLASH_SIZE; + } + + platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices)); } MACHINE_START(IXDP425, "Intel IXDP425 Development Platform") @@ -122,6 +132,17 @@ MACHINE_START(IXDP425, "Intel IXDP425 Development Platform") INIT_MACHINE(ixdp425_init) MACHINE_END +MACHINE_START(IXDP465, "Intel IXDP465 Development Platform") + MAINTAINER("MontaVista Software, Inc.") + BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS, + IXP4XX_PERIPHERAL_BASE_VIRT) + MAPIO(ixdp425_map_io) + INITIRQ(ixp4xx_init_irq) + .timer = &ixp4xx_timer, + BOOT_PARAMS(0x0100) + INIT_MACHINE(ixdp425_init) +MACHINE_END + MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform") MAINTAINER("MontaVista Software, Inc.") BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS, diff --git a/arch/ia64/sn/kernel/bte_error.c b/arch/ia64/sn/kernel/bte_error.c index 3591c2cf1..fd104312c 100644 --- a/arch/ia64/sn/kernel/bte_error.c +++ b/arch/ia64/sn/kernel/bte_error.c @@ -10,11 +10,12 @@ #include #include "ioerror.h" #include -#include "shubio.h" +#include #include #include "xtalk/xwidgetdev.h" #include "xtalk/hubdev.h" #include +#include /* * Bte error handling is done in two parts. The first captures @@ -47,6 +48,7 @@ void bte_error_handler(unsigned long _nodepda) ii_icrb0_d_u_t icrbd; /* II CRB Register D */ ii_ibcr_u_t ibcr; ii_icmr_u_t icmr; + ii_ieclr_u_t ieclr; BTE_PRINTK(("bte_error_handler(%p) - %d\n", err_nodepda, smp_processor_id())); @@ -131,6 +133,14 @@ void bte_error_handler(unsigned long _nodepda) imem.ii_imem_fld_s.i_b0_esd = imem.ii_imem_fld_s.i_b1_esd = 1; REMOTE_HUB_S(nasid, IIO_IMEM, imem.ii_imem_regval); + /* Clear BTE0/1 error bits */ + ieclr.ii_ieclr_regval = 0; + if (err_nodepda->bte_if[0].bh_error != BTE_SUCCESS) + ieclr.ii_ieclr_fld_s.i_e_bte_0 = 1; + if (err_nodepda->bte_if[1].bh_error != BTE_SUCCESS) + ieclr.ii_ieclr_fld_s.i_e_bte_1 = 1; + REMOTE_HUB_S(nasid, IIO_IECLR, ieclr.ii_ieclr_regval); + /* Reinitialize both BTE state machines. */ ibcr.ii_ibcr_regval = REMOTE_HUB_L(nasid, IIO_IBCR); ibcr.ii_ibcr_fld_s.i_soft_reset = 1; @@ -152,7 +162,7 @@ void bte_error_handler(unsigned long _nodepda) err_nodepda->bte_if[i].cleanup_active = 0; BTE_PRINTK(("eh:%p:%d Unlocked %d\n", err_nodepda, smp_processor_id(), i)); - spin_unlock(&pda->cpu_bte_if[i]->spinlock); + spin_unlock(&err_nodepda->bte_if[i].spinlock); } del_timer(recovery_timer); diff --git a/arch/mips/pmc-sierra/yosemite/dbg_io.c b/arch/mips/pmc-sierra/yosemite/dbg_io.c index abaff965b..0f659c910 100644 --- a/arch/mips/pmc-sierra/yosemite/dbg_io.c +++ b/arch/mips/pmc-sierra/yosemite/dbg_io.c @@ -31,9 +31,6 @@ * the interrupt came from channel A or B. */ -#include - -#ifdef CONFIG_KGDB #include /* @@ -181,4 +178,3 @@ int putDebugChar(unsigned char byte) return 1; } -#endif diff --git a/arch/mips/pmc-sierra/yosemite/py-console.c b/arch/mips/pmc-sierra/yosemite/py-console.c index abc04358d..757e60569 100644 --- a/arch/mips/pmc-sierra/yosemite/py-console.c +++ b/arch/mips/pmc-sierra/yosemite/py-console.c @@ -48,9 +48,12 @@ struct yo_uartregs { #define iu_iir u3.iir #define iu_fcr u3.fcr +#define ssnop() __asm__ __volatile__("sll $0, $0, 1\n"); +#define ssnop_4() do { ssnop(); ssnop(); ssnop(); ssnop(); } while (0) + #define IO_BASE_64 0x9000000000000000ULL -static unsigned char readb_outer_space(unsigned long phys) +static unsigned char readb_outer_space(unsigned long long phys) { unsigned long long vaddr = IO_BASE_64 | phys; unsigned char res; @@ -58,29 +61,23 @@ static unsigned char readb_outer_space(unsigned long phys) sr = read_c0_status(); write_c0_status((sr | ST0_KX) & ~ ST0_IE); - __asm__("sll $0, $0, 2\n"); - __asm__("sll $0, $0, 2\n"); - __asm__("sll $0, $0, 2\n"); - __asm__("sll $0, $0, 2\n"); + ssnop_4(); __asm__ __volatile__ ( " .set mips3 \n" - " ld %0, (%0) \n" + " ld %0, %1 \n" " lbu %0, (%0) \n" " .set mips0 \n" : "=r" (res) - : "0" (&vaddr)); + : "m" (vaddr)); write_c0_status(sr); - __asm__("sll $0, $0, 2\n"); - __asm__("sll $0, $0, 2\n"); - __asm__("sll $0, $0, 2\n"); - __asm__("sll $0, $0, 2\n"); + ssnop_4(); return res; } -static void writeb_outer_space(unsigned long phys, unsigned char c) +static void writeb_outer_space(unsigned long long phys, unsigned char c) { unsigned long long vaddr = IO_BASE_64 | phys; unsigned long tmp; @@ -88,30 +85,24 @@ static void writeb_outer_space(unsigned long phys, unsigned char c) sr = read_c0_status(); write_c0_status((sr | ST0_KX) & ~ ST0_IE); - __asm__("sll $0, $0, 2\n"); - __asm__("sll $0, $0, 2\n"); - __asm__("sll $0, $0, 2\n"); - __asm__("sll $0, $0, 2\n"); + ssnop_4(); __asm__ __volatile__ ( " .set mips3 \n" - " ld %0, (%1) \n" + " ld %0, %1 \n" " sb %2, (%0) \n" " .set mips0 \n" - : "=r" (tmp) - : "r" (&vaddr), "r" (c)); + : "=&r" (tmp) + : "m" (vaddr), "r" (c)); write_c0_status(sr); - __asm__("sll $0, $0, 2\n"); - __asm__("sll $0, $0, 2\n"); - __asm__("sll $0, $0, 2\n"); - __asm__("sll $0, $0, 2\n"); + ssnop_4(); } void prom_putchar(char c) { - unsigned long lsr = 0xfd000008UL + offsetof(struct yo_uartregs, iu_lsr); - unsigned long thr = 0xfd000008UL + offsetof(struct yo_uartregs, iu_thr); + unsigned long lsr = 0xfd000008ULL + offsetof(struct yo_uartregs, iu_lsr); + unsigned long thr = 0xfd000008ULL + offsetof(struct yo_uartregs, iu_thr); while ((readb_outer_space(lsr) & 0x20) == 0); writeb_outer_space(thr, c); diff --git a/arch/ppc/platforms/85xx/Makefile b/arch/ppc/platforms/85xx/Makefile index 673b970f1..b5161e386 100644 --- a/arch/ppc/platforms/85xx/Makefile +++ b/arch/ppc/platforms/85xx/Makefile @@ -1,12 +1,10 @@ # # Makefile for the PowerPC 85xx linux kernel. # +obj-$(CONFIG_85xx) += mpc85xx_sys.o mpc85xx_devices.o obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads_common.o mpc8540_ads.o obj-$(CONFIG_MPC8555_CDS) += mpc85xx_cds_common.o obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads_common.o mpc8560_ads.o obj-$(CONFIG_SBC8560) += sbc85xx.o sbc8560.o - -obj-$(CONFIG_MPC8540) += mpc8540.o -obj-$(CONFIG_MPC8555) += mpc8555.o -obj-$(CONFIG_MPC8560) += mpc8560.o +obj-$(CONFIG_STX_GP3) += stx_gp3.o diff --git a/arch/s390/mm/mmap.c b/arch/s390/mm/mmap.c index ebe73afa7..fb187e5a5 100644 --- a/arch/s390/mm/mmap.c +++ b/arch/s390/mm/mmap.c @@ -26,6 +26,7 @@ #include #include +#include /* * Top of mmap area (just below the process stack). @@ -81,3 +82,5 @@ void arch_pick_mmap_layout(struct mm_struct *mm) mm->unmap_area = arch_unmap_area_topdown; } } +EXPORT_SYMBOL_GPL(arch_pick_mmap_layout); + diff --git a/arch/sh/cchips/voyagergx/consistent.c b/arch/sh/cchips/voyagergx/consistent.c index 921d12b42..5b92585a3 100644 --- a/arch/sh/cchips/voyagergx/consistent.c +++ b/arch/sh/cchips/voyagergx/consistent.c @@ -23,7 +23,7 @@ struct voya_alloc_entry { unsigned long len; }; -static spinlock_t voya_list_lock = SPIN_LOCK_UNLOCKED; +static DEFINE_SPINLOCK(voya_list_lock); static LIST_HEAD(voya_alloc_list); #define OHCI_SRAM_START 0xb0000000 diff --git a/arch/sh64/kernel/fpu.c b/arch/sh64/kernel/fpu.c index 175c88a5d..8ad4ed6a6 100644 --- a/arch/sh64/kernel/fpu.c +++ b/arch/sh64/kernel/fpu.c @@ -158,12 +158,12 @@ do_fpu_state_restore(unsigned long ex, struct pt_regs *regs) fpsave(&last_task_used_math->thread.fpu.hard); } last_task_used_math = current; - if (current->used_math) { + if (used_math()) { fpload(¤t->thread.fpu.hard); } else { /* First time FPU user. */ fpload(&init_fpuregs.hard); - current->used_math = 1; + set_used_math(); } release_fpu(); } diff --git a/drivers/char/lcd.h b/drivers/char/lcd.h index 8aed49850..878a95280 100644 --- a/drivers/char/lcd.h +++ b/drivers/char/lcd.h @@ -37,6 +37,8 @@ struct lcd_display { #define LCD_DRIVER "Cobalt LCD Driver v2.10" +#define LCD "lcd: " + #define kLCD_IR 0x0F000000 #define kLCD_DR 0x0F000010 #define kGPI 0x0D000000 diff --git a/drivers/mtd/chips/cfi_util.c b/drivers/mtd/chips/cfi_util.c index 49c97bc96..2b2ede2bf 100644 --- a/drivers/mtd/chips/cfi_util.c +++ b/drivers/mtd/chips/cfi_util.c @@ -7,7 +7,7 @@ * * This code is covered by the GPL. * - * $Id: cfi_util.c,v 1.5 2004/08/12 06:40:23 eric Exp $ + * $Id: cfi_util.c,v 1.8 2004/12/14 19:55:56 nico Exp $ * */ @@ -22,13 +22,14 @@ #include #include #include +#include #include #include #include #include struct cfi_extquery * -cfi_read_pri(struct map_info *map, __u16 adr, __u16 size, const char* name) +__xipram cfi_read_pri(struct map_info *map, __u16 adr, __u16 size, const char* name) { struct cfi_private *cfi = map->fldrv_priv; __u32 base = 0; // cfi->chips[0].start; @@ -40,21 +41,35 @@ cfi_read_pri(struct map_info *map, __u16 adr, __u16 size, const char* name) if (!adr) goto out; - /* Switch it into Query Mode */ - cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, NULL); - extp = kmalloc(size, GFP_KERNEL); if (!extp) { printk(KERN_ERR "Failed to allocate memory\n"); goto out; } - + +#ifdef CONFIG_MTD_XIP + local_irq_disable(); +#endif + + /* Switch it into Query Mode */ + cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, NULL); + /* Read in the Extended Query Table */ for (i=0; idevice_type, NULL); + cfi_send_gen_cmd(0xff, 0, base, map, cfi, cfi->device_type, NULL); + +#ifdef CONFIG_MTD_XIP + (void) map_read(map, base); + asm volatile (".rep 8; nop; .endr"); + local_irq_enable(); +#endif + if (extp->MajorVersion != '1' || (extp->MinorVersion < '0' || extp->MinorVersion > '3')) { printk(KERN_WARNING " Unknown %s Extended Query " @@ -62,15 +77,9 @@ cfi_read_pri(struct map_info *map, __u16 adr, __u16 size, const char* name) extp->MinorVersion); kfree(extp); extp = NULL; - goto out; } -out: - /* Make sure it's in read mode */ - cfi_send_gen_cmd(0xf0, 0, base, map, cfi, cfi->device_type, NULL); - cfi_send_gen_cmd(0xff, 0, base, map, cfi, cfi->device_type, NULL); - - return extp; + out: return extp; } EXPORT_SYMBOL(cfi_read_pri); @@ -156,7 +165,6 @@ int cfi_varsize_frob(struct mtd_info *mtd, varsize_frob_t frob, i=first; while(len) { - unsigned long chipmask; int size = regions[i].erasesize; ret = (*frob)(map, &cfi->chips[chipnum], adr, size, thunk); @@ -165,10 +173,10 @@ int cfi_varsize_frob(struct mtd_info *mtd, varsize_frob_t frob, return ret; adr += size; + ofs += size; len -= size; - chipmask = (1 << cfi->chipshift) - 1; - if ((adr & chipmask) == ((regions[i].offset + size * regions[i].numblocks) & chipmask)) + if (ofs == regions[i].offset + size * regions[i].numblocks) i++; if (adr >> cfi->chipshift) { diff --git a/drivers/pcmcia/pd6729.h b/drivers/pcmcia/pd6729.h index 9e90520ef..f392e458c 100644 --- a/drivers/pcmcia/pd6729.h +++ b/drivers/pcmcia/pd6729.h @@ -16,13 +16,15 @@ #define PD67_EXD_VS1(s) (0x01 << ((s) << 1)) #define PD67_EXD_VS2(s) (0x02 << ((s) << 1)) - - +/* Default ISA interrupt mask */ +#define PD67_MASK 0x0eb8 /* irq 11,10,9,7,5,4,3 */ struct pd6729_socket { int number; + int card_irq; unsigned long io_base; /* base io address of the socket */ struct pcmcia_socket socket; + struct timer_list poll_timer; }; #endif diff --git a/drivers/pcmcia/soc_common.h b/drivers/pcmcia/soc_common.h index f77923ced..700a155fb 100644 --- a/drivers/pcmcia/soc_common.h +++ b/drivers/pcmcia/soc_common.h @@ -53,7 +53,7 @@ struct soc_pcmcia_socket { struct resource res_io; struct resource res_mem; struct resource res_attr; - void *virt_io; + void __iomem *virt_io; unsigned int irq_state; diff --git a/fs/xfs/linux-2.6/xfs_stats.h b/fs/xfs/linux-2.6/xfs_stats.h index 04566006f..3f756a6c3 100644 --- a/fs/xfs/linux-2.6/xfs_stats.h +++ b/fs/xfs/linux-2.6/xfs_stats.h @@ -140,11 +140,13 @@ struct xfsstats { DECLARE_PER_CPU(struct xfsstats, xfsstats); -/* We don't disable preempt, not too worried about poking the - * wrong cpu's stat for now */ -#define XFS_STATS_INC(count) (__get_cpu_var(xfsstats).count++) -#define XFS_STATS_DEC(count) (__get_cpu_var(xfsstats).count--) -#define XFS_STATS_ADD(count, inc) (__get_cpu_var(xfsstats).count += (inc)) +/* + * We don't disable preempt, not too worried about poking the + * wrong CPU's stat for now (also aggregated before reporting). + */ +#define XFS_STATS_INC(v) (per_cpu(xfsstats, current_cpu()).v++) +#define XFS_STATS_DEC(v) (per_cpu(xfsstats, current_cpu()).v--) +#define XFS_STATS_ADD(v, inc) (per_cpu(xfsstats, current_cpu()).v += (inc)) extern void xfs_init_procfs(void); extern void xfs_cleanup_procfs(void); diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h index a048cbc58..4ac964b90 100644 --- a/include/asm-arm/arch-ixp4xx/hardware.h +++ b/include/asm-arm/arch-ixp4xx/hardware.h @@ -27,6 +27,13 @@ #define pcibios_assign_all_busses() 1 +#if defined(CONFIG_CPU_IXP465) && !defined(__ASSEMBLY__) +extern unsigned int processor_id; +#define cpu_is_ixp465() ((processor_id & 0xffffffc0) == 0x69054200) +#else +#define cpu_is_ixp465() (0) +#endif + /* Register locations and bits */ #include "ixp4xx-regs.h" diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h index c782b560c..ca808281c 100644 --- a/include/asm-arm/arch-ixp4xx/irqs.h +++ b/include/asm-arm/arch-ixp4xx/irqs.h @@ -15,7 +15,6 @@ #ifndef _ARCH_IXP4XX_IRQS_H_ #define _ARCH_IXP4XX_IRQS_H_ -#define NR_IRQS 32 #define IRQ_IXP4XX_NPEA 0 #define IRQ_IXP4XX_NPEB 1 @@ -49,6 +48,25 @@ #define IRQ_IXP4XX_GPIO12 29 #define IRQ_IXP4XX_SW_INT1 30 #define IRQ_IXP4XX_SW_INT2 31 +#define IRQ_IXP4XX_USB_HOST 32 +#define IRQ_IXP4XX_I2C 33 +#define IRQ_IXP4XX_SSP 34 +#define IRQ_IXP4XX_TSYNC 35 +#define IRQ_IXP4XX_EAU_DONE 36 +#define IRQ_IXP4XX_SHA_DONE 37 +#define IRQ_IXP4XX_SWCP_PE 58 +#define IRQ_IXP4XX_QM_PE 60 +#define IRQ_IXP4XX_MCU_ECC 61 +#define IRQ_IXP4XX_EXP_PE 62 + +/* + * Only first 32 sources are valid if running on IXP42x systems + */ +#ifndef CONFIG_CPU_IXP46X +#define NR_IRQS 32 +#else +#define NR_IRQS 64 +#endif #define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU) diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h index 0f352ac94..8eeb1db63 100644 --- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h +++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h @@ -43,6 +43,10 @@ * 0xC8000000 0x0000C000 0xffbf2000 On-Chip Peripherals */ +/* + * Queue Manager + */ +#define IXP4XX_QMGR_BASE_PHYS (0x60000000) /* * Expansion BUS Configuration registers @@ -107,7 +111,9 @@ #define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000) #define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000) #define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000) -#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000) +#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000) +#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000) +#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000) #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000) #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000) @@ -115,7 +121,9 @@ #define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000) #define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000) #define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000) -#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000) +#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000) +#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000) +#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000) /* * Constants to make it easy to access Interrupt Controller registers @@ -129,6 +137,17 @@ #define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */ #define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */ +/* + * IXP465-only + */ +#define IXP4XX_ICPR2_OFFSET 0x20 /* Interrupt Status 2 */ +#define IXP4XX_ICMR2_OFFSET 0x24 /* Interrupt Enable 2 */ +#define IXP4XX_ICLR2_OFFSET 0x28 /* Interrupt IRQ/FIQ Select 2 */ +#define IXP4XX_ICIP2_OFFSET 0x2C /* IRQ Status */ +#define IXP4XX_ICFP2_OFFSET 0x30 /* FIQ Status */ +#define IXP4XX_ICEEN_OFFSET 0x34 /* Error High Pri Enable */ + + /* * Interrupt Controller Register Definitions. */ @@ -143,6 +162,12 @@ #define IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET) #define IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET) #define IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET) +#define IXP4XX_ICPR2 IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET) +#define IXP4XX_ICMR2 IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET) +#define IXP4XX_ICLR2 IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET) +#define IXP4XX_ICIP2 IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET) +#define IXP4XX_ICFP2 IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET) +#define IXP4XX_ICEEN IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET) /* * Constants to make it easy to access GPIO registers @@ -548,4 +573,19 @@ #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ +#ifndef __ASSEMBLY__ +static inline int cpu_is_ixp46x(void) +{ +#ifdef CONFIG_CPU_IXP46X + unsigned int processor_id; + + asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :); + + if ((processor_id & 0xffffff00) == 0x69054200) + return 1; +#endif + return 0; +} +#endif + #endif diff --git a/include/asm-ia64/cpu.h b/include/asm-ia64/cpu.h index 33c5d0fe9..e87fa3210 100644 --- a/include/asm-ia64/cpu.h +++ b/include/asm-ia64/cpu.h @@ -14,4 +14,9 @@ DECLARE_PER_CPU(struct ia64_cpu, cpu_devices); DECLARE_PER_CPU(int, cpu_state); +extern int arch_register_cpu(int num); +#ifdef CONFIG_HOTPLUG_CPU +extern void arch_unregister_cpu(int); +#endif + #endif /* _ASM_IA64_CPU_H_ */ diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h index ddb265c91..5c2fcf13d 100644 --- a/include/asm-ia64/sn/shub_mmr.h +++ b/include/asm-ia64/sn/shub_mmr.h @@ -14,117 +14,96 @@ /* Register "SH_IPI_INT" */ /* SHub Inter-Processor Interrupt Registers */ /* ==================================================================== */ -#define SH_IPI_INT 0x0000000110000380UL -#define SH_IPI_INT_MASK 0x8ff3ffffffefffffUL -#define SH_IPI_INT_INIT 0x0000000000000000UL +#define SH1_IPI_INT 0x0000000110000380 +#define SH2_IPI_INT 0x0000000010000380 /* SH_IPI_INT_TYPE */ /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ #define SH_IPI_INT_TYPE_SHFT 0 -#define SH_IPI_INT_TYPE_MASK 0x0000000000000007UL +#define SH_IPI_INT_TYPE_MASK 0x0000000000000007 /* SH_IPI_INT_AGT */ /* Description: Agent, must be 0 for SHub */ #define SH_IPI_INT_AGT_SHFT 3 -#define SH_IPI_INT_AGT_MASK 0x0000000000000008UL +#define SH_IPI_INT_AGT_MASK 0x0000000000000008 /* SH_IPI_INT_PID */ /* Description: Processor ID, same setting as on targeted McKinley */ #define SH_IPI_INT_PID_SHFT 4 -#define SH_IPI_INT_PID_MASK 0x00000000000ffff0UL +#define SH_IPI_INT_PID_MASK 0x00000000000ffff0 /* SH_IPI_INT_BASE */ /* Description: Optional interrupt vector area, 2MB aligned */ #define SH_IPI_INT_BASE_SHFT 21 -#define SH_IPI_INT_BASE_MASK 0x0003ffffffe00000UL +#define SH_IPI_INT_BASE_MASK 0x0003ffffffe00000 /* SH_IPI_INT_IDX */ /* Description: Targeted McKinley interrupt vector */ #define SH_IPI_INT_IDX_SHFT 52 -#define SH_IPI_INT_IDX_MASK 0x0ff0000000000000UL +#define SH_IPI_INT_IDX_MASK 0x0ff0000000000000 /* SH_IPI_INT_SEND */ /* Description: Send Interrupt Message to PI, This generates a puls */ #define SH_IPI_INT_SEND_SHFT 63 -#define SH_IPI_INT_SEND_MASK 0x8000000000000000UL +#define SH_IPI_INT_SEND_MASK 0x8000000000000000 /* ==================================================================== */ /* Register "SH_EVENT_OCCURRED" */ /* SHub Interrupt Event Occurred */ /* ==================================================================== */ -#define SH_EVENT_OCCURRED 0x0000000110010000UL -#define SH_EVENT_OCCURRED_ALIAS 0x0000000110010008UL +#define SH1_EVENT_OCCURRED 0x0000000110010000 +#define SH1_EVENT_OCCURRED_ALIAS 0x0000000110010008 +#define SH2_EVENT_OCCURRED 0x0000000010010000 +#define SH2_EVENT_OCCURRED_ALIAS 0x0000000010010008 /* ==================================================================== */ /* Register "SH_PI_CAM_CONTROL" */ /* CRB CAM MMR Access Control */ /* ==================================================================== */ -#ifndef __ASSEMBLY__ -#define SH_PI_CAM_CONTROL 0x0000000120050300UL -#else -#define SH_PI_CAM_CONTROL 0x0000000120050300 -#endif +#define SH1_PI_CAM_CONTROL 0x0000000120050300 /* ==================================================================== */ /* Register "SH_SHUB_ID" */ /* SHub ID Number */ /* ==================================================================== */ -#define SH_SHUB_ID 0x0000000110060580UL -#define SH_SHUB_ID_REVISION_SHFT 28 -#define SH_SHUB_ID_REVISION_MASK 0x00000000f0000000 - -/* ==================================================================== */ -/* Register "SH_PTC_0" */ -/* Puge Translation Cache Message Configuration Information */ -/* ==================================================================== */ -#define SH_PTC_0 0x00000001101a0000UL -#define SH_PTC_1 0x00000001101a0080UL +#define SH1_SHUB_ID 0x0000000110060580 +#define SH1_SHUB_ID_REVISION_SHFT 28 +#define SH1_SHUB_ID_REVISION_MASK 0x00000000f0000000 /* ==================================================================== */ /* Register "SH_RTC" */ /* Real-time Clock */ /* ==================================================================== */ -#define SH_RTC 0x00000001101c0000UL -#define SH_RTC_MASK 0x007fffffffffffffUL - -/* ==================================================================== */ -/* Register "SH_MEMORY_WRITE_STATUS_0|1" */ -/* Memory Write Status for CPU 0 & 1 */ -/* ==================================================================== */ -#define SH_MEMORY_WRITE_STATUS_0 0x0000000120070000UL -#define SH_MEMORY_WRITE_STATUS_1 0x0000000120070080UL +#define SH1_RTC 0x00000001101c0000 +#define SH2_RTC 0x00000002101c0000 +#define SH_RTC_MASK 0x007fffffffffffff /* ==================================================================== */ /* Register "SH_PIO_WRITE_STATUS_0|1" */ /* PIO Write Status for CPU 0 & 1 */ /* ==================================================================== */ -#ifndef __ASSEMBLY__ -#define SH_PIO_WRITE_STATUS_0 0x0000000120070200UL -#define SH_PIO_WRITE_STATUS_1 0x0000000120070280UL +#define SH1_PIO_WRITE_STATUS_0 0x0000000120070200 +#define SH1_PIO_WRITE_STATUS_1 0x0000000120070280 +#define SH2_PIO_WRITE_STATUS_0 0x0000000020070200 +#define SH2_PIO_WRITE_STATUS_1 0x0000000020070280 +#define SH2_PIO_WRITE_STATUS_2 0x0000000020070300 +#define SH2_PIO_WRITE_STATUS_3 0x0000000020070380 /* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */ /* Description: Deadlock response detected */ -#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT 1 -#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_MASK 0x0000000000000002 +#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1 +#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK 0x0000000000000002 /* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */ /* Description: Count of currently pending PIO writes */ -#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 56 -#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x3f00000000000000UL -#else -#define SH_PIO_WRITE_STATUS_0 0x0000000120070200 -#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 56 -#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT 1 -#endif +#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56 +#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK 0x3f00000000000000 /* ==================================================================== */ /* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */ /* ==================================================================== */ -#ifndef __ASSEMBLY__ -#define SH_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208UL -#else -#define SH_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208 -#endif +#define SH1_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208 +#define SH2_PIO_WRITE_STATUS_0_ALIAS 0x0000000020070208 /* ==================================================================== */ /* Register "SH_EVENT_OCCURRED" */ @@ -151,61 +130,85 @@ #define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000 /* ==================================================================== */ -/* Register "SH_PTC_0" */ +/* LEDS */ +/* ==================================================================== */ +#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL +#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL +#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL +#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL + +#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL +#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL +#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL +#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL + +/* ==================================================================== */ +/* Register "SH1_PTC_0" */ /* Puge Translation Cache Message Configuration Information */ /* ==================================================================== */ -#define SH_PTC_0 0x00000001101a0000UL -#define SH_PTC_0_MASK 0x80000000fffffffd -#define SH_PTC_0_INIT 0x0000000000000000 +#define SH1_PTC_0 0x00000001101a0000 -/* SH_PTC_0_A */ +/* SH1_PTC_0_A */ /* Description: Type */ -#define SH_PTC_0_A_SHFT 0 -#define SH_PTC_0_A_MASK 0x0000000000000001 +#define SH1_PTC_0_A_SHFT 0 -/* SH_PTC_0_PS */ +/* SH1_PTC_0_PS */ /* Description: Page Size */ -#define SH_PTC_0_PS_SHFT 2 -#define SH_PTC_0_PS_MASK 0x00000000000000fc +#define SH1_PTC_0_PS_SHFT 2 -/* SH_PTC_0_RID */ +/* SH1_PTC_0_RID */ /* Description: Region ID */ -#define SH_PTC_0_RID_SHFT 8 -#define SH_PTC_0_RID_MASK 0x00000000ffffff00 +#define SH1_PTC_0_RID_SHFT 8 -/* SH_PTC_0_START */ +/* SH1_PTC_0_START */ /* Description: Start */ -#define SH_PTC_0_START_SHFT 63 -#define SH_PTC_0_START_MASK 0x8000000000000000 +#define SH1_PTC_0_START_SHFT 63 /* ==================================================================== */ -/* Register "SH_PTC_1" */ +/* Register "SH1_PTC_1" */ /* Puge Translation Cache Message Configuration Information */ /* ==================================================================== */ -#define SH_PTC_1 0x00000001101a0080UL -#define SH_PTC_1_MASK 0x9ffffffffffff000 -#define SH_PTC_1_INIT 0x0000000000000000 - -/* SH_PTC_1_VPN */ -/* Description: Virtual page number */ -#define SH_PTC_1_VPN_SHFT 12 -#define SH_PTC_1_VPN_MASK 0x1ffffffffffff000 +#define SH1_PTC_1 0x00000001101a0080 -/* SH_PTC_1_START */ +/* SH1_PTC_1_START */ /* Description: PTC_1 Start */ -#define SH_PTC_1_START_SHFT 63 -#define SH_PTC_1_START_MASK 0x8000000000000000 +#define SH1_PTC_1_START_SHFT 63 -/* - * Register definitions - */ + +/* ==================================================================== */ +/* Register "SH2_PTC" */ +/* Puge Translation Cache Message Configuration Information */ +/* ==================================================================== */ +#define SH2_PTC 0x0000000170000000 + +/* SH2_PTC_A */ +/* Description: Type */ +#define SH2_PTC_A_SHFT 0 + +/* SH2_PTC_PS */ +/* Description: Page Size */ +#define SH2_PTC_PS_SHFT 2 + +/* SH2_PTC_RID */ +/* Description: Region ID */ +#define SH2_PTC_RID_SHFT 4 + +/* SH2_PTC_START */ +/* Description: Start */ +#define SH2_PTC_START_SHFT 63 + +/* SH2_PTC_ADDR_RID */ +/* Description: Region ID */ +#define SH2_PTC_ADDR_SHFT 4 +#define SH2_PTC_ADDR_MASK 0x1ffffffffffff000 /* ==================================================================== */ /* Register "SH_RTC1_INT_CONFIG" */ /* SHub RTC 1 Interrupt Config Registers */ /* ==================================================================== */ -#define SH_RTC1_INT_CONFIG 0x0000000110001480 +#define SH1_RTC1_INT_CONFIG 0x0000000110001480 +#define SH2_RTC1_INT_CONFIG 0x0000000010001480 #define SH_RTC1_INT_CONFIG_MASK 0x0ff3ffffffefffff #define SH_RTC1_INT_CONFIG_INIT 0x0000000000000000 @@ -239,7 +242,8 @@ /* SHub RTC 1 Interrupt Enable Registers */ /* ==================================================================== */ -#define SH_RTC1_INT_ENABLE 0x0000000110001500 +#define SH1_RTC1_INT_ENABLE 0x0000000110001500 +#define SH2_RTC1_INT_ENABLE 0x0000000010001500 #define SH_RTC1_INT_ENABLE_MASK 0x0000000000000001 #define SH_RTC1_INT_ENABLE_INIT 0x0000000000000000 @@ -253,7 +257,8 @@ /* SHub RTC 2 Interrupt Config Registers */ /* ==================================================================== */ -#define SH_RTC2_INT_CONFIG 0x0000000110001580 +#define SH1_RTC2_INT_CONFIG 0x0000000110001580 +#define SH2_RTC2_INT_CONFIG 0x0000000010001580 #define SH_RTC2_INT_CONFIG_MASK 0x0ff3ffffffefffff #define SH_RTC2_INT_CONFIG_INIT 0x0000000000000000 @@ -287,7 +292,8 @@ /* SHub RTC 2 Interrupt Enable Registers */ /* ==================================================================== */ -#define SH_RTC2_INT_ENABLE 0x0000000110001600 +#define SH1_RTC2_INT_ENABLE 0x0000000110001600 +#define SH2_RTC2_INT_ENABLE 0x0000000010001600 #define SH_RTC2_INT_ENABLE_MASK 0x0000000000000001 #define SH_RTC2_INT_ENABLE_INIT 0x0000000000000000 @@ -301,7 +307,8 @@ /* SHub RTC 3 Interrupt Config Registers */ /* ==================================================================== */ -#define SH_RTC3_INT_CONFIG 0x0000000110001680 +#define SH1_RTC3_INT_CONFIG 0x0000000110001680 +#define SH2_RTC3_INT_CONFIG 0x0000000010001680 #define SH_RTC3_INT_CONFIG_MASK 0x0ff3ffffffefffff #define SH_RTC3_INT_CONFIG_INIT 0x0000000000000000 @@ -335,7 +342,8 @@ /* SHub RTC 3 Interrupt Enable Registers */ /* ==================================================================== */ -#define SH_RTC3_INT_ENABLE 0x0000000110001700 +#define SH1_RTC3_INT_ENABLE 0x0000000110001700 +#define SH2_RTC3_INT_ENABLE 0x0000000010001700 #define SH_RTC3_INT_ENABLE_MASK 0x0000000000000001 #define SH_RTC3_INT_ENABLE_INIT 0x0000000000000000 @@ -364,7 +372,8 @@ /* RTC Compare Value for Processor B */ /* ==================================================================== */ -#define SH_INT_CMPB 0x00000001101b0080 +#define SH1_INT_CMPB 0x00000001101b0080 +#define SH2_INT_CMPB 0x00000000101b0080 #define SH_INT_CMPB_MASK 0x007fffffffffffff #define SH_INT_CMPB_INIT 0x0000000000000000 @@ -378,7 +387,8 @@ /* RTC Compare Value for Processor C */ /* ==================================================================== */ -#define SH_INT_CMPC 0x00000001101b0100 +#define SH1_INT_CMPC 0x00000001101b0100 +#define SH2_INT_CMPC 0x00000000101b0100 #define SH_INT_CMPC_MASK 0x007fffffffffffff #define SH_INT_CMPC_INIT 0x0000000000000000 @@ -392,7 +402,8 @@ /* RTC Compare Value for Processor D */ /* ==================================================================== */ -#define SH_INT_CMPD 0x00000001101b0180 +#define SH1_INT_CMPD 0x00000001101b0180 +#define SH2_INT_CMPD 0x00000000101b0180 #define SH_INT_CMPD_MASK 0x007fffffffffffff #define SH_INT_CMPD_INIT 0x0000000000000000 @@ -401,4 +412,30 @@ #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 #define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff + +/* ==================================================================== */ +/* Some MMRs are functionally identical (or close enough) on both SHUB1 */ +/* and SHUB2 that it makes sense to define a geberic name for the MMR. */ +/* It is acceptible to use (for example) SH_IPI_INT to reference the */ +/* the IPI MMR. The value of SH_IPI_INT is determined at runtime based */ +/* on the type of the SHUB. Do not use these #defines in performance */ +/* critical code or loops - there is a small performance penalty. */ +/* ==================================================================== */ +#define shubmmr(a,b) (is_shub2() ? a##2_##b : a##1_##b) + +#define SH_REAL_JUNK_BUS_LED0 shubmmr(SH, REAL_JUNK_BUS_LED0) +#define SH_IPI_INT shubmmr(SH, IPI_INT) +#define SH_EVENT_OCCURRED shubmmr(SH, EVENT_OCCURRED) +#define SH_EVENT_OCCURRED_ALIAS shubmmr(SH, EVENT_OCCURRED_ALIAS) +#define SH_RTC shubmmr(SH, RTC) +#define SH_RTC1_INT_CONFIG shubmmr(SH, RTC1_INT_CONFIG) +#define SH_RTC1_INT_ENABLE shubmmr(SH, RTC1_INT_ENABLE) +#define SH_RTC2_INT_CONFIG shubmmr(SH, RTC2_INT_CONFIG) +#define SH_RTC2_INT_ENABLE shubmmr(SH, RTC2_INT_ENABLE) +#define SH_RTC3_INT_CONFIG shubmmr(SH, RTC3_INT_CONFIG) +#define SH_RTC3_INT_ENABLE shubmmr(SH, RTC3_INT_ENABLE) +#define SH_INT_CMPB shubmmr(SH, INT_CMPB) +#define SH_INT_CMPC shubmmr(SH, INT_CMPC) +#define SH_INT_CMPD shubmmr(SH, INT_CMPD) + #endif /* _ASM_IA64_SN_SHUB_MMR_H */ diff --git a/include/asm-mips/pmon.h b/include/asm-mips/pmon.h index 7b4f990e1..260f3448c 100644 --- a/include/asm-mips/pmon.h +++ b/include/asm-mips/pmon.h @@ -4,22 +4,43 @@ * for more details. * * Copyright (C) 2004 by Ralf Baechle + * + * The cpustart method is a PMC-Sierra's function to start the secondary CPU. + * Stock PMON 2000 has the smpfork, semlock and semunlock methods instead. */ #ifndef _ASM_PMON_H #define _ASM_PMON_H struct callvectors { - int (*open) (char*, int, int); /* 0 */ - int (*close) (int); /* 4 */ - int (*read) (int, void*, int); /* 8 */ - int (*write) (int, void*, int); /* 12 */ - off_t (*lseek) (int, off_t, int); /* 16 */ - int (*printf) (const char*, ...); /* 20 */ - void (*cacheflush) (void); /* 24 */ - char* (*gets) (char*); /* 28 */ - int (*cpustart) (int, void *, int, int); /* 32 */ + int (*open) (char*, int, int); + int (*close) (int); + int (*read) (int, void*, int); + int (*write) (int, void*, int); + off_t (*lseek) (int, off_t, int); + int (*printf) (const char*, ...); + void (*cacheflush) (void); + char* (*gets) (char*); + union { + int (*smpfork) (unsigned long cp, char *sp); + int (*cpustart) (long, long, long, long); + } _s; + int (*semlock) (int sem); + void (*semunlock) (int sem); }; extern struct callvectors *debug_vectors; +#define pmon_open(name, flags, mode) debug_vectors->open(name, flage, mode) +#define pmon_close(fd) debug_vectors->close(fd) +#define pmon_read(fd, buf, count) debug_vectors->read(fd, buf, count) +#define pmon_write(fd, buf, count) debug_vectors->write(fd, buf, count) +#define pmon_lseek(fd, off, whence) debug_vectors->lseek(fd, off, whence) +#define pmon_printf(fmt...) debug_vectors->printf(fmt) +#define pmon_cacheflush() debug_vectors->cacheflush() +#define pmon_gets(s) debug_vectors->gets(s) +#define pmon_cpustart(n, f, sp, gp) debug_vectors->_s.cpustart(n, f, sp, gp) +#define pmon_smpfork(cp, sp) debug_vectors->_s.smpfork(cp, sp) +#define pmon_semlock(sem) debug_vectors->semlock(sem) +#define pmon_semunlock(sem) debug_vectors->semunlock(sem) + #endif /* _ASM_PMON_H */ diff --git a/include/asm-sh64/thread_info.h b/include/asm-sh64/thread_info.h index f9d2a22db..99e7c926f 100644 --- a/include/asm-sh64/thread_info.h +++ b/include/asm-sh64/thread_info.h @@ -74,6 +74,7 @@ static inline struct thread_info *current_thread_info(void) #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ #define TIF_SIGPENDING 2 /* signal pending */ #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ +#define TIF_MEMDIE 4 #define THREAD_SIZE 16384 diff --git a/include/linux/prio_tree.h b/include/linux/prio_tree.h index 6356a511f..db04abb55 100644 --- a/include/linux/prio_tree.h +++ b/include/linux/prio_tree.h @@ -1,15 +1,38 @@ #ifndef _LINUX_PRIO_TREE_H #define _LINUX_PRIO_TREE_H +/* + * K&R 2nd ed. A8.3 somewhat obliquely hints that initial sequences of struct + * fields with identical types should end up at the same location. We'll use + * this until we can scrap struct raw_prio_tree_node. + * + * Note: all this could be done more elegantly by using unnamed union/struct + * fields. However, gcc 2.95.3 and apparently also gcc 3.0.4 don't support this + * language extension. + */ + +struct raw_prio_tree_node { + struct prio_tree_node *left; + struct prio_tree_node *right; + struct prio_tree_node *parent; +}; + struct prio_tree_node { struct prio_tree_node *left; struct prio_tree_node *right; struct prio_tree_node *parent; + unsigned long start; + unsigned long last; /* last location _in_ interval */ }; struct prio_tree_root { struct prio_tree_node *prio_tree_node; - unsigned int index_bits; + unsigned short index_bits; + unsigned short raw; + /* + * 0: nodes are of type struct prio_tree_node + * 1: nodes are of type raw_prio_tree_node + */ }; struct prio_tree_iter { @@ -29,14 +52,19 @@ static inline void prio_tree_iter_init(struct prio_tree_iter *iter, iter->root = root; iter->r_index = r_index; iter->h_index = h_index; + iter->cur = NULL; } -#define INIT_PRIO_TREE_ROOT(ptr) \ +#define __INIT_PRIO_TREE_ROOT(ptr, _raw) \ do { \ (ptr)->prio_tree_node = NULL; \ (ptr)->index_bits = 1; \ + (ptr)->raw = (_raw); \ } while (0) +#define INIT_PRIO_TREE_ROOT(ptr) __INIT_PRIO_TREE_ROOT(ptr, 0) +#define INIT_RAW_PRIO_TREE_ROOT(ptr) __INIT_PRIO_TREE_ROOT(ptr, 1) + #define INIT_PRIO_TREE_NODE(ptr) \ do { \ (ptr)->left = (ptr)->right = (ptr)->parent = (ptr); \ @@ -73,4 +101,20 @@ static inline int prio_tree_right_empty(const struct prio_tree_node *node) return node->right == node; } + +struct prio_tree_node *prio_tree_replace(struct prio_tree_root *root, + struct prio_tree_node *old, struct prio_tree_node *node); +struct prio_tree_node *prio_tree_insert(struct prio_tree_root *root, + struct prio_tree_node *node); +void prio_tree_remove(struct prio_tree_root *root, struct prio_tree_node *node); +struct prio_tree_node *prio_tree_next(struct prio_tree_iter *iter); + +#define raw_prio_tree_replace(root, old, node) \ + prio_tree_replace(root, (struct prio_tree_node *) (old), \ + (struct prio_tree_node *) (node)) +#define raw_prio_tree_insert(root, node) \ + prio_tree_insert(root, (struct prio_tree_node *) (node)) +#define raw_prio_tree_remove(root, node) \ + prio_tree_remove(root, (struct prio_tree_node *) (node)) + #endif /* _LINUX_PRIO_TREE_H */ diff --git a/mm/prio_tree.c b/mm/prio_tree.c index 3bd8d5a99..b4e76c25f 100644 --- a/mm/prio_tree.c +++ b/mm/prio_tree.c @@ -11,473 +11,24 @@ * 02Feb2004 Initial version */ -#include -#include #include #include /* - * A clever mix of heap and radix trees forms a radix priority search tree (PST) - * which is useful for storing intervals, e.g, we can consider a vma as a closed - * interval of file pages [offset_begin, offset_end], and store all vmas that - * map a file in a PST. Then, using the PST, we can answer a stabbing query, - * i.e., selecting a set of stored intervals (vmas) that overlap with (map) a - * given input interval X (a set of consecutive file pages), in "O(log n + m)" - * time where 'log n' is the height of the PST, and 'm' is the number of stored - * intervals (vmas) that overlap (map) with the input interval X (the set of - * consecutive file pages). - * - * In our implementation, we store closed intervals of the form [radix_index, - * heap_index]. We assume that always radix_index <= heap_index. McCreight's PST - * is designed for storing intervals with unique radix indices, i.e., each - * interval have different radix_index. However, this limitation can be easily - * overcome by using the size, i.e., heap_index - radix_index, as part of the - * index, so we index the tree using [(radix_index,size), heap_index]. - * - * When the above-mentioned indexing scheme is used, theoretically, in a 32 bit - * machine, the maximum height of a PST can be 64. We can use a balanced version - * of the priority search tree to optimize the tree height, but the balanced - * tree proposed by McCreight is too complex and memory-hungry for our purpose. + * See lib/prio_tree.c for details on the general radix priority search tree + * code. */ /* - * The following macros are used for implementing prio_tree for i_mmap + * The following #defines are mirrored from lib/prio_tree.c. They're only used + * for debugging, and should be removed (along with the debugging code using + * them) when switching also VMAs to the regular prio_tree code. */ #define RADIX_INDEX(vma) ((vma)->vm_pgoff) #define VMA_SIZE(vma) (((vma)->vm_end - (vma)->vm_start) >> PAGE_SHIFT) /* avoid overflow */ -#define HEAP_INDEX(vma) ((vma)->vm_pgoff + (VMA_SIZE(vma) - 1)) - -#define GET_INDEX_VMA(vma, radix, heap) \ -do { \ - radix = RADIX_INDEX(vma); \ - heap = HEAP_INDEX(vma); \ -} while (0) - -#define GET_INDEX(node, radix, heap) \ -do { \ - struct vm_area_struct *__tmp = \ - prio_tree_entry(node, struct vm_area_struct, shared.prio_tree_node);\ - GET_INDEX_VMA(__tmp, radix, heap); \ -} while (0) - -static unsigned long index_bits_to_maxindex[BITS_PER_LONG]; - -void __init prio_tree_init(void) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(index_bits_to_maxindex) - 1; i++) - index_bits_to_maxindex[i] = (1UL << (i + 1)) - 1; - index_bits_to_maxindex[ARRAY_SIZE(index_bits_to_maxindex) - 1] = ~0UL; -} - -/* - * Maximum heap_index that can be stored in a PST with index_bits bits - */ -static inline unsigned long prio_tree_maxindex(unsigned int bits) -{ - return index_bits_to_maxindex[bits - 1]; -} - -static void prio_tree_remove(struct prio_tree_root *, struct prio_tree_node *); - -/* - * Extend a priority search tree so that it can store a node with heap_index - * max_heap_index. In the worst case, this algorithm takes O((log n)^2). - * However, this function is used rarely and the common case performance is - * not bad. - */ -static struct prio_tree_node *prio_tree_expand(struct prio_tree_root *root, - struct prio_tree_node *node, unsigned long max_heap_index) -{ - struct prio_tree_node *first = NULL, *prev, *last = NULL; - - if (max_heap_index > prio_tree_maxindex(root->index_bits)) - root->index_bits++; - - while (max_heap_index > prio_tree_maxindex(root->index_bits)) { - root->index_bits++; - - if (prio_tree_empty(root)) - continue; - - if (first == NULL) { - first = root->prio_tree_node; - prio_tree_remove(root, root->prio_tree_node); - INIT_PRIO_TREE_NODE(first); - last = first; - } else { - prev = last; - last = root->prio_tree_node; - prio_tree_remove(root, root->prio_tree_node); - INIT_PRIO_TREE_NODE(last); - prev->left = last; - last->parent = prev; - } - } - - INIT_PRIO_TREE_NODE(node); - - if (first) { - node->left = first; - first->parent = node; - } else - last = node; - - if (!prio_tree_empty(root)) { - last->left = root->prio_tree_node; - last->left->parent = last; - } - - root->prio_tree_node = node; - return node; -} - -/* - * Replace a prio_tree_node with a new node and return the old node - */ -static struct prio_tree_node *prio_tree_replace(struct prio_tree_root *root, - struct prio_tree_node *old, struct prio_tree_node *node) -{ - INIT_PRIO_TREE_NODE(node); - - if (prio_tree_root(old)) { - BUG_ON(root->prio_tree_node != old); - /* - * We can reduce root->index_bits here. However, it is complex - * and does not help much to improve performance (IMO). - */ - node->parent = node; - root->prio_tree_node = node; - } else { - node->parent = old->parent; - if (old->parent->left == old) - old->parent->left = node; - else - old->parent->right = node; - } - - if (!prio_tree_left_empty(old)) { - node->left = old->left; - old->left->parent = node; - } - - if (!prio_tree_right_empty(old)) { - node->right = old->right; - old->right->parent = node; - } - - return old; -} - -/* - * Insert a prio_tree_node @node into a radix priority search tree @root. The - * algorithm typically takes O(log n) time where 'log n' is the number of bits - * required to represent the maximum heap_index. In the worst case, the algo - * can take O((log n)^2) - check prio_tree_expand. - * - * If a prior node with same radix_index and heap_index is already found in - * the tree, then returns the address of the prior node. Otherwise, inserts - * @node into the tree and returns @node. - */ -static struct prio_tree_node *prio_tree_insert(struct prio_tree_root *root, - struct prio_tree_node *node) -{ - struct prio_tree_node *cur, *res = node; - unsigned long radix_index, heap_index; - unsigned long r_index, h_index, index, mask; - int size_flag = 0; - - GET_INDEX(node, radix_index, heap_index); - - if (prio_tree_empty(root) || - heap_index > prio_tree_maxindex(root->index_bits)) - return prio_tree_expand(root, node, heap_index); - - cur = root->prio_tree_node; - mask = 1UL << (root->index_bits - 1); - - while (mask) { - GET_INDEX(cur, r_index, h_index); - - if (r_index == radix_index && h_index == heap_index) - return cur; - - if (h_index < heap_index || - (h_index == heap_index && r_index > radix_index)) { - struct prio_tree_node *tmp = node; - node = prio_tree_replace(root, cur, node); - cur = tmp; - /* swap indices */ - index = r_index; - r_index = radix_index; - radix_index = index; - index = h_index; - h_index = heap_index; - heap_index = index; - } - - if (size_flag) - index = heap_index - radix_index; - else - index = radix_index; - - if (index & mask) { - if (prio_tree_right_empty(cur)) { - INIT_PRIO_TREE_NODE(node); - cur->right = node; - node->parent = cur; - return res; - } else - cur = cur->right; - } else { - if (prio_tree_left_empty(cur)) { - INIT_PRIO_TREE_NODE(node); - cur->left = node; - node->parent = cur; - return res; - } else - cur = cur->left; - } - - mask >>= 1; - - if (!mask) { - mask = 1UL << (BITS_PER_LONG - 1); - size_flag = 1; - } - } - /* Should not reach here */ - BUG(); - return NULL; -} - -/* - * Remove a prio_tree_node @node from a radix priority search tree @root. The - * algorithm takes O(log n) time where 'log n' is the number of bits required - * to represent the maximum heap_index. - */ -static void prio_tree_remove(struct prio_tree_root *root, - struct prio_tree_node *node) -{ - struct prio_tree_node *cur; - unsigned long r_index, h_index_right, h_index_left; - - cur = node; - - while (!prio_tree_left_empty(cur) || !prio_tree_right_empty(cur)) { - if (!prio_tree_left_empty(cur)) - GET_INDEX(cur->left, r_index, h_index_left); - else { - cur = cur->right; - continue; - } - - if (!prio_tree_right_empty(cur)) - GET_INDEX(cur->right, r_index, h_index_right); - else { - cur = cur->left; - continue; - } - - /* both h_index_left and h_index_right cannot be 0 */ - if (h_index_left >= h_index_right) - cur = cur->left; - else - cur = cur->right; - } - - if (prio_tree_root(cur)) { - BUG_ON(root->prio_tree_node != cur); - INIT_PRIO_TREE_ROOT(root); - return; - } - - if (cur->parent->right == cur) - cur->parent->right = cur->parent; - else - cur->parent->left = cur->parent; - - while (cur != node) - cur = prio_tree_replace(root, cur->parent, cur); -} - -/* - * Following functions help to enumerate all prio_tree_nodes in the tree that - * overlap with the input interval X [radix_index, heap_index]. The enumeration - * takes O(log n + m) time where 'log n' is the height of the tree (which is - * proportional to # of bits required to represent the maximum heap_index) and - * 'm' is the number of prio_tree_nodes that overlap the interval X. - */ - -static struct prio_tree_node *prio_tree_left(struct prio_tree_iter *iter, - unsigned long *r_index, unsigned long *h_index) -{ - if (prio_tree_left_empty(iter->cur)) - return NULL; - - GET_INDEX(iter->cur->left, *r_index, *h_index); - - if (iter->r_index <= *h_index) { - iter->cur = iter->cur->left; - iter->mask >>= 1; - if (iter->mask) { - if (iter->size_level) - iter->size_level++; - } else { - if (iter->size_level) { - BUG_ON(!prio_tree_left_empty(iter->cur)); - BUG_ON(!prio_tree_right_empty(iter->cur)); - iter->size_level++; - iter->mask = ULONG_MAX; - } else { - iter->size_level = 1; - iter->mask = 1UL << (BITS_PER_LONG - 1); - } - } - return iter->cur; - } - - return NULL; -} - -static struct prio_tree_node *prio_tree_right(struct prio_tree_iter *iter, - unsigned long *r_index, unsigned long *h_index) -{ - unsigned long value; - - if (prio_tree_right_empty(iter->cur)) - return NULL; - - if (iter->size_level) - value = iter->value; - else - value = iter->value | iter->mask; - - if (iter->h_index < value) - return NULL; - - GET_INDEX(iter->cur->right, *r_index, *h_index); - - if (iter->r_index <= *h_index) { - iter->cur = iter->cur->right; - iter->mask >>= 1; - iter->value = value; - if (iter->mask) { - if (iter->size_level) - iter->size_level++; - } else { - if (iter->size_level) { - BUG_ON(!prio_tree_left_empty(iter->cur)); - BUG_ON(!prio_tree_right_empty(iter->cur)); - iter->size_level++; - iter->mask = ULONG_MAX; - } else { - iter->size_level = 1; - iter->mask = 1UL << (BITS_PER_LONG - 1); - } - } - return iter->cur; - } - - return NULL; -} - -static struct prio_tree_node *prio_tree_parent(struct prio_tree_iter *iter) -{ - iter->cur = iter->cur->parent; - if (iter->mask == ULONG_MAX) - iter->mask = 1UL; - else if (iter->size_level == 1) - iter->mask = 1UL; - else - iter->mask <<= 1; - if (iter->size_level) - iter->size_level--; - if (!iter->size_level && (iter->value & iter->mask)) - iter->value ^= iter->mask; - return iter->cur; -} - -static inline int overlap(struct prio_tree_iter *iter, - unsigned long r_index, unsigned long h_index) -{ - return iter->h_index >= r_index && iter->r_index <= h_index; -} - -/* - * prio_tree_first: - * - * Get the first prio_tree_node that overlaps with the interval [radix_index, - * heap_index]. Note that always radix_index <= heap_index. We do a pre-order - * traversal of the tree. - */ -static struct prio_tree_node *prio_tree_first(struct prio_tree_iter *iter) -{ - struct prio_tree_root *root; - unsigned long r_index, h_index; - - INIT_PRIO_TREE_ITER(iter); - - root = iter->root; - if (prio_tree_empty(root)) - return NULL; - - GET_INDEX(root->prio_tree_node, r_index, h_index); - - if (iter->r_index > h_index) - return NULL; - - iter->mask = 1UL << (root->index_bits - 1); - iter->cur = root->prio_tree_node; - - while (1) { - if (overlap(iter, r_index, h_index)) - return iter->cur; - - if (prio_tree_left(iter, &r_index, &h_index)) - continue; - - if (prio_tree_right(iter, &r_index, &h_index)) - continue; - - break; - } - return NULL; -} - -/* - * prio_tree_next: - * - * Get the next prio_tree_node that overlaps with the input interval in iter - */ -static struct prio_tree_node *prio_tree_next(struct prio_tree_iter *iter) -{ - unsigned long r_index, h_index; - -repeat: - while (prio_tree_left(iter, &r_index, &h_index)) - if (overlap(iter, r_index, h_index)) - return iter->cur; - - while (!prio_tree_right(iter, &r_index, &h_index)) { - while (!prio_tree_root(iter->cur) && - iter->cur->parent->right == iter->cur) - prio_tree_parent(iter); - - if (prio_tree_root(iter->cur)) - return NULL; - - prio_tree_parent(iter); - } - - if (overlap(iter, r_index, h_index)) - return iter->cur; - - goto repeat; -} +#define HEAP_INDEX(vma) ((vma)->vm_pgoff + (VMA_SIZE(vma) - 1)) /* * Radix priority search tree for address_space->i_mmap @@ -551,8 +102,8 @@ void vma_prio_tree_insert(struct vm_area_struct *vma, vma->shared.vm_set.head = NULL; - ptr = prio_tree_insert(root, &vma->shared.prio_tree_node); - if (ptr != &vma->shared.prio_tree_node) { + ptr = raw_prio_tree_insert(root, &vma->shared.prio_tree_node); + if (ptr != (struct prio_tree_node *) &vma->shared.prio_tree_node) { old = prio_tree_entry(ptr, struct vm_area_struct, shared.prio_tree_node); vma_prio_tree_add(vma, old); @@ -568,7 +119,7 @@ void vma_prio_tree_remove(struct vm_area_struct *vma, if (!vma->shared.vm_set.parent) list_del_init(&vma->shared.vm_set.list); else - prio_tree_remove(root, &vma->shared.prio_tree_node); + raw_prio_tree_remove(root, &vma->shared.prio_tree_node); } else { /* Leave this BUG_ON till prio_tree patch stabilizes */ BUG_ON(vma->shared.vm_set.head->shared.vm_set.head != vma); @@ -583,7 +134,7 @@ void vma_prio_tree_remove(struct vm_area_struct *vma, } else new_head = NULL; - prio_tree_replace(root, &vma->shared.prio_tree_node, + raw_prio_tree_replace(root, &vma->shared.prio_tree_node, &head->shared.prio_tree_node); head->shared.vm_set.head = new_head; if (new_head) @@ -620,7 +171,7 @@ struct vm_area_struct *vma_prio_tree_next(struct vm_area_struct *vma, /* * First call is with NULL vma */ - ptr = prio_tree_first(iter); + ptr = prio_tree_next(iter); if (ptr) { next = prio_tree_entry(ptr, struct vm_area_struct, shared.prio_tree_node); diff --git a/net/bluetooth/hidp/hidp.h b/net/bluetooth/hidp/hidp.h index 98a742a64..c2775f587 100644 --- a/net/bluetooth/hidp/hidp.h +++ b/net/bluetooth/hidp/hidp.h @@ -26,6 +26,51 @@ #include #include +/* HIDP header masks */ +#define HIDP_HEADER_TRANS_MASK 0xf0 +#define HIDP_HEADER_PARAM_MASK 0x0f + +/* HIDP transaction types */ +#define HIDP_TRANS_HANDSHAKE 0x00 +#define HIDP_TRANS_HID_CONTROL 0x10 +#define HIDP_TRANS_GET_REPORT 0x40 +#define HIDP_TRANS_SET_REPORT 0x50 +#define HIDP_TRANS_GET_PROTOCOL 0x60 +#define HIDP_TRANS_SET_PROTOCOL 0x70 +#define HIDP_TRANS_GET_IDLE 0x80 +#define HIDP_TRANS_SET_IDLE 0x90 +#define HIDP_TRANS_DATA 0xa0 +#define HIDP_TRANS_DATC 0xb0 + +/* HIDP handshake results */ +#define HIDP_HSHK_SUCCESSFUL 0x00 +#define HIDP_HSHK_NOT_READY 0x01 +#define HIDP_HSHK_ERR_INVALID_REPORT_ID 0x02 +#define HIDP_HSHK_ERR_UNSUPPORTED_REQUEST 0x03 +#define HIDP_HSHK_ERR_INVALID_PARAMETER 0x04 +#define HIDP_HSHK_ERR_UNKNOWN 0x0e +#define HIDP_HSHK_ERR_FATAL 0x0f + +/* HIDP control operation parameters */ +#define HIDP_CTRL_NOP 0x00 +#define HIDP_CTRL_HARD_RESET 0x01 +#define HIDP_CTRL_SOFT_RESET 0x02 +#define HIDP_CTRL_SUSPEND 0x03 +#define HIDP_CTRL_EXIT_SUSPEND 0x04 +#define HIDP_CTRL_VIRTUAL_CABLE_UNPLUG 0x05 + +/* HIDP data transaction headers */ +#define HIDP_DATA_RTYPE_MASK 0x03 +#define HIDP_DATA_RSRVD_MASK 0x0c +#define HIDP_DATA_RTYPE_OTHER 0x00 +#define HIDP_DATA_RTYPE_INPUT 0x01 +#define HIDP_DATA_RTYPE_OUPUT 0x02 +#define HIDP_DATA_RTYPE_FEATURE 0x03 + +/* HIDP protocol header parameters */ +#define HIDP_PROTO_BOOT 0x00 +#define HIDP_PROTO_REPORT 0x01 + /* HIDP ioctl defines */ #define HIDPCONNADD _IOW('H', 200, int) #define HIDPCONNDEL _IOW('H', 201, int) -- 2.45.2