X-Git-Url: http://git.onelab.eu/?p=linux-2.6.git;a=blobdiff_plain;f=arch%2Farm%2Fmach-ebsa110%2Fio.c;h=ef7eb5dc91bd9560a80251fa33ddc338b46e8710;hp=f5181ed485ed824d587a32ece29ca92f34a0c7b0;hb=f7f1b0f1e2fbadeab12d24236000e778aa9b1ead;hpb=e3f6fb6212a7102bdb56ba38fa1e98fe72950475

diff --git a/arch/arm/mach-ebsa110/io.c b/arch/arm/mach-ebsa110/io.c
index f5181ed48..ef7eb5dc9 100644
--- a/arch/arm/mach-ebsa110/io.c
+++ b/arch/arm/mach-ebsa110/io.c
@@ -153,9 +153,9 @@ u8 __inb8(unsigned int port)
 	 * The SuperIO registers use sane addressing techniques...
 	 */
 	if (SUPERIO_PORT(port))
-		ret = __raw_readb(ISAIO_BASE + (port << 2));
+		ret = __raw_readb((void __iomem *)ISAIO_BASE + (port << 2));
 	else {
-		void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
+		void __iomem *a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1);
 
 		/*
 		 * Shame nothing else does
@@ -174,45 +174,33 @@ u8 __inb8(unsigned int port)
  */
 u8 __inb16(unsigned int port)
 {
-	u32 ret;
+	unsigned int offset;
 
 	/*
 	 * The SuperIO registers use sane addressing techniques...
 	 */
 	if (SUPERIO_PORT(port))
-		ret = __raw_readb(ISAIO_BASE + (port << 2));
-	else {
-		void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
+		offset = port << 2;
+	else
+		offset = (port & ~1) << 1 | (port & 1);
 
-		/*
-		 * Shame nothing else does
-		 */
-		ret = __raw_readb(a + (port & 1));
-	}
-	return ret;
+	return __raw_readb((void __iomem *)ISAIO_BASE + offset);
 }
 
 u16 __inw(unsigned int port)
 {
-	u32 ret;
+	unsigned int offset;
 
 	/*
 	 * The SuperIO registers use sane addressing techniques...
 	 */
 	if (SUPERIO_PORT(port))
-		ret = __raw_readw(ISAIO_BASE + (port << 2));
+		offset = port << 2;
 	else {
-		void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
-
-		/*
-		 * Shame nothing else does
-		 */
-		if (port & 1)
-			BUG();
-
-		ret = __raw_readw(a);
+		offset = port << 1;
+		BUG_ON(port & 1);
 	}
-	return ret;
+	return __raw_readw((void __iomem *)ISAIO_BASE + offset);
 }
 
 /*
@@ -225,7 +213,7 @@ u32 __inl(unsigned int port)
 	if (SUPERIO_PORT(port) || port & 3)
 		BUG();
 
-	a = ISAIO_BASE + (port << 1);
+	a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1);
 
 	return __raw_readw(a) | __raw_readw(a + 4) << 16;
 }
@@ -241,9 +229,9 @@ void __outb8(u8 val, unsigned int port)
 	 * The SuperIO registers use sane addressing techniques...
 	 */
 	if (SUPERIO_PORT(port))
-		__raw_writeb(val, ISAIO_BASE + (port << 2));
+		__raw_writeb(val, (void __iomem *)ISAIO_BASE + (port << 2));
 	else {
-		void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
+		void __iomem *a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1);
 
 		/*
 		 * Shame nothing else does
@@ -257,37 +245,33 @@ void __outb8(u8 val, unsigned int port)
 
 void __outb16(u8 val, unsigned int port)
 {
+	unsigned int offset;
+
 	/*
 	 * The SuperIO registers use sane addressing techniques...
 	 */
 	if (SUPERIO_PORT(port))
-		__raw_writeb(val, ISAIO_BASE + (port << 2));
-	else {
-		void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
+		offset = port << 2;
+	else
+		offset = (port & ~1) << 1 | (port & 1);
 
-		/*
-		 * Shame nothing else does
-		 */
-		__raw_writeb(val, a + (port & 1));
-	}
+	__raw_writeb(val, (void __iomem *)ISAIO_BASE + offset);
 }
 
 void __outw(u16 val, unsigned int port)
 {
-	u32 off;
+	unsigned int offset;
 
 	/*
 	 * The SuperIO registers use sane addressing techniques...
 	 */
 	if (SUPERIO_PORT(port))
-		off = port << 2;
+		offset = port << 2;
 	else {
-		off = port << 1;
-		if (port & 1)
-			BUG();
-
+		offset = port << 1;
+		BUG_ON(port & 1);
 	}
-	__raw_writew(val, ISAIO_BASE + off);
+	__raw_writew(val, (void __iomem *)ISAIO_BASE + offset);
 }
 
 void __outl(u32 val, unsigned int port)
@@ -300,13 +284,6 @@ EXPORT_SYMBOL(__outb16);
 EXPORT_SYMBOL(__outw);
 EXPORT_SYMBOL(__outl);
 
-extern void __arch_writesb(unsigned long virt, const void *from, int len);
-extern void __arch_writesw(unsigned long virt, const void *from, int len);
-extern void __arch_writesl(unsigned long virt, const void *from, int len);
-extern void __arch_readsb(unsigned long virt, void *from, int len);
-extern void __arch_readsw(unsigned long virt, void *from, int len);
-extern void __arch_readsl(unsigned long virt, void *from, int len);
-
 void outsb(unsigned int port, const void *from, int len)
 {
 	u32 off;
@@ -319,7 +296,7 @@ void outsb(unsigned int port, const void *from, int len)
 			BUG();
 	}
 
-	__raw_writesb(ISAIO_BASE + off, from, len);
+	__raw_writesb((void __iomem *)ISAIO_BASE + off, from, len);
 }
 
 void insb(unsigned int port, void *from, int len)
@@ -334,7 +311,7 @@ void insb(unsigned int port, void *from, int len)
 			BUG();
 	}
 
-	__raw_readsb(ISAIO_BASE + off, from, len);
+	__raw_readsb((void __iomem *)ISAIO_BASE + off, from, len);
 }
 
 EXPORT_SYMBOL(outsb);
@@ -352,7 +329,7 @@ void outsw(unsigned int port, const void *from, int len)
 			BUG();
 	}
 
-	__raw_writesw(ISAIO_BASE + off, from, len);
+	__raw_writesw((void __iomem *)ISAIO_BASE + off, from, len);
 }
 
 void insw(unsigned int port, void *from, int len)
@@ -367,7 +344,7 @@ void insw(unsigned int port, void *from, int len)
 			BUG();
 	}
 
-	__raw_readsw(ISAIO_BASE + off, from, len);
+	__raw_readsw((void __iomem *)ISAIO_BASE + off, from, len);
 }
 
 EXPORT_SYMBOL(outsw);
@@ -384,7 +361,7 @@ void outsl(unsigned int port, const void *from, int len)
 	if (SUPERIO_PORT(port) || port & 3)
 		BUG();
 
-	__raw_writesw(ISAIO_BASE + off, from, len << 1);
+	__raw_writesw((void __iomem *)ISAIO_BASE + off, from, len << 1);
 }
 
 void insl(unsigned int port, void *from, int len)
@@ -394,7 +371,7 @@ void insl(unsigned int port, void *from, int len)
 	if (SUPERIO_PORT(port) || port & 3)
 		BUG();
 
-	__raw_readsw(ISAIO_BASE + off, from, len << 1);
+	__raw_readsw((void __iomem *)ISAIO_BASE + off, from, len << 1);
 }
 
 EXPORT_SYMBOL(outsl);