X-Git-Url: http://git.onelab.eu/?p=linux-2.6.git;a=blobdiff_plain;f=arch%2Fppc%2Fplatforms%2Fkatana.c;fp=arch%2Fppc%2Fplatforms%2Fkatana.c;h=ad21280e892095abd5fa6759b86bcf5cc4c03a4a;hp=eda922ac31677db6bf12f18b0766a2beceaf8dcb;hb=43bc926fffd92024b46cafaf7350d669ba9ca884;hpb=cee37fe97739d85991964371c1f3a745c00dd236 diff --git a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c index eda922ac3..ad21280e8 100644 --- a/arch/ppc/platforms/katana.c +++ b/arch/ppc/platforms/katana.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/katana.c - * * Board setup routines for the Artesyn Katana cPCI boards. * * Author: Tim Montgomery @@ -27,12 +25,14 @@ #include #include #include -#include #include #include +#include #ifdef CONFIG_BOOTIMG #include #endif +#include +#include #include #include #include @@ -41,16 +41,16 @@ #include #include #include +#include -static struct mv64x60_handle bh; -static katana_id_t katana_id; -static void __iomem *cpld_base; -static void __iomem *sram_base; - -static u32 katana_flash_size_0; -static u32 katana_flash_size_1; - -static u32 katana_bus_frequency; +static struct mv64x60_handle bh; +static katana_id_t katana_id; +static void __iomem *cpld_base; +static void __iomem *sram_base; +static u32 katana_flash_size_0; +static u32 katana_flash_size_1; +static u32 katana_bus_frequency; +static struct pci_controller katana_hose_a; unsigned char __res[sizeof(bd_t)]; @@ -71,8 +71,12 @@ katana_irq_lookup_750i(unsigned char idsel, unsigned char pin) KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i }, /* IDSEL 6 (T8110) */ {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 }, + /* IDSEL 7 (unused) */ + {0, 0, 0, 0 }, + /* IDSEL 8 (Intel 82544) (752i only but doesn't harm 750i) */ + {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 }, }; - const long min_idsel = 4, max_idsel = 6, irqs_per_slot = 4; + const long min_idsel = 4, max_idsel = 8, irqs_per_slot = 4; return PCI_IRQ_TABLE_LOOKUP; } @@ -148,7 +152,7 @@ katana_get_proc_num(void) save_exclude = mv64x60_pci_exclude_bridge; mv64x60_pci_exclude_bridge = 0; - early_read_config_word(bh.hose_a, 0, + early_read_config_word(bh.hose_b, 0, PCI_DEVFN(0,0), PCI_DEVICE_ID, &val); mv64x60_pci_exclude_bridge = save_exclude; @@ -191,7 +195,8 @@ katana_setup_bridge(void) struct mv64x60_setup_info si; void __iomem *vaddr; int i; - u16 val; + u32 v; + u16 val, type; u8 save_exclude; /* @@ -222,6 +227,20 @@ katana_setup_bridge(void) PCI_DEVICE_ID, val); } + /* + * While we're in here, set the hotswap register correctly. + * Turn off blue LED; mask ENUM#, clear insertion & extraction bits. + */ + early_read_config_dword(&hose, 0, PCI_DEVFN(0, 0), + MV64360_PCICFG_CPCI_HOTSWAP, &v); + v &= ~(1<<19); + v |= ((1<<17) | (1<<22) | (1<<23)); + early_write_config_dword(&hose, 0, PCI_DEVFN(0, 0), + MV64360_PCICFG_CPCI_HOTSWAP, v); + + /* While we're at it, grab the bridge type for later */ + early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &type); + mv64x60_pci_exclude_bridge = save_exclude; iounmap(vaddr); @@ -251,21 +270,23 @@ katana_setup_bridge(void) si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; si.pci_1.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_NONE | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; + MV64360_PCI_ACC_CNTL_SNOOP_NONE | + MV64360_PCI_ACC_CNTL_SWAP_NONE | + MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | + MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; #else si.cpu_prot_options[i] = 0; - si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */ - si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */ - si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */ + si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; + si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; + si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; si.pci_1.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_WB | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES; + MV64360_PCI_ACC_CNTL_SNOOP_WB | + MV64360_PCI_ACC_CNTL_SWAP_NONE | + MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | + ((type == PCI_DEVICE_ID_MARVELL_MV64360) ? + MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES : + MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES); #endif } @@ -281,12 +302,26 @@ katana_setup_bridge(void) mv64x60_set_bus(&bh, 1, 0); bh.hose_b->first_busno = 0; bh.hose_b->last_busno = 0xff; + + /* + * Need to access hotswap reg which is in the pci config area of the + * bridge's hose 0. Note that pcibios_alloc_controller() can't be used + * to alloc hose_a b/c that would make hose 0 known to the generic + * pci code which we don't want. + */ + bh.hose_a = &katana_hose_a; + setup_indirect_pci_nomap(bh.hose_a, + bh.v_base + MV64x60_PCI0_CONFIG_ADDR, + bh.v_base + MV64x60_PCI0_CONFIG_DATA); } /* Bridge & platform setup routines */ void __init katana_intr_setup(void) { + if (bh.type == MV64x60_TYPE_MV64460) /* As per instns from Marvell */ + mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, 1 << 15); + /* MPP 8, 9, and 10 */ mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff); @@ -309,9 +344,16 @@ katana_intr_setup(void) /* Config GPP intr ctlr to respond to level trigger */ mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10)); - /* Erranum FEr PCI-#8 */ - mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9)); - mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9)); + if (bh.type == MV64x60_TYPE_MV64360) { + /* Erratum FEr PCI-#9 */ + mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, + (1<<4) | (1<<5) | (1<<6) | (1<<7)); + mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, (1<<8) | (1<<9)); + } else { + mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<6) | (1<<7)); + mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, + (1<<4) | (1<<5) | (1<<8) | (1<<9)); + } /* * Dismiss and then enable interrupt on GPP interrupt cause @@ -473,17 +515,46 @@ katana_setup_arch(void) ppc_md.progress("katana_setup_arch: exit", 0); } +void +katana_fixup_resources(struct pci_dev *dev) +{ + u16 v16; + + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES>>2); + + pci_read_config_word(dev, PCI_COMMAND, &v16); + v16 |= PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK; + pci_write_config_word(dev, PCI_COMMAND, v16); +} + +static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */ + 0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/ + 16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /*16-31*/ +}; + +static int +katana_get_cpu_freq(void) +{ + unsigned long pll_cfg; + + pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27; + return katana_bus_frequency * cpu_750xx[pll_cfg]/2; +} + /* Platform device data fixup routines. */ #if defined(CONFIG_SERIAL_MPSC) static void __init katana_fixup_mpsc_pdata(struct platform_device *pdev) { - struct mpsc_pdata *pdata; + struct mpsc_pdata *pdata = (struct mpsc_pdata *)pdev->dev.platform_data; + bd_t *bdp = (bd_t *)__res; - pdata = (struct mpsc_pdata *)pdev->dev.platform_data; + if (bdp->bi_baudrate) + pdata->default_baud = bdp->bi_baudrate; + else + pdata->default_baud = KATANA_DEFAULT_BAUD; pdata->max_idle = 40; - pdata->default_baud = KATANA_DEFAULT_BAUD; pdata->brg_clk_src = KATANA_MPSC_CLK_SRC; /* * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts, @@ -513,7 +584,19 @@ katana_fixup_eth_pdata(struct platform_device *pdev) } #endif -static int __init +#if defined(CONFIG_SYSFS) +static void __init +katana_fixup_mv64xxx_pdata(struct platform_device *pdev) +{ + struct mv64xxx_pdata *pdata = (struct mv64xxx_pdata *) + pdev->dev.platform_data; + + /* Katana supports the mv64xxx hotswap register */ + pdata->hs_reg_valid = 1; +} +#endif + +static int katana_platform_notify(struct device *dev) { static struct { @@ -528,6 +611,9 @@ katana_platform_notify(struct device *dev) { MV643XX_ETH_NAME ".0", katana_fixup_eth_pdata }, { MV643XX_ETH_NAME ".1", katana_fixup_eth_pdata }, { MV643XX_ETH_NAME ".2", katana_fixup_eth_pdata }, +#endif +#if defined(CONFIG_SYSFS) + { MV64XXX_DEV_NAME ".0", katana_fixup_mv64xxx_pdata }, #endif }; struct platform_device *pdev; @@ -536,8 +622,7 @@ katana_platform_notify(struct device *dev) if (dev && dev->bus_id) for (i=0; ibus_id, dev_map[i].bus_id, - BUS_ID_SIZE)) { - + BUS_ID_SIZE)) { pdev = container_of(dev, struct platform_device, dev); dev_map[i].rtn(pdev); @@ -577,13 +662,11 @@ katana_setup_mtd(void) ptbl_entries = (size >= (64*MB)) ? 6 : 4; - if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition), - GFP_KERNEL)) == NULL) { - + if ((ptbl = kcalloc(ptbl_entries, sizeof(struct mtd_partition), + GFP_KERNEL)) == NULL) { printk(KERN_WARNING "Can't alloc MTD partition table\n"); return -ENOMEM; } - memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition)); ptbl[0].name = "Monitor"; ptbl[0].size = KATANA_MTD_MONITOR_SIZE; @@ -611,7 +694,6 @@ katana_setup_mtd(void) physmap_set_partitions(ptbl, ptbl_entries); return 0; } - arch_initcall(katana_setup_mtd); #endif @@ -632,7 +714,22 @@ katana_halt(void) { u8 v; - if (katana_id == KATANA_ID_752I) { + /* Turn on blue LED to indicate its okay to remove */ + if (katana_id == KATANA_ID_750I) { + u32 v; + u8 save_exclude; + + /* Set LOO bit in cPCI HotSwap reg of hose 0 to turn on LED. */ + save_exclude = mv64x60_pci_exclude_bridge; + mv64x60_pci_exclude_bridge = 0; + early_read_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0), + MV64360_PCICFG_CPCI_HOTSWAP, &v); + v &= 0xff; + v |= (1 << 19); + early_write_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0), + MV64360_PCICFG_CPCI_HOTSWAP, v); + mv64x60_pci_exclude_bridge = save_exclude; + } else if (katana_id == KATANA_ID_752I) { v = in_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF); v |= HSL_PLD_HOT_SWAP_LED_BIT; out_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF, v); @@ -652,37 +749,65 @@ katana_power_off(void) static int katana_show_cpuinfo(struct seq_file *m) { + char *s; + + seq_printf(m, "cpu freq\t: %dMHz\n", + (katana_get_cpu_freq() + 500000) / 1000000); + seq_printf(m, "bus freq\t: %ldMHz\n", + ((long)katana_bus_frequency + 500000) / 1000000); seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n"); seq_printf(m, "board\t\t: "); - switch (katana_id) { case KATANA_ID_3750: - seq_printf(m, "Katana 3750\n"); + seq_printf(m, "Katana 3750"); break; case KATANA_ID_750I: - seq_printf(m, "Katana 750i\n"); + seq_printf(m, "Katana 750i"); break; case KATANA_ID_752I: - seq_printf(m, "Katana 752i\n"); + seq_printf(m, "Katana 752i"); break; default: - seq_printf(m, "Unknown\n"); + seq_printf(m, "Unknown"); break; } - - seq_printf(m, "product ID\t: 0x%x\n", + seq_printf(m, " (product id: 0x%x)\n", in_8(cpld_base + KATANA_CPLD_PRODUCT_ID)); + + seq_printf(m, "pci mode\t: %sMonarch\n", + katana_is_monarch()? "" : "Non-"); seq_printf(m, "hardware rev\t: 0x%x\n", in_8(cpld_base+KATANA_CPLD_HARDWARE_VER)); - seq_printf(m, "PLD rev\t\t: 0x%x\n", + seq_printf(m, "pld rev\t\t: 0x%x\n", in_8(cpld_base + KATANA_CPLD_PLD_VER)); - seq_printf(m, "PLB freq\t: %ldMhz\n", - (long)katana_bus_frequency / 1000000); - seq_printf(m, "PCI\t\t: %sMonarch\n", katana_is_monarch()? "" : "Non-"); + + switch(bh.type) { + case MV64x60_TYPE_GT64260A: + s = "gt64260a"; + break; + case MV64x60_TYPE_GT64260B: + s = "gt64260b"; + break; + case MV64x60_TYPE_MV64360: + s = "mv64360"; + break; + case MV64x60_TYPE_MV64460: + s = "mv64460"; + break; + default: + s = "Unknown"; + } + seq_printf(m, "bridge type\t: %s\n", s); + seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev); +#if defined(CONFIG_NOT_COHERENT_CACHE) + seq_printf(m, "coherency\t: %s\n", "off"); +#else + seq_printf(m, "coherency\t: %s\n", "on"); +#endif return 0; } @@ -701,11 +826,20 @@ katana_calibrate_decr(void) tb_to_us = mulhwu_scale_factor(freq, 1000000); } +/* + * The katana supports both uImage and zImage. If uImage, get the mem size + * from the bd info. If zImage, the bootwrapper adds a BI_MEMSIZE entry in + * the bi_rec data which is sucked out and put into boot_mem_size by + * parse_bootinfo(). MMU_init() will then use the boot_mem_size for the mem + * size and not call this routine. The only way this will fail is when a uImage + * is used but the fw doesn't pass in a valid bi_memsize. This should never + * happen, though. + */ unsigned long __init katana_find_end_of_memory(void) { - return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, - MV64x60_TYPE_MV64360); + bd_t *bdp = (bd_t *)__res; + return bdp->bi_memsize; } #if defined(CONFIG_I2C_MV64XXX) && defined(CONFIG_SENSORS_M41T00) @@ -729,15 +863,6 @@ katana_rtc_hookup(void) late_initcall(katana_rtc_hookup); #endif -static inline void -katana_set_bat(void) -{ - mb(); - mtspr(SPRN_DBAT2U, 0xf0001ffe); - mtspr(SPRN_DBAT2L, 0xf000002a); - mb(); -} - #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) static void __init katana_map_io(void) @@ -763,15 +888,24 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, */ if (r3 && r6) { /* copy board info structure */ - memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) ); + memcpy((void *)__res, (void *)(r3+KERNELBASE), sizeof(bd_t)); /* copy command line */ *(char *)(r7+KERNELBASE) = 0; strcpy(cmd_line, (char *)(r6+KERNELBASE)); } +#ifdef CONFIG_BLK_DEV_INITRD + /* take care of initrd if we have one */ + if (r4) { + initrd_start = r4 + KERNELBASE; + initrd_end = r5 + KERNELBASE; + } +#endif /* CONFIG_BLK_DEV_INITRD */ + isa_mem_base = 0; ppc_md.setup_arch = katana_setup_arch; + ppc_md.pcibios_fixup_resources = katana_fixup_resources; ppc_md.show_cpuinfo = katana_show_cpuinfo; ppc_md.init_IRQ = mv64360_init_irq; ppc_md.get_irq = mv64360_get_irq; @@ -790,6 +924,4 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) platform_notify = katana_platform_notify; #endif - - katana_set_bat(); /* Need for katana_find_end_of_memory and progress */ }