X-Git-Url: http://git.onelab.eu/?p=linux-2.6.git;a=blobdiff_plain;f=drivers%2Fmtd%2Fnand%2Fs3c2410.c;fp=drivers%2Fmtd%2Fnand%2Fs3c2410.c;h=8b3203571eeb3e0d7afbb36bc9c8b092ff49b840;hp=5b55599739f3d3557e84bef104c209f3fc35ef8a;hb=97bf2856c6014879bd04983a3e9dfcdac1e7fe85;hpb=76828883507a47dae78837ab5dec5a5b4513c667 diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 5b5559973..8b3203571 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -18,8 +18,9 @@ * 20-Jun-2005 BJD Updated s3c2440 support, fixed timing bug * 08-Jul-2005 BJD Fix OOPS when no platform data supplied * 20-Oct-2005 BJD Fix timing calculation bug + * 14-Jan-2006 BJD Allow clock to be stopped when idle * - * $Id: s3c2410.c,v 1.20 2005/11/07 11:14:31 gleixner Exp $ + * $Id: s3c2410.c,v 1.23 2006/04/01 18:06:29 bjd Exp $ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,9 +37,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include -#include - #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG #define DEBUG #endif @@ -65,22 +63,26 @@ #include #include -#define PFX "s3c2410-nand: " - #ifdef CONFIG_MTD_NAND_S3C2410_HWECC static int hardware_ecc = 1; #else static int hardware_ecc = 0; #endif +#ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP +static int clock_stop = 1; +#else +static const int clock_stop = 0; +#endif + + /* new oob placement block for use with hardware ecc generation */ -static struct nand_oobinfo nand_hw_eccoob = { - .useecc = MTD_NANDECC_AUTOPLACE, - .eccbytes = 3, - .eccpos = {0, 1, 2 }, - .oobfree = { {8, 8} } +static struct nand_ecclayout nand_hw_eccoob = { + .eccbytes = 3, + .eccpos = {0, 1, 2}, + .oobfree = {{8, 8}} }; /* controller and mtd information */ @@ -95,6 +97,12 @@ struct s3c2410_nand_mtd { int scan_res; }; +enum s3c_cpu_type { + TYPE_S3C2410, + TYPE_S3C2412, + TYPE_S3C2440, +}; + /* overview of the s3c2410 nand state */ struct s3c2410_nand_info { @@ -108,9 +116,11 @@ struct s3c2410_nand_info { struct resource *area; struct clk *clk; void __iomem *regs; + void __iomem *sel_reg; + int sel_bit; int mtd_count; - unsigned char is_s3c2440; + enum s3c_cpu_type cpu_type; }; /* conversion functions */ @@ -135,11 +145,16 @@ static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) return dev->dev.platform_data; } +static inline int allow_clk_stop(struct s3c2410_nand_info *info) +{ + return clock_stop; +} + /* timing calculations */ #define NS_IN_KHZ 1000000 -static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max) +static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) { int result; @@ -149,8 +164,7 @@ static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max) pr_debug("result %d from %ld, %d\n", result, clk, wanted); if (result > max) { - printk("%d ns is too big for current clock rate %ld\n", - wanted, clk); + printk("%d ns is too big for current clock rate %ld\n", wanted, clk); return -1; } @@ -169,46 +183,53 @@ static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, { struct s3c2410_platform_nand *plat = to_nand_plat(pdev); unsigned long clkrate = clk_get_rate(info->clk); + int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; int tacls, twrph0, twrph1; - unsigned long cfg; + unsigned long cfg = 0; /* calculate the timing information for the controller */ clkrate /= 1000; /* turn clock into kHz for ease of use */ if (plat != NULL) { - tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 4); - twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8); - twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8); + tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); + twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); + twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); } else { /* default timings */ - tacls = 4; + tacls = tacls_max; twrph0 = 8; twrph1 = 8; } if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { - printk(KERN_ERR PFX "cannot get timings suitable for board\n"); + dev_err(info->device, "cannot get suitable timings\n"); return -EINVAL; } - printk(KERN_INFO PFX "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", - tacls, to_ns(tacls, clkrate), - twrph0, to_ns(twrph0, clkrate), - twrph1, to_ns(twrph1, clkrate)); + dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", + tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate)); - if (!info->is_s3c2440) { - cfg = S3C2410_NFCONF_EN; - cfg |= S3C2410_NFCONF_TACLS(tacls-1); - cfg |= S3C2410_NFCONF_TWRPH0(twrph0-1); - cfg |= S3C2410_NFCONF_TWRPH1(twrph1-1); - } else { - cfg = S3C2440_NFCONF_TACLS(tacls-1); - cfg |= S3C2440_NFCONF_TWRPH0(twrph0-1); - cfg |= S3C2440_NFCONF_TWRPH1(twrph1-1); + switch (info->cpu_type) { + case TYPE_S3C2410: + cfg = S3C2410_NFCONF_EN; + cfg |= S3C2410_NFCONF_TACLS(tacls - 1); + cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); + cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); + break; + + case TYPE_S3C2440: + case TYPE_S3C2412: + cfg = S3C2440_NFCONF_TACLS(tacls - 1); + cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); + cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); + + /* enable the controller and de-assert nFCE */ + + writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); } - pr_debug(PFX "NF_CONF is 0x%lx\n", cfg); + dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg); writel(cfg, info->regs + S3C2410_NFCONF); return 0; @@ -221,99 +242,71 @@ static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) struct s3c2410_nand_info *info; struct s3c2410_nand_mtd *nmtd; struct nand_chip *this = mtd->priv; - void __iomem *reg; unsigned long cur; - unsigned long bit; nmtd = this->priv; info = nmtd->info; - bit = (info->is_s3c2440) ? S3C2440_NFCONT_nFCE : S3C2410_NFCONF_nFCE; - reg = info->regs+((info->is_s3c2440) ? S3C2440_NFCONT:S3C2410_NFCONF); + if (chip != -1 && allow_clk_stop(info)) + clk_enable(info->clk); - cur = readl(reg); + cur = readl(info->sel_reg); if (chip == -1) { - cur |= bit; + cur |= info->sel_bit; } else { if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { - printk(KERN_ERR PFX "chip %d out of range\n", chip); + dev_err(info->device, "invalid chip %d\n", chip); return; } if (info->platform != NULL) { if (info->platform->select_chip != NULL) - (info->platform->select_chip)(nmtd->set, chip); + (info->platform->select_chip) (nmtd->set, chip); } - cur &= ~bit; + cur &= ~info->sel_bit; } - writel(cur, reg); + writel(cur, info->sel_reg); + + if (chip == -1 && allow_clk_stop(info)) + clk_disable(info->clk); } -/* command and control functions - * - * Note, these all use tglx's method of changing the IO_ADDR_W field - * to make the code simpler, and use the nand layer's code to issue the - * command and address sequences via the proper IO ports. +/* s3c2410_nand_hwcontrol * + * Issue command and address cycles to the chip */ -static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd) +static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, + unsigned int ctrl) { struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); - struct nand_chip *chip = mtd->priv; - switch (cmd) { - case NAND_CTL_SETNCE: - case NAND_CTL_CLRNCE: - printk(KERN_ERR "%s: called for NCE\n", __FUNCTION__); - break; - - case NAND_CTL_SETCLE: - chip->IO_ADDR_W = info->regs + S3C2410_NFCMD; - break; + if (cmd == NAND_CMD_NONE) + return; - case NAND_CTL_SETALE: - chip->IO_ADDR_W = info->regs + S3C2410_NFADDR; - break; - - /* NAND_CTL_CLRCLE: */ - /* NAND_CTL_CLRALE: */ - default: - chip->IO_ADDR_W = info->regs + S3C2410_NFDATA; - break; - } + if (ctrl & NAND_CLE) + writeb(cmd, info->regs + S3C2410_NFCMD); + else + writeb(cmd, info->regs + S3C2410_NFADDR); } /* command and control functions */ -static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd) +static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd, + unsigned int ctrl) { struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); - struct nand_chip *chip = mtd->priv; - switch (cmd) { - case NAND_CTL_SETNCE: - case NAND_CTL_CLRNCE: - printk(KERN_ERR "%s: called for NCE\n", __FUNCTION__); - break; + if (cmd == NAND_CMD_NONE) + return; - case NAND_CTL_SETCLE: - chip->IO_ADDR_W = info->regs + S3C2440_NFCMD; - break; - - case NAND_CTL_SETALE: - chip->IO_ADDR_W = info->regs + S3C2440_NFADDR; - break; - - /* NAND_CTL_CLRCLE: */ - /* NAND_CTL_CLRALE: */ - default: - chip->IO_ADDR_W = info->regs + S3C2440_NFDATA; - break; - } + if (ctrl & NAND_CLE) + writeb(cmd, info->regs + S3C2440_NFCMD); + else + writeb(cmd, info->regs + S3C2440_NFADDR); } /* s3c2410_nand_devready() @@ -324,28 +317,32 @@ static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd) static int s3c2410_nand_devready(struct mtd_info *mtd) { struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); - - if (info->is_s3c2440) - return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; } +static int s3c2440_nand_devready(struct mtd_info *mtd) +{ + struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); + return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; +} + +static int s3c2412_nand_devready(struct mtd_info *mtd) +{ + struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); + return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY; +} /* ECC handling functions */ static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) { - pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", - mtd, dat, read_ecc, calc_ecc); + pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", mtd, dat, read_ecc, calc_ecc); pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n", - read_ecc[0], read_ecc[1], read_ecc[2], - calc_ecc[0], calc_ecc[1], calc_ecc[2]); + read_ecc[0], read_ecc[1], read_ecc[2], calc_ecc[0], calc_ecc[1], calc_ecc[2]); - if (read_ecc[0] == calc_ecc[0] && - read_ecc[1] == calc_ecc[1] && - read_ecc[2] == calc_ecc[2]) + if (read_ecc[0] == calc_ecc[0] && read_ecc[1] == calc_ecc[1] && read_ecc[2] == calc_ecc[2]) return 0; /* we curently have no method for correcting the error */ @@ -378,8 +375,7 @@ static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); } -static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, - const u_char *dat, u_char *ecc_code) +static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); @@ -387,15 +383,12 @@ static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); - pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", - ecc_code[0], ecc_code[1], ecc_code[2]); + pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]); return 0; } - -static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, - const u_char *dat, u_char *ecc_code) +static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); @@ -404,13 +397,11 @@ static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, ecc_code[1] = ecc >> 8; ecc_code[2] = ecc >> 16; - pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", - ecc_code[0], ecc_code[1], ecc_code[2]); + pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]); return 0; } - /* over-ride the standard functions for a little more speed. We can * use read/write block to move the data buffers to/from the controller */ @@ -421,8 +412,7 @@ static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) readsb(this->IO_ADDR_R, buf, len); } -static void s3c2410_nand_write_buf(struct mtd_info *mtd, - const u_char *buf, int len) +static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) { struct nand_chip *this = mtd->priv; writesb(this->IO_ADDR_W, buf, len); @@ -459,7 +449,8 @@ static int s3c2410_nand_remove(struct platform_device *pdev) /* free the common resources */ if (info->clk != NULL && !IS_ERR(info->clk)) { - clk_disable(info->clk); + if (!allow_clk_stop(info)) + clk_disable(info->clk); clk_put(info->clk); } @@ -488,9 +479,7 @@ static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, return add_mtd_device(&mtd->mtd); if (set->nr_partitions > 0 && set->partitions != NULL) { - return add_mtd_partitions(&mtd->mtd, - set->partitions, - set->nr_partitions); + return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions); } return add_mtd_device(&mtd->mtd); @@ -514,11 +503,8 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, struct s3c2410_nand_set *set) { struct nand_chip *chip = &nmtd->chip; + void __iomem *regs = info->regs; - chip->IO_ADDR_R = info->regs + S3C2410_NFDATA; - chip->IO_ADDR_W = info->regs + S3C2410_NFDATA; - chip->hwcontrol = s3c2410_nand_hwcontrol; - chip->dev_ready = s3c2410_nand_devready; chip->write_buf = s3c2410_nand_write_buf; chip->read_buf = s3c2410_nand_read_buf; chip->select_chip = s3c2410_nand_select_chip; @@ -527,29 +513,66 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, chip->options = 0; chip->controller = &info->controller; - if (info->is_s3c2440) { - chip->IO_ADDR_R = info->regs + S3C2440_NFDATA; - chip->IO_ADDR_W = info->regs + S3C2440_NFDATA; - chip->hwcontrol = s3c2440_nand_hwcontrol; - } + switch (info->cpu_type) { + case TYPE_S3C2410: + chip->IO_ADDR_W = regs + S3C2410_NFDATA; + info->sel_reg = regs + S3C2410_NFCONF; + info->sel_bit = S3C2410_NFCONF_nFCE; + chip->cmd_ctrl = s3c2410_nand_hwcontrol; + chip->dev_ready = s3c2410_nand_devready; + break; + + case TYPE_S3C2440: + chip->IO_ADDR_W = regs + S3C2440_NFDATA; + info->sel_reg = regs + S3C2440_NFCONT; + info->sel_bit = S3C2440_NFCONT_nFCE; + chip->cmd_ctrl = s3c2440_nand_hwcontrol; + chip->dev_ready = s3c2440_nand_devready; + break; + + case TYPE_S3C2412: + chip->IO_ADDR_W = regs + S3C2440_NFDATA; + info->sel_reg = regs + S3C2440_NFCONT; + info->sel_bit = S3C2412_NFCONT_nFCE0; + chip->cmd_ctrl = s3c2440_nand_hwcontrol; + chip->dev_ready = s3c2412_nand_devready; + + if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) + dev_info(info->device, "System booted from NAND\n"); + + break; + } + + chip->IO_ADDR_R = chip->IO_ADDR_W; nmtd->info = info; nmtd->mtd.priv = chip; + nmtd->mtd.owner = THIS_MODULE; nmtd->set = set; if (hardware_ecc) { - chip->correct_data = s3c2410_nand_correct_data; - chip->enable_hwecc = s3c2410_nand_enable_hwecc; - chip->calculate_ecc = s3c2410_nand_calculate_ecc; - chip->eccmode = NAND_ECC_HW3_512; - chip->autooob = &nand_hw_eccoob; - - if (info->is_s3c2440) { - chip->enable_hwecc = s3c2440_nand_enable_hwecc; - chip->calculate_ecc = s3c2440_nand_calculate_ecc; + chip->ecc.calculate = s3c2410_nand_calculate_ecc; + chip->ecc.correct = s3c2410_nand_correct_data; + chip->ecc.mode = NAND_ECC_HW; + chip->ecc.size = 512; + chip->ecc.bytes = 3; + chip->ecc.layout = &nand_hw_eccoob; + + switch (info->cpu_type) { + case TYPE_S3C2410: + chip->ecc.hwctl = s3c2410_nand_enable_hwecc; + chip->ecc.calculate = s3c2410_nand_calculate_ecc; + break; + + case TYPE_S3C2412: + case TYPE_S3C2440: + chip->ecc.hwctl = s3c2440_nand_enable_hwecc; + chip->ecc.calculate = s3c2440_nand_calculate_ecc; + break; + } } else { - chip->eccmode = NAND_ECC_SOFT; + chip->ecc.mode = NAND_ECC_SOFT; } } @@ -561,7 +584,8 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, * nand layer to look for devices */ -static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440) +static int s3c24xx_nand_probe(struct platform_device *pdev, + enum s3c_cpu_type cpu_type) { struct s3c2410_platform_nand *plat = to_nand_plat(pdev); struct s3c2410_nand_info *info; @@ -616,7 +640,7 @@ static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440) info->device = &pdev->dev; info->platform = plat; info->regs = ioremap(res->start, size); - info->is_s3c2440 = is_s3c2440; + info->cpu_type = cpu_type; if (info->regs == NULL) { dev_err(&pdev->dev, "cannot reserve register region\n"); @@ -654,13 +678,11 @@ static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440) nmtd = info->mtds; for (setno = 0; setno < nr_sets; setno++, nmtd++) { - pr_debug("initialising set %d (%p, info %p)\n", - setno, nmtd, info); + pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info); s3c2410_nand_init_chip(info, nmtd, sets); - nmtd->scan_res = nand_scan(&nmtd->mtd, - (sets) ? sets->nr_chips : 1); + nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1); if (nmtd->scan_res == 0) { s3c2410_nand_add_partition(info, nmtd, sets); @@ -670,6 +692,11 @@ static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440) sets++; } + if (allow_clk_stop(info)) { + dev_info(&pdev->dev, "clock idle support enabled\n"); + clk_disable(info->clk); + } + pr_debug("initialised ok\n"); return 0; @@ -681,21 +708,63 @@ static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440) return err; } +/* PM Support */ +#ifdef CONFIG_PM + +static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm) +{ + struct s3c2410_nand_info *info = platform_get_drvdata(dev); + + if (info) { + if (!allow_clk_stop(info)) + clk_disable(info->clk); + } + + return 0; +} + +static int s3c24xx_nand_resume(struct platform_device *dev) +{ + struct s3c2410_nand_info *info = platform_get_drvdata(dev); + + if (info) { + clk_enable(info->clk); + s3c2410_nand_inithw(info, dev); + + if (allow_clk_stop(info)) + clk_disable(info->clk); + } + + return 0; +} + +#else +#define s3c24xx_nand_suspend NULL +#define s3c24xx_nand_resume NULL +#endif + /* driver device registration */ static int s3c2410_nand_probe(struct platform_device *dev) { - return s3c24xx_nand_probe(dev, 0); + return s3c24xx_nand_probe(dev, TYPE_S3C2410); } static int s3c2440_nand_probe(struct platform_device *dev) { - return s3c24xx_nand_probe(dev, 1); + return s3c24xx_nand_probe(dev, TYPE_S3C2440); +} + +static int s3c2412_nand_probe(struct platform_device *dev) +{ + return s3c24xx_nand_probe(dev, TYPE_S3C2412); } static struct platform_driver s3c2410_nand_driver = { .probe = s3c2410_nand_probe, .remove = s3c2410_nand_remove, + .suspend = s3c24xx_nand_suspend, + .resume = s3c24xx_nand_resume, .driver = { .name = "s3c2410-nand", .owner = THIS_MODULE, @@ -705,22 +774,37 @@ static struct platform_driver s3c2410_nand_driver = { static struct platform_driver s3c2440_nand_driver = { .probe = s3c2440_nand_probe, .remove = s3c2410_nand_remove, + .suspend = s3c24xx_nand_suspend, + .resume = s3c24xx_nand_resume, .driver = { .name = "s3c2440-nand", .owner = THIS_MODULE, }, }; +static struct platform_driver s3c2412_nand_driver = { + .probe = s3c2412_nand_probe, + .remove = s3c2410_nand_remove, + .suspend = s3c24xx_nand_suspend, + .resume = s3c24xx_nand_resume, + .driver = { + .name = "s3c2412-nand", + .owner = THIS_MODULE, + }, +}; + static int __init s3c2410_nand_init(void) { printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n"); + platform_driver_register(&s3c2412_nand_driver); platform_driver_register(&s3c2440_nand_driver); return platform_driver_register(&s3c2410_nand_driver); } static void __exit s3c2410_nand_exit(void) { + platform_driver_unregister(&s3c2412_nand_driver); platform_driver_unregister(&s3c2440_nand_driver); platform_driver_unregister(&s3c2410_nand_driver); }