1 <!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook V3.1//EN"[]>
3 <book id="MTD-NAND-Guide">
5 <title>MTD NAND Driver Programming Interface</title>
9 <firstname>Thomas</firstname>
10 <surname>Gleixner</surname>
13 <email>tglx@linutronix.de</email>
21 <holder>Thomas Gleixner</holder>
26 This documentation is free software; you can redistribute
27 it and/or modify it under the terms of the GNU General Public
28 License version 2 as published by the Free Software Foundation.
32 This program is distributed in the hope that it will be
33 useful, but WITHOUT ANY WARRANTY; without even the implied
34 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
35 See the GNU General Public License for more details.
39 You should have received a copy of the GNU General Public
40 License along with this program; if not, write to the Free
41 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
46 For more details see the file COPYING in the source
47 distribution of Linux.
55 <title>Introduction</title>
57 The generic NAND driver supports almost all NAND and AG-AND based
58 chips and connects them to the Memory Technology Devices (MTD)
59 subsystem of the Linux Kernel.
62 This documentation is provided for developers who want to implement
63 board drivers or filesystem drivers suitable for NAND devices.
68 <title>Known Bugs And Assumptions</title>
74 <chapter id="dochints">
75 <title>Documentation hints</title>
77 The function and structure docs are autogenerated. Each function and
78 struct member has a short description which is marked with an [XXX] identifier.
79 The following chapters explain the meaning of those identifiers.
82 <title>Function identifiers [XXX]</title>
84 The functions are marked with [XXX] identifiers in the short
85 comment. The identifiers explain the usage and scope of the
86 functions. Following identifiers are used:
90 [MTD Interface]</para><para>
91 These functions provide the interface to the MTD kernel API.
92 They are not replacable and provide functionality
93 which is complete hardware independent.
96 [NAND Interface]</para><para>
97 These functions are exported and provide the interface to the NAND kernel API.
100 [GENERIC]</para><para>
101 Generic functions are not replacable and provide functionality
102 which is complete hardware independent.
105 [DEFAULT]</para><para>
106 Default functions provide hardware related functionality which is suitable
107 for most of the implementations. These functions can be replaced by the
108 board driver if neccecary. Those functions are called via pointers in the
109 NAND chip description structure. The board driver can set the functions which
110 should be replaced by board dependend functions before calling nand_scan().
111 If the function pointer is NULL on entry to nand_scan() then the pointer
112 is set to the default function which is suitable for the detected chip type.
117 <title>Struct member identifiers [XXX]</title>
119 The struct members are marked with [XXX] identifiers in the
120 comment. The identifiers explain the usage and scope of the
121 members. Following identifiers are used:
125 [INTERN]</para><para>
126 These members are for NAND driver internal use only and must not be
127 modified. Most of these values are calculated from the chip geometry
128 information which is evaluated during nand_scan().
131 [REPLACEABLE]</para><para>
132 Replaceable members hold hardware related functions which can be
133 provided by the board driver. The board driver can set the functions which
134 should be replaced by board dependend functions before calling nand_scan().
135 If the function pointer is NULL on entry to nand_scan() then the pointer
136 is set to the default function which is suitable for the detected chip type.
139 [BOARDSPECIFIC]</para><para>
140 Board specific members hold hardware related information which must
141 be provided by the board driver. The board driver must set the function
142 pointers and datafields before calling nand_scan().
145 [OPTIONAL]</para><para>
146 Optional members can hold information relevant for the board driver. The
147 generic NAND driver code does not use this information.
153 <chapter id="basicboarddriver">
154 <title>Basic board driver</title>
156 For most boards it will be sufficient to provide just the
157 basic functions and fill out some really board dependend
158 members in the nand chip description structure.
159 See drivers/mtd/nand/skeleton for reference.
162 <title>Basic defines</title>
164 At least you have to provide a mtd structure and
165 a storage for the ioremap'ed chip address.
166 You can allocate the mtd structure using kmalloc
167 or you can allocate it statically.
168 In case of static allocation you have to allocate
169 a nand_chip structure too.
172 Kmalloc based example
175 static struct mtd_info *board_mtd;
176 static unsigned long baseaddr;
182 static struct mtd_info board_mtd;
183 static struct nand_chip board_chip;
184 static unsigned long baseaddr;
188 <title>Partition defines</title>
190 If you want to divide your device into parititions, then
191 enable the configuration switch CONFIG_MTD_PARITIONS and define
192 a paritioning scheme suitable to your board.
195 #define NUM_PARTITIONS 2
196 static struct mtd_partition partition_info[] = {
197 { .name = "Flash partition 1",
199 .size = 8 * 1024 * 1024 },
200 { .name = "Flash partition 2",
201 .offset = MTDPART_OFS_NEXT,
202 .size = MTDPART_SIZ_FULL },
207 <title>Hardware control function</title>
209 The hardware control function provides access to the
210 control pins of the NAND chip(s).
211 The access can be done by GPIO pins or by address lines.
212 If you use address lines, make sure that the timing
213 requirements are met.
216 <emphasis>GPIO based example</emphasis>
219 static void board_hwcontrol(struct mtd_info *mtd, int cmd)
222 case NAND_CTL_SETCLE: /* Set CLE pin high */ break;
223 case NAND_CTL_CLRCLE: /* Set CLE pin low */ break;
224 case NAND_CTL_SETALE: /* Set ALE pin high */ break;
225 case NAND_CTL_CLRALE: /* Set ALE pin low */ break;
226 case NAND_CTL_SETNCE: /* Set nCE pin low */ break;
227 case NAND_CTL_CLRNCE: /* Set nCE pin high */ break;
232 <emphasis>Address lines based example.</emphasis> It's assumed that the
233 nCE pin is driven by a chip select decoder.
236 static void board_hwcontrol(struct mtd_info *mtd, int cmd)
238 struct nand_chip *this = (struct nand_chip *) mtd->priv;
240 case NAND_CTL_SETCLE: this->IO_ADDR_W |= CLE_ADRR_BIT; break;
241 case NAND_CTL_CLRCLE: this->IO_ADDR_W &= ~CLE_ADRR_BIT; break;
242 case NAND_CTL_SETALE: this->IO_ADDR_W |= ALE_ADRR_BIT; break;
243 case NAND_CTL_CLRALE: this->IO_ADDR_W &= ~ALE_ADRR_BIT; break;
249 <title>Device ready function</title>
251 If the hardware interface has the ready busy pin of the NAND chip connected to a
252 GPIO or other accesible I/O pin, this function is used to read back the state of the
253 pin. The function has no arguments and should return 0, if the device is busy (R/B pin
254 is low) and 1, if the device is ready (R/B pin is high).
255 If the hardware interface does not give access to the ready busy pin, then
256 the function must not be defined and the function pointer this->dev_ready is set to NULL.
260 <title>Init function</title>
262 The init function allocates memory and sets up all the board
263 specific parameters and function pointers. When everything
264 is set up nand_scan() is called. This function tries to
265 detect and identify then chip. If a chip is found all the
266 internal data fields are initialized accordingly.
267 The structure(s) have to be zeroed out first and then filled with the neccecary
268 information about the device.
271 int __init board_init (void)
273 struct nand_chip *this;
276 /* Allocate memory for MTD device structure and private data */
277 board_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip), GFP_KERNEL);
279 printk ("Unable to allocate NAND MTD device structure.\n");
284 /* Initialize structures */
285 memset ((char *) board_mtd, 0, sizeof(struct mtd_info) + sizeof(struct nand_chip));
287 /* map physical adress */
288 baseaddr = (unsigned long)ioremap(CHIP_PHYSICAL_ADDRESS, 1024);
290 printk("Ioremap to access NAND chip failed\n");
295 /* Get pointer to private data */
296 this = (struct nand_chip *) ();
297 /* Link the private data with the MTD structure */
298 board_mtd->priv = this;
300 /* Set address of NAND IO lines */
301 this->IO_ADDR_R = baseaddr;
302 this->IO_ADDR_W = baseaddr;
303 /* Reference hardware control function */
304 this->hwcontrol = board_hwcontrol;
305 /* Set command delay time, see datasheet for correct value */
306 this->chip_delay = CHIP_DEPENDEND_COMMAND_DELAY;
307 /* Assign the device ready function, if available */
308 this->dev_ready = board_dev_ready;
309 this->eccmode = NAND_ECC_SOFT;
311 /* Scan to find existance of the device */
312 if (nand_scan (board_mtd, 1)) {
317 add_mtd_partitions(board_mtd, partition_info, NUM_PARTITIONS);
321 iounmap((void *)baseaddr);
327 module_init(board_init);
331 <title>Exit function</title>
333 The exit function is only neccecary if the driver is
334 compiled as a module. It releases all resources which
335 are held by the chip driver and unregisters the partitions
340 static void __exit board_cleanup (void)
342 /* Release resources, unregister device */
343 nand_release (board_mtd);
345 /* unmap physical adress */
346 iounmap((void *)baseaddr);
348 /* Free the MTD device structure */
351 module_exit(board_cleanup);
357 <chapter id="boarddriversadvanced">
358 <title>Advanced board driver functions</title>
360 This chapter describes the advanced functionality of the NAND
361 driver. For a list of functions which can be overridden by the board
362 driver see the documentation of the nand_chip structure.
365 <title>Multiple chip control</title>
367 The nand driver can control chip arrays. Therefor the
368 board driver must provide an own select_chip function. This
369 function must (de)select the requested chip.
370 The function pointer in the nand_chip structure must
371 be set before calling nand_scan(). The maxchip parameter
372 of nand_scan() defines the maximum number of chips to
373 scan for. Make sure that the select_chip function can
374 handle the requested number of chips.
377 The nand driver concatenates the chips to one virtual
378 chip and provides this virtual chip to the MTD layer.
381 <emphasis>Note: The driver can only handle linear chip arrays
382 of equally sized chips. There is no support for
383 parallel arrays which extend the buswidth.</emphasis>
386 <emphasis>GPIO based example</emphasis>
389 static void board_select_chip (struct mtd_info *mtd, int chip)
391 /* Deselect all chips, set all nCE pins high */
392 GPIO(BOARD_NAND_NCE) |= 0xff;
394 GPIO(BOARD_NAND_NCE) &= ~ (1 << chip);
398 <emphasis>Address lines based example.</emphasis>
399 Its assumed that the nCE pins are connected to an
403 static void board_select_chip (struct mtd_info *mtd, int chip)
405 struct nand_chip *this = (struct nand_chip *) mtd->priv;
407 /* Deselect all chips */
408 this->IO_ADDR_R &= ~BOARD_NAND_ADDR_MASK;
409 this->IO_ADDR_W &= ~BOARD_NAND_ADDR_MASK;
412 this->IO_ADDR_R |= BOARD_NAND_ADDR_CHIP0;
413 this->IO_ADDR_W |= BOARD_NAND_ADDR_CHIP0;
417 this->IO_ADDR_R |= BOARD_NAND_ADDR_CHIPn;
418 this->IO_ADDR_W |= BOARD_NAND_ADDR_CHIPn;
425 <title>Hardware ECC support</title>
427 <title>Functions and constants</title>
429 The nand driver supports three different types of
432 <listitem><para>NAND_ECC_HW3_256</para><para>
433 Hardware ECC generator providing 3 bytes ECC per
436 <listitem><para>NAND_ECC_HW3_512</para><para>
437 Hardware ECC generator providing 3 bytes ECC per
440 <listitem><para>NAND_ECC_HW6_512</para><para>
441 Hardware ECC generator providing 6 bytes ECC per
444 <listitem><para>NAND_ECC_HW8_512</para><para>
445 Hardware ECC generator providing 6 bytes ECC per
449 If your hardware generator has a different functionality
450 add it at the appropriate place in nand_base.c
453 The board driver must provide following functions:
455 <listitem><para>enable_hwecc</para><para>
456 This function is called before reading / writing to
457 the chip. Reset or initialize the hardware generator
458 in this function. The function is called with an
459 argument which let you distinguish between read
460 and write operations.
462 <listitem><para>calculate_ecc</para><para>
463 This function is called after read / write from / to
464 the chip. Transfer the ECC from the hardware to
465 the buffer. If the option NAND_HWECC_SYNDROME is set
466 then the function is only called on write. See below.
468 <listitem><para>correct_data</para><para>
469 In case of an ECC error this function is called for
470 error detection and correction. Return 1 respectively 2
471 in case the error can be corrected. If the error is
472 not correctable return -1. If your hardware generator
473 matches the default algorithm of the nand_ecc software
474 generator then use the correction function provided
475 by nand_ecc instead of implementing duplicated code.
481 <title>Hardware ECC with syndrome calculation</title>
483 Many hardware ECC implementations provide Reed-Solomon
484 codes and calculate an error syndrome on read. The syndrome
485 must be converted to a standard Reed-Solomon syndrome
486 before calling the error correction code in the generic
487 Reed-Solomon library.
490 The ECC bytes must be placed immidiately after the data
491 bytes in order to make the syndrome generator work. This
492 is contrary to the usual layout used by software ECC. The
493 seperation of data and out of band area is not longer
494 possible. The nand driver code handles this layout and
495 the remaining free bytes in the oob area are managed by
496 the autoplacement code. Provide a matching oob-layout
497 in this case. See rts_from4.c and diskonchip.c for
498 implementation reference. In those cases we must also
499 use bad block tables on FLASH, because the ECC layout is
500 interferring with the bad block marker positions.
501 See bad block table support for details.
506 <title>Bad block table support</title>
508 Most NAND chips mark the bad blocks at a defined
509 position in the spare area. Those blocks must
510 not be erased under any circumstances as the bad
511 block information would be lost.
512 It is possible to check the bad block mark each
513 time when the blocks are accessed by reading the
514 spare area of the first page in the block. This
515 is time consuming so a bad block table is used.
518 The nand driver supports various types of bad block
521 <listitem><para>Per device</para><para>
522 The bad block table contains all bad block information
523 of the device which can consist of multiple chips.
525 <listitem><para>Per chip</para><para>
526 A bad block table is used per chip and contains the
527 bad block information for this particular chip.
529 <listitem><para>Fixed offset</para><para>
530 The bad block table is located at a fixed offset
531 in the chip (device). This applies to various
534 <listitem><para>Automatic placed</para><para>
535 The bad block table is automatically placed and
536 detected either at the end or at the beginning
539 <listitem><para>Mirrored tables</para><para>
540 The bad block table is mirrored on the chip (device) to
541 allow updates of the bad block table without data loss.
546 nand_scan() calls the function nand_default_bbt().
547 nand_default_bbt() selects appropriate default
548 bad block table desriptors depending on the chip information
549 which was retrieved by nand_scan().
552 The standard policy is scanning the device for bad
553 blocks and build a ram based bad block table which
554 allows faster access than always checking the
555 bad block information on the flash chip itself.
558 <title>Flash based tables</title>
560 It may be desired or neccecary to keep a bad block table in FLASH.
561 For AG-AND chips this is mandatory, as they have no factory marked
562 bad blocks. They have factory marked good blocks. The marker pattern
563 is erased when the block is erased to be reused. So in case of
564 powerloss before writing the pattern back to the chip this block
565 would be lost and added to the bad blocks. Therefor we scan the
566 chip(s) when we detect them the first time for good blocks and
567 store this information in a bad block table before erasing any
571 The blocks in which the tables are stored are procteted against
572 accidental access by marking them bad in the memory bad block
573 table. The bad block table managment functions are allowed
574 to circumvernt this protection.
577 The simplest way to activate the FLASH based bad block table support
578 is to set the option NAND_USE_FLASH_BBT in the option field of
579 the nand chip structure before calling nand_scan(). For AG-AND
580 chips is this done by default.
581 This activates the default FLASH based bad block table functionality
582 of the NAND driver. The default bad block table options are
584 <listitem><para>Store bad block table per chip</para></listitem>
585 <listitem><para>Use 2 bits per block</para></listitem>
586 <listitem><para>Automatic placement at the end of the chip</para></listitem>
587 <listitem><para>Use mirrored tables with version numbers</para></listitem>
588 <listitem><para>Reserve 4 blocks at the end of the chip</para></listitem>
593 <title>User defined tables</title>
595 User defined tables are created by filling out a
596 nand_bbt_descr structure and storing the pointer in the
597 nand_chip structure member bbt_td before calling nand_scan().
598 If a mirror table is neccecary a second structure must be
599 created and a pointer to this structure must be stored
600 in bbt_md inside the nand_chip structure. If the bbt_md
601 member is set to NULL then only the main table is used
602 and no scan for the mirrored table is performed.
605 The most important field in the nand_bbt_descr structure
606 is the options field. The options define most of the
607 table properties. Use the predefined constants from
608 nand.h to define the options.
610 <listitem><para>Number of bits per block</para>
611 <para>The supported number of bits is 1, 2, 4, 8.</para></listitem>
612 <listitem><para>Table per chip</para>
613 <para>Setting the constant NAND_BBT_PERCHIP selects that
614 a bad block table is managed for each chip in a chip array.
615 If this option is not set then a per device bad block table
616 is used.</para></listitem>
617 <listitem><para>Table location is absolute</para>
618 <para>Use the option constant NAND_BBT_ABSPAGE and
619 define the absolute page number where the bad block
620 table starts in the field pages. If you have selected bad block
621 tables per chip and you have a multi chip array then the start page
622 must be given for each chip in the chip array. Note: there is no scan
623 for a table ident pattern performed, so the fields
624 pattern, veroffs, offs, len can be left uninitialized</para></listitem>
625 <listitem><para>Table location is automatically detected</para>
626 <para>The table can either be located in the first or the last good
627 blocks of the chip (device). Set NAND_BBT_LASTBLOCK to place
628 the bad block table at the end of the chip (device). The
629 bad block tables are marked and identified by a pattern which
630 is stored in the spare area of the first page in the block which
631 holds the bad block table. Store a pointer to the pattern
632 in the pattern field. Further the length of the pattern has to be
633 stored in len and the offset in the spare area must be given
634 in the offs member of the nand_bbt_descr stucture. For mirrored
635 bad block tables different patterns are mandatory.</para></listitem>
636 <listitem><para>Table creation</para>
637 <para>Set the option NAND_BBT_CREATE to enable the table creation
638 if no table can be found during the scan. Usually this is done only
639 once if a new chip is found. </para></listitem>
640 <listitem><para>Table write support</para>
641 <para>Set the option NAND_BBT_WRITE to enable the table write support.
642 This allows the update of the bad block table(s) in case a block has
643 to be marked bad due to wear. The MTD interface function block_markbad
644 is calling the update function of the bad block table. If the write
645 support is enabled then the table is updated on FLASH.</para>
647 Note: Write support should only be enabled for mirrored tables with
650 <listitem><para>Table version control</para>
651 <para>Set the option NAND_BBT_VERSION to enable the table version control.
652 It's highly recommended to enable this for mirrored tables with write
653 support. It makes sure that the risk of loosing the bad block
654 table information is reduced to the loss of the information about the
655 one worn out block which should be marked bad. The version is stored in
656 4 consecutive bytes in the spare area of the device. The position of
657 the version number is defined by the member veroffs in the bad block table
658 descriptor.</para></listitem>
659 <listitem><para>Save block contents on write</para>
661 In case that the block which holds the bad block table does contain
662 other useful information, set the option NAND_BBT_SAVECONTENT. When
663 the bad block table is written then the whole block is read the bad
664 block table is updated and the block is erased and everything is
665 written back. If this option is not set only the bad block table
666 is written and everything else in the block is ignored and erased.
668 <listitem><para>Number of reserved blocks</para>
670 For automatic placement some blocks must be reserved for
671 bad block table storage. The number of reserved blocks is defined
672 in the maxblocks member of the babd block table description structure.
673 Reserving 4 blocks for mirrored tables should be a reasonable number.
674 This also limits the number of blocks which are scanned for the bad
675 block table ident pattern.
682 <title>Spare area (auto)placement</title>
684 The nand driver implements different possibilities for
685 placement of filesystem data in the spare area,
687 <listitem><para>Placement defined by fs driver</para></listitem>
688 <listitem><para>Automatic placement</para></listitem>
690 The default placement function is automatic placement. The
691 nand driver has built in default placement schemes for the
692 various chiptypes. If due to hardware ECC functionality the
693 default placement does not fit then the board driver can
694 provide a own placement scheme.
697 File system drivers can provide a own placement scheme which
698 is used instead of the default placement scheme.
701 Placement schemes are defined by a nand_oobinfo structure
703 struct nand_oobinfo {
711 <listitem><para>useecc</para><para>
712 The useecc member controls the ecc and placement function. The header
713 file include/mtd/mtd-abi.h contains constants to select ecc and
714 placement. MTD_NANDECC_OFF switches off the ecc complete. This is
715 not recommended and available for testing and diagnosis only.
716 MTD_NANDECC_PLACE selects caller defined placement, MTD_NANDECC_AUTOPLACE
717 selects automatic placement.
719 <listitem><para>eccbytes</para><para>
720 The eccbytes member defines the number of ecc bytes per page.
722 <listitem><para>eccpos</para><para>
723 The eccpos array holds the byte offsets in the spare area where
724 the ecc codes are placed.
726 <listitem><para>oobfree</para><para>
727 The oobfree array defines the areas in the spare area which can be
728 used for automatic placement. The information is given in the format
729 {offset, size}. offset defines the start of the usable area, size the
730 length in bytes. More than one area can be defined. The list is terminated
736 <title>Placement defined by fs driver</title>
738 The calling function provides a pointer to a nand_oobinfo
739 structure which defines the ecc placement. For writes the
740 caller must provide a spare area buffer along with the
741 data buffer. The spare area buffer size is (number of pages) *
742 (size of spare area). For reads the buffer size is
743 (number of pages) * ((size of spare area) + (number of ecc
744 steps per page) * sizeof (int)). The driver stores the
745 result of the ecc check for each tuple in the spare buffer.
746 The storage sequence is
749 <spare data page 0><ecc result 0>...<ecc result n>
755 <spare data page n><ecc result 0>...<ecc result n>
758 This is a legacy mode used by YAFFS1.
761 If the spare area buffer is NULL then only the ECC placement is
762 done according to the given scheme in the nand_oobinfo structure.
766 <title>Automatic placement</title>
768 Automatic placement uses the built in defaults to place the
769 ecc bytes in the spare area. If filesystem data have to be stored /
770 read into the spare area then the calling function must provide a
771 buffer. The buffer size per page is determined by the oobfree array in
772 the nand_oobinfo structure.
775 If the spare area buffer is NULL then only the ECC placement is
776 done according to the default builtin scheme.
780 <title>User space placement selection</title>
782 All non ecc functions like mtd->read and mtd->write use an internal
783 structure, which can be set by an ioctl. This structure is preset
784 to the autoplacement default.
786 ioctl (fd, MEMSETOOBSEL, oobsel);
788 oobsel is a pointer to a user supplied structure of type
789 nand_oobconfig. The contents of this structure must match the
790 criteria of the filesystem, which will be used. See an example in utils/nandwrite.c.
795 <title>Spare area autoplacement default schemes</title>
797 <title>256 byte pagesize</title>
798 <informaltable><tgroup cols="3"><tbody>
800 <entry>Offset</entry>
801 <entry>Content</entry>
802 <entry>Comment</entry>
806 <entry>ECC byte 0</entry>
807 <entry>Error correction code byte 0</entry>
811 <entry>ECC byte 1</entry>
812 <entry>Error correction code byte 1</entry>
816 <entry>ECC byte 2</entry>
817 <entry>Error correction code byte 2</entry>
821 <entry>Autoplace 0</entry>
826 <entry>Autoplace 1</entry>
831 <entry>Bad block marker</entry>
832 <entry>If any bit in this byte is zero, then this block is bad.
833 This applies only to the first page in a block. In the remaining
834 pages this byte is reserved</entry>
838 <entry>Autoplace 2</entry>
843 <entry>Autoplace 3</entry>
846 </tbody></tgroup></informaltable>
849 <title>512 byte pagesize</title>
850 <informaltable><tgroup cols="3"><tbody>
852 <entry>Offset</entry>
853 <entry>Content</entry>
854 <entry>Comment</entry>
858 <entry>ECC byte 0</entry>
859 <entry>Error correction code byte 0 of the lower 256 Byte data in
864 <entry>ECC byte 1</entry>
865 <entry>Error correction code byte 1 of the lower 256 Bytes of data
870 <entry>ECC byte 2</entry>
871 <entry>Error correction code byte 2 of the lower 256 Bytes of data
876 <entry>ECC byte 3</entry>
877 <entry>Error correction code byte 0 of the upper 256 Bytes of data
882 <entry>reserved</entry>
883 <entry>reserved</entry>
887 <entry>Bad block marker</entry>
888 <entry>If any bit in this byte is zero, then this block is bad.
889 This applies only to the first page in a block. In the remaining
890 pages this byte is reserved</entry>
894 <entry>ECC byte 4</entry>
895 <entry>Error correction code byte 1 of the upper 256 Bytes of data
900 <entry>ECC byte 5</entry>
901 <entry>Error correction code byte 2 of the upper 256 Bytes of data
905 <entry>0x08 - 0x0F</entry>
906 <entry>Autoplace 0 - 7</entry>
909 </tbody></tgroup></informaltable>
912 <title>2048 byte pagesize</title>
913 <informaltable><tgroup cols="3"><tbody>
915 <entry>Offset</entry>
916 <entry>Content</entry>
917 <entry>Comment</entry>
921 <entry>Bad block marker</entry>
922 <entry>If any bit in this byte is zero, then this block is bad.
923 This applies only to the first page in a block. In the remaining
924 pages this byte is reserved</entry>
928 <entry>Reserved</entry>
929 <entry>Reserved</entry>
932 <entry>0x02-0x27</entry>
933 <entry>Autoplace 0 - 37</entry>
938 <entry>ECC byte 0</entry>
939 <entry>Error correction code byte 0 of the first 256 Byte data in
944 <entry>ECC byte 1</entry>
945 <entry>Error correction code byte 1 of the first 256 Bytes of data
950 <entry>ECC byte 2</entry>
951 <entry>Error correction code byte 2 of the first 256 Bytes data in
956 <entry>ECC byte 3</entry>
957 <entry>Error correction code byte 0 of the second 256 Bytes of data
962 <entry>ECC byte 4</entry>
963 <entry>Error correction code byte 1 of the second 256 Bytes of data
968 <entry>ECC byte 5</entry>
969 <entry>Error correction code byte 2 of the second 256 Bytes of data
974 <entry>ECC byte 6</entry>
975 <entry>Error correction code byte 0 of the third 256 Bytes of data
980 <entry>ECC byte 7</entry>
981 <entry>Error correction code byte 1 of the third 256 Bytes of data
986 <entry>ECC byte 8</entry>
987 <entry>Error correction code byte 2 of the third 256 Bytes of data
992 <entry>ECC byte 9</entry>
993 <entry>Error correction code byte 0 of the fourth 256 Bytes of data
998 <entry>ECC byte 10</entry>
999 <entry>Error correction code byte 1 of the fourth 256 Bytes of data
1000 in this page</entry>
1004 <entry>ECC byte 11</entry>
1005 <entry>Error correction code byte 2 of the fourth 256 Bytes of data
1006 in this page</entry>
1010 <entry>ECC byte 12</entry>
1011 <entry>Error correction code byte 0 of the fifth 256 Bytes of data
1012 in this page</entry>
1016 <entry>ECC byte 13</entry>
1017 <entry>Error correction code byte 1 of the fifth 256 Bytes of data
1018 in this page</entry>
1022 <entry>ECC byte 14</entry>
1023 <entry>Error correction code byte 2 of the fifth 256 Bytes of data
1024 in this page</entry>
1028 <entry>ECC byte 15</entry>
1029 <entry>Error correction code byte 0 of the sixt 256 Bytes of data
1030 in this page</entry>
1034 <entry>ECC byte 16</entry>
1035 <entry>Error correction code byte 1 of the sixt 256 Bytes of data
1036 in this page</entry>
1040 <entry>ECC byte 17</entry>
1041 <entry>Error correction code byte 2 of the sixt 256 Bytes of data
1042 in this page</entry>
1046 <entry>ECC byte 18</entry>
1047 <entry>Error correction code byte 0 of the seventh 256 Bytes of
1048 data in this page</entry>
1052 <entry>ECC byte 19</entry>
1053 <entry>Error correction code byte 1 of the seventh 256 Bytes of
1054 data in this page</entry>
1058 <entry>ECC byte 20</entry>
1059 <entry>Error correction code byte 2 of the seventh 256 Bytes of
1060 data in this page</entry>
1064 <entry>ECC byte 21</entry>
1065 <entry>Error correction code byte 0 of the eigth 256 Bytes of data
1066 in this page</entry>
1070 <entry>ECC byte 22</entry>
1071 <entry>Error correction code byte 1 of the eigth 256 Bytes of data
1072 in this page</entry>
1076 <entry>ECC byte 23</entry>
1077 <entry>Error correction code byte 2 of the eigth 256 Bytes of data
1078 in this page</entry>
1080 </tbody></tgroup></informaltable>
1085 <chapter id="filesystems">
1086 <title>Filesystem support</title>
1088 The NAND driver provides all neccecary functions for a
1089 filesystem via the MTD interface.
1092 Filesystems must be aware of the NAND pecularities and
1093 restrictions. One major restrictions of NAND Flash is, that you cannot
1094 write as often as you want to a page. The consecutive writes to a page,
1095 before erasing it again, are restricted to 1-3 writes, depending on the
1096 manufacturers specifications. This applies similar to the spare area.
1099 Therefor NAND aware filesystems must either write in page size chunks
1100 or hold a writebuffer to collect smaller writes until they sum up to
1101 pagesize. Available NAND aware filesystems: JFFS2, YAFFS.
1104 The spare area usage to store filesystem data is controlled by
1105 the spare area placement functionality which is described in one
1106 of the earlier chapters.
1109 <chapter id="tools">
1110 <title>Tools</title>
1112 The MTD project provides a couple of helpful tools to handle NAND Flash.
1114 <listitem><para>flasherase, flasheraseall: Erase and format FLASH partitions</para></listitem>
1115 <listitem><para>nandwrite: write filesystem images to NAND FLASH</para></listitem>
1116 <listitem><para>nanddump: dump the contents of a NAND FLASH partitions</para></listitem>
1120 These tools are aware of the NAND restrictions. Please use those tools
1121 instead of complaining about errors which are caused by non NAND aware
1126 <chapter id="defines">
1127 <title>Constants</title>
1129 This chapter describes the constants which might be relevant for a driver developer.
1132 <title>Chip option constants</title>
1134 <title>Constants for chip id table</title>
1136 These constants are defined in nand.h. They are ored together to describe
1137 the chip functionality.
1139 /* Chip can not auto increment pages */
1140 #define NAND_NO_AUTOINCR 0x00000001
1141 /* Buswitdh is 16 bit */
1142 #define NAND_BUSWIDTH_16 0x00000002
1143 /* Device supports partial programming without padding */
1144 #define NAND_NO_PADDING 0x00000004
1145 /* Chip has cache program function */
1146 #define NAND_CACHEPRG 0x00000008
1147 /* Chip has copy back function */
1148 #define NAND_COPYBACK 0x00000010
1149 /* AND Chip which has 4 banks and a confusing page / block
1150 * assignment. See Renesas datasheet for further information */
1151 #define NAND_IS_AND 0x00000020
1152 /* Chip has a array of 4 pages which can be read without
1153 * additional ready /busy waits */
1154 #define NAND_4PAGE_ARRAY 0x00000040
1159 <title>Constants for runtime options</title>
1161 These constants are defined in nand.h. They are ored together to describe
1164 /* Use a flash based bad block table. This option is parsed by the
1165 * default bad block table function (nand_default_bbt). */
1166 #define NAND_USE_FLASH_BBT 0x00010000
1167 /* The hw ecc generator provides a syndrome instead a ecc value on read
1168 * This can only work if we have the ecc bytes directly behind the
1169 * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
1170 #define NAND_HWECC_SYNDROME 0x00020000
1177 <title>ECC selection constants</title>
1179 Use these constants to select the ECC algorithm.
1181 /* No ECC. Usage is not recommended ! */
1182 #define NAND_ECC_NONE 0
1183 /* Software ECC 3 byte ECC per 256 Byte data */
1184 #define NAND_ECC_SOFT 1
1185 /* Hardware ECC 3 byte ECC per 256 Byte data */
1186 #define NAND_ECC_HW3_256 2
1187 /* Hardware ECC 3 byte ECC per 512 Byte data */
1188 #define NAND_ECC_HW3_512 3
1189 /* Hardware ECC 6 byte ECC per 512 Byte data */
1190 #define NAND_ECC_HW6_512 4
1191 /* Hardware ECC 6 byte ECC per 512 Byte data */
1192 #define NAND_ECC_HW8_512 6
1198 <title>Hardware control related constants</title>
1200 These constants describe the requested hardware access function when
1201 the boardspecific hardware control function is called
1203 /* Select the chip by setting nCE to low */
1204 #define NAND_CTL_SETNCE 1
1205 /* Deselect the chip by setting nCE to high */
1206 #define NAND_CTL_CLRNCE 2
1207 /* Select the command latch by setting CLE to high */
1208 #define NAND_CTL_SETCLE 3
1209 /* Deselect the command latch by setting CLE to low */
1210 #define NAND_CTL_CLRCLE 4
1211 /* Select the address latch by setting ALE to high */
1212 #define NAND_CTL_SETALE 5
1213 /* Deselect the address latch by setting ALE to low */
1214 #define NAND_CTL_CLRALE 6
1215 /* Set write protection by setting WP to high. Not used! */
1216 #define NAND_CTL_SETWP 7
1217 /* Clear write protection by setting WP to low. Not used! */
1218 #define NAND_CTL_CLRWP 8
1224 <title>Bad block table related constants</title>
1226 These constants describe the options used for bad block
1229 /* Options for the bad block table descriptors */
1231 /* The number of bits used per block in the bbt on the device */
1232 #define NAND_BBT_NRBITS_MSK 0x0000000F
1233 #define NAND_BBT_1BIT 0x00000001
1234 #define NAND_BBT_2BIT 0x00000002
1235 #define NAND_BBT_4BIT 0x00000004
1236 #define NAND_BBT_8BIT 0x00000008
1237 /* The bad block table is in the last good block of the device */
1238 #define NAND_BBT_LASTBLOCK 0x00000010
1239 /* The bbt is at the given page, else we must scan for the bbt */
1240 #define NAND_BBT_ABSPAGE 0x00000020
1241 /* The bbt is at the given page, else we must scan for the bbt */
1242 #define NAND_BBT_SEARCH 0x00000040
1243 /* bbt is stored per chip on multichip devices */
1244 #define NAND_BBT_PERCHIP 0x00000080
1245 /* bbt has a version counter at offset veroffs */
1246 #define NAND_BBT_VERSION 0x00000100
1247 /* Create a bbt if none axists */
1248 #define NAND_BBT_CREATE 0x00000200
1249 /* Search good / bad pattern through all pages of a block */
1250 #define NAND_BBT_SCANALLPAGES 0x00000400
1251 /* Scan block empty during good / bad block scan */
1252 #define NAND_BBT_SCANEMPTY 0x00000800
1253 /* Write bbt if neccecary */
1254 #define NAND_BBT_WRITE 0x00001000
1255 /* Read and write back block contents when writing bbt */
1256 #define NAND_BBT_SAVECONTENT 0x00002000
1263 <chapter id="structs">
1264 <title>Structures</title>
1266 This chapter contains the autogenerated documentation of the structures which are
1267 used in the NAND driver and might be relevant for a driver developer. Each
1268 struct member has a short description which is marked with an [XXX] identifier.
1269 See the chapter "Documentation hints" for an explanation.
1271 !Iinclude/linux/mtd/nand.h
1274 <chapter id="pubfunctions">
1275 <title>Public Functions Provided</title>
1277 This chapter contains the autogenerated documentation of the NAND kernel API functions
1278 which are exported. Each function has a short description which is marked with an [XXX] identifier.
1279 See the chapter "Documentation hints" for an explanation.
1281 !Edrivers/mtd/nand/nand_base.c
1282 !Edrivers/mtd/nand/nand_bbt.c
1283 !Edrivers/mtd/nand/nand_ecc.c
1286 <chapter id="intfunctions">
1287 <title>Internal Functions Provided</title>
1289 This chapter contains the autogenerated documentation of the NAND driver internal functions.
1290 Each function has a short description which is marked with an [XXX] identifier.
1291 See the chapter "Documentation hints" for an explanation.
1292 The functions marked with [DEFAULT] might be relevant for a board driver developer.
1294 !Idrivers/mtd/nand/nand_base.c
1295 !Idrivers/mtd/nand/nand_bbt.c
1296 !Idrivers/mtd/nand/nand_ecc.c
1299 <chapter id="credits">
1300 <title>Credits</title>
1302 The following people have contributed to the NAND driver:
1304 <listitem><para>Steven J. Hill<email>sjhill@realitydiluted.com</email></para></listitem>
1305 <listitem><para>David Woodhouse<email>dwmw2@infradead.org</email></para></listitem>
1306 <listitem><para>Thomas Gleixner<email>tglx@linutronix.de</email></para></listitem>
1308 A lot of users have provided bugfixes, improvements and helping hands for testing.
1312 The following people have contributed to this document:
1314 <listitem><para>Thomas Gleixner<email>tglx@linutronix.de</email></para></listitem>