2 Intel's XScale Microarchitecture provides support for locking of TLB
3 entries in both the instruction and data TLBs. This file provides
4 an overview of the API that has been developed to take advantage of this
5 feature from kernel space. Note that there is NO support for user space.
7 In general, this feature should be used in conjunction with locking
8 data or instructions into the appropriate caches. See the file
9 cache-lock.txt in this directory.
11 If you have any questions, comments, patches, etc, please contact me.
13 Deepak Saxena <dsaxena@mvista.com>
20 #include <asm/xscale-lock.h>
22 II. Locking an entry into the TLB
26 xscale_tlb_lock(u8 tlb_type, u32 addr);
36 This function locks the virtual to physical mapping for virtual
37 address addr into the requested TLB.
41 If the entry is properly locked into the TLB, a 0 is returned.
42 In case of an error, an appropriate error is returned.
44 -ENOSPC No more entries left in the TLB
47 III. Unlocking an entry from a TLB
51 xscale_tlb_unlock(u8 tlb_type, u32 addr);
55 This function unlocks the entry for virtual address addr from the
60 If the TLB entry is properly unlocked, a 0 is returned.
61 In case of an error, an appropriate error is returned.
63 -ENOENT No entry for given address in specified TLB