2 * linux/arch/alpha/kernel/pci.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
9 /* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * PCI-PCI bridges cleanup
15 #include <linux/config.h>
16 #include <linux/string.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/kernel.h>
21 #include <linux/bootmem.h>
22 #include <linux/module.h>
23 #include <linux/cache.h>
24 #include <linux/slab.h>
25 #include <asm/machvec.h>
32 * Some string constants used by the various core logics.
35 const char *const pci_io_names[] = {
36 "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
37 "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
40 const char *const pci_mem_names[] = {
41 "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
42 "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
45 const char pci_hae0_name[] = "HAE0";
47 /* Indicate whether we respect the PCI setup left by console. */
49 * Make this long-lived so that we know when shutting down
50 * whether we probed only or not.
55 * The PCI controller list.
58 struct pci_controller *hose_head, **hose_tail = &hose_head;
59 struct pci_controller *pci_isa_hose;
66 quirk_isa_bridge(struct pci_dev *dev)
68 dev->class = PCI_CLASS_BRIDGE_ISA << 8;
70 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
73 quirk_cypress(struct pci_dev *dev)
75 /* The Notorious Cy82C693 chip. */
77 /* The Cypress IDE controller doesn't support native mode, but it
78 has programmable addresses of IDE command/control registers.
79 This violates PCI specifications, confuses the IDE subsystem and
80 causes resource conflicts between the primary HD_CMD register and
81 the floppy controller. Ugh. Fix that. */
82 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
83 dev->resource[0].flags = 0;
84 dev->resource[1].flags = 0;
87 /* The Cypress bridge responds on the PCI bus in the address range
88 0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no
89 way to turn this off. The bridge also supports several extended
90 BIOS ranges (disabled after power-up), and some consoles do turn
91 them on. So if we use a large direct-map window, or a large SG
92 window, we must avoid the entire 0xfff00000-0xffffffff region. */
93 else if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
94 if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
95 __direct_map_size = 0xfff00000UL - __direct_map_base;
97 struct pci_controller *hose = dev->sysdata;
98 struct pci_iommu_arena *pci = hose->sg_pci;
99 if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
100 pci->size = 0xfff00000UL - pci->dma_base;
104 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
106 /* Called for each device after PCI setup is done. */
108 pcibios_fixup_final(struct pci_dev *dev)
110 unsigned int class = dev->class >> 8;
112 if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
113 dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
117 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
119 /* Just declaring that the power-of-ten prefixes are actually the
120 power-of-two ones doesn't make it true :) */
126 pcibios_align_resource(void *data, struct resource *res,
127 unsigned long size, unsigned long align)
129 struct pci_dev *dev = data;
130 struct pci_controller *hose = dev->sysdata;
131 unsigned long alignto;
132 unsigned long start = res->start;
134 if (res->flags & IORESOURCE_IO) {
135 /* Make sure we start at our min on all hoses */
136 if (start - hose->io_space->start < PCIBIOS_MIN_IO)
137 start = PCIBIOS_MIN_IO + hose->io_space->start;
140 * Put everything into 0x00-0xff region modulo 0x400
143 start = (start + 0x3ff) & ~0x3ff;
145 else if (res->flags & IORESOURCE_MEM) {
146 /* Make sure we start at our min on all hoses */
147 if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
148 start = PCIBIOS_MIN_MEM + hose->mem_space->start;
151 * The following holds at least for the Low Cost
152 * Alpha implementation of the PCI interface:
154 * In sparse memory address space, the first
155 * octant (16MB) of every 128MB segment is
156 * aliased to the very first 16 MB of the
157 * address space (i.e., it aliases the ISA
158 * memory address space). Thus, we try to
159 * avoid allocating PCI devices in that range.
160 * Can be allocated in 2nd-7th octant only.
161 * Devices that need more than 112MB of
162 * address space must be accessed through
163 * dense memory space only!
166 /* Align to multiple of size of minimum base. */
167 alignto = max(0x1000UL, align);
168 start = ALIGN(start, alignto);
169 if (hose->sparse_mem_base && size <= 7 * 16*MB) {
170 if (((start / (16*MB)) & 0x7) == 0) {
171 start &= ~(128*MB - 1);
173 start = ALIGN(start, alignto);
175 if (start/(128*MB) != (start + size - 1)/(128*MB)) {
176 start &= ~(128*MB - 1);
177 start += (128 + 16)*MB;
178 start = ALIGN(start, alignto);
192 if (alpha_mv.init_pci)
197 subsys_initcall(pcibios_init);
200 pcibios_setup(char *str)
205 #ifdef ALPHA_RESTORE_SRM_SETUP
206 static struct pdev_srm_saved_conf *srm_saved_configs;
209 pdev_save_srm_config(struct pci_dev *dev)
211 struct pdev_srm_saved_conf *tmp;
212 static int printed = 0;
214 if (!alpha_using_srm || pci_probe_only)
218 printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
222 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
224 printk(KERN_ERR "%s: kmalloc() failed!\n", __FUNCTION__);
227 tmp->next = srm_saved_configs;
230 pci_save_state(dev, tmp->regs);
232 srm_saved_configs = tmp;
236 pci_restore_srm_config(void)
238 struct pdev_srm_saved_conf *tmp;
240 /* No need to restore if probed only. */
244 /* Restore SRM config. */
245 for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
246 pci_restore_state(tmp->dev, tmp->regs);
252 pcibios_fixup_resource(struct resource *res, struct resource *root)
254 res->start += root->start;
255 res->end += root->start;
259 pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus)
261 /* Update device resources. */
262 struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
265 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
266 if (!dev->resource[i].start)
268 if (dev->resource[i].flags & IORESOURCE_IO)
269 pcibios_fixup_resource(&dev->resource[i],
271 else if (dev->resource[i].flags & IORESOURCE_MEM)
272 pcibios_fixup_resource(&dev->resource[i],
278 pcibios_fixup_bus(struct pci_bus *bus)
280 /* Propagate hose info into the subordinate devices. */
282 struct pci_controller *hose = bus->sysdata;
283 struct list_head *ln;
284 struct pci_dev *dev = bus->self;
289 u32 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
292 bus->resource[0] = hose->io_space;
293 bus->resource[1] = hose->mem_space;
295 /* Adjust hose mem_space limit to prevent PCI allocations
296 in the iommu windows. */
297 pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
298 end = hose->mem_space->start + pci_mem_end;
299 if (hose->mem_space->end > end)
300 hose->mem_space->end = end;
301 } else if (pci_probe_only &&
302 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
303 pci_read_bridge_bases(bus);
304 pcibios_fixup_device_resources(dev, bus);
307 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
308 struct pci_dev *dev = pci_dev_b(ln);
310 pdev_save_srm_config(dev);
311 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
312 pcibios_fixup_device_resources(dev, bus);
317 pcibios_update_irq(struct pci_dev *dev, int irq)
319 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
322 /* Most Alphas have straight-forward swizzling needs. */
325 common_swizzle(struct pci_dev *dev, u8 *pinp)
329 while (dev->bus->parent) {
330 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
331 /* Move up the chain of bridges. */
332 dev = dev->bus->self;
336 /* The slot is the slot of the last bridge. */
337 return PCI_SLOT(dev->devfn);
341 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
342 struct resource *res)
344 struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
345 unsigned long offset = 0;
347 if (res->flags & IORESOURCE_IO)
348 offset = hose->io_space->start;
349 else if (res->flags & IORESOURCE_MEM)
350 offset = hose->mem_space->start;
352 region->start = res->start - offset;
353 region->end = res->end - offset;
356 #ifdef CONFIG_HOTPLUG
357 EXPORT_SYMBOL(pcibios_resource_to_bus);
361 pcibios_enable_device(struct pci_dev *dev, int mask)
366 pci_read_config_word(dev, PCI_COMMAND, &cmd);
369 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
370 struct resource *res = &dev->resource[i];
372 if (res->flags & IORESOURCE_IO)
373 cmd |= PCI_COMMAND_IO;
374 else if (res->flags & IORESOURCE_MEM)
375 cmd |= PCI_COMMAND_MEMORY;
379 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
381 /* Enable the appropriate bits in the PCI command register. */
382 pci_write_config_word(dev, PCI_COMMAND, cmd);
388 * If we set up a device for bus mastering, we need to check the latency
389 * timer as certain firmware forgets to set it properly, as seen
390 * on SX164 and LX164 with SRM.
393 pcibios_set_master(struct pci_dev *dev)
396 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
397 if (lat >= 16) return;
398 printk("PCI: Setting latency timer of device %s to 64\n",
400 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
404 pcibios_claim_one_bus(struct pci_bus *b)
406 struct list_head *ld;
407 struct pci_bus *child_bus;
409 for (ld = b->devices.next; ld != &b->devices; ld = ld->next) {
410 struct pci_dev *dev = pci_dev_b(ld);
413 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
414 struct resource *r = &dev->resource[i];
416 if (r->parent || !r->start || !r->flags)
418 pci_claim_resource(dev, i);
422 list_for_each_entry(child_bus, &b->children, node)
423 pcibios_claim_one_bus(child_bus);
427 pcibios_claim_console_setup(void)
429 struct list_head *lb;
431 for(lb = pci_root_buses.next; lb != &pci_root_buses; lb = lb->next) {
432 struct pci_bus *b = pci_bus_b(lb);
433 pcibios_claim_one_bus(b);
438 common_init_pci(void)
440 struct pci_controller *hose;
443 int need_domain_info = 0;
445 /* Scan all of the recorded PCI controllers. */
446 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
447 bus = pci_scan_bus(next_busno, alpha_mv.pci_ops, hose);
449 hose->need_domain_info = need_domain_info;
450 next_busno = bus->subordinate + 1;
451 /* Don't allow 8-bit bus number overflow inside the hose -
452 reserve some space for bridges. */
453 if (next_busno > 224) {
455 need_domain_info = 1;
460 pcibios_claim_console_setup();
462 pci_assign_unassigned_resources();
463 pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
467 struct pci_controller * __init
468 alloc_pci_controller(void)
470 struct pci_controller *hose;
472 hose = alloc_bootmem(sizeof(*hose));
475 hose_tail = &hose->next;
480 struct resource * __init
483 struct resource *res;
485 res = alloc_bootmem(sizeof(*res));
491 /* Provide information on locations of various I/O regions in physical
492 memory. Do this on a per-card basis so that we choose the right hose. */
495 sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
497 struct pci_controller *hose;
500 /* from hose or from bus.devfn */
501 if (which & IOBASE_FROM_HOSE) {
502 for(hose = hose_head; hose; hose = hose->next)
503 if (hose->index == bus) break;
504 if (!hose) return -ENODEV;
506 /* Special hook for ISA access. */
507 if (bus == 0 && dfn == 0) {
510 dev = pci_find_slot(bus, dfn);
517 switch (which & ~IOBASE_FROM_HOSE) {
520 case IOBASE_SPARSE_MEM:
521 return hose->sparse_mem_base;
522 case IOBASE_DENSE_MEM:
523 return hose->dense_mem_base;
524 case IOBASE_SPARSE_IO:
525 return hose->sparse_io_base;
526 case IOBASE_DENSE_IO:
527 return hose->dense_io_base;
528 case IOBASE_ROOT_BUS:
529 return hose->bus->number;
535 /* Create an __iomem token from a PCI BAR. Copied from lib/iomap.c with
536 no changes, since we don't want the other things in that object file. */
538 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
540 unsigned long start = pci_resource_start(dev, bar);
541 unsigned long len = pci_resource_len(dev, bar);
542 unsigned long flags = pci_resource_flags(dev, bar);
546 if (maxlen && len > maxlen)
548 if (flags & IORESOURCE_IO)
549 return ioport_map(start, len);
550 if (flags & IORESOURCE_MEM) {
551 /* Not checking IORESOURCE_CACHEABLE because alpha does
552 not distinguish between ioremap and ioremap_nocache. */
553 return ioremap(start, len);
558 /* Destroy that token. Not copied from lib/iomap.c. */
560 void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
566 EXPORT_SYMBOL(pci_iomap);
567 EXPORT_SYMBOL(pci_iounmap);