2 * linux/arch/alpha/kernel/pci.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
9 /* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * PCI-PCI bridges cleanup
15 #include <linux/config.h>
16 #include <linux/string.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/kernel.h>
21 #include <linux/bootmem.h>
22 #include <linux/module.h>
23 #include <linux/cache.h>
24 #include <linux/slab.h>
25 #include <asm/machvec.h>
32 * Some string constants used by the various core logics.
35 const char *const pci_io_names[] = {
36 "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
37 "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
40 const char *const pci_mem_names[] = {
41 "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
42 "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
45 const char pci_hae0_name[] = "HAE0";
47 /* Indicate whether we respect the PCI setup left by console. */
49 * Make this long-lived so that we know when shutting down
50 * whether we probed only or not.
55 * The PCI controller list.
58 struct pci_controller *hose_head, **hose_tail = &hose_head;
59 struct pci_controller *pci_isa_hose;
66 quirk_isa_bridge(struct pci_dev *dev)
68 dev->class = PCI_CLASS_BRIDGE_ISA << 8;
72 quirk_cypress(struct pci_dev *dev)
74 /* The Notorious Cy82C693 chip. */
76 /* The Cypress IDE controller doesn't support native mode, but it
77 has programmable addresses of IDE command/control registers.
78 This violates PCI specifications, confuses the IDE subsystem and
79 causes resource conflicts between the primary HD_CMD register and
80 the floppy controller. Ugh. Fix that. */
81 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
82 dev->resource[0].flags = 0;
83 dev->resource[1].flags = 0;
86 /* The Cypress bridge responds on the PCI bus in the address range
87 0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no
88 way to turn this off. The bridge also supports several extended
89 BIOS ranges (disabled after power-up), and some consoles do turn
90 them on. So if we use a large direct-map window, or a large SG
91 window, we must avoid the entire 0xfff00000-0xffffffff region. */
92 else if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
93 if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
94 __direct_map_size = 0xfff00000UL - __direct_map_base;
96 struct pci_controller *hose = dev->sysdata;
97 struct pci_iommu_arena *pci = hose->sg_pci;
98 if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
99 pci->size = 0xfff00000UL - pci->dma_base;
104 /* Called for each device after PCI setup is done. */
106 pcibios_fixup_final(struct pci_dev *dev)
108 unsigned int class = dev->class >> 8;
110 if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
111 dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
116 struct pci_fixup pcibios_fixups[] __initdata = {
117 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378,
119 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693,
121 { PCI_FIXUP_FINAL, PCI_ANY_ID, PCI_ANY_ID,
122 pcibios_fixup_final },
131 pcibios_align_resource(void *data, struct resource *res,
132 unsigned long size, unsigned long align)
134 struct pci_dev *dev = data;
135 struct pci_controller *hose = dev->sysdata;
136 unsigned long alignto;
137 unsigned long start = res->start;
139 if (res->flags & IORESOURCE_IO) {
140 /* Make sure we start at our min on all hoses */
141 if (start - hose->io_space->start < PCIBIOS_MIN_IO)
142 start = PCIBIOS_MIN_IO + hose->io_space->start;
145 * Put everything into 0x00-0xff region modulo 0x400
148 start = (start + 0x3ff) & ~0x3ff;
150 else if (res->flags & IORESOURCE_MEM) {
151 /* Make sure we start at our min on all hoses */
152 if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
153 start = PCIBIOS_MIN_MEM + hose->mem_space->start;
156 * The following holds at least for the Low Cost
157 * Alpha implementation of the PCI interface:
159 * In sparse memory address space, the first
160 * octant (16MB) of every 128MB segment is
161 * aliased to the very first 16 MB of the
162 * address space (i.e., it aliases the ISA
163 * memory address space). Thus, we try to
164 * avoid allocating PCI devices in that range.
165 * Can be allocated in 2nd-7th octant only.
166 * Devices that need more than 112MB of
167 * address space must be accessed through
168 * dense memory space only!
171 /* Align to multiple of size of minimum base. */
172 alignto = max(0x1000UL, align);
173 start = ALIGN(start, alignto);
174 if (hose->sparse_mem_base && size <= 7 * 16*MB) {
175 if (((start / (16*MB)) & 0x7) == 0) {
176 start &= ~(128*MB - 1);
178 start = ALIGN(start, alignto);
180 if (start/(128*MB) != (start + size - 1)/(128*MB)) {
181 start &= ~(128*MB - 1);
182 start += (128 + 16)*MB;
183 start = ALIGN(start, alignto);
197 if (alpha_mv.init_pci)
202 subsys_initcall(pcibios_init);
205 pcibios_setup(char *str)
210 #ifdef ALPHA_RESTORE_SRM_SETUP
211 static struct pdev_srm_saved_conf *srm_saved_configs;
214 pdev_save_srm_config(struct pci_dev *dev)
216 struct pdev_srm_saved_conf *tmp;
217 static int printed = 0;
219 if (!alpha_using_srm || pci_probe_only)
223 printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
227 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
229 printk(KERN_ERR "%s: kmalloc() failed!\n", __FUNCTION__);
232 tmp->next = srm_saved_configs;
235 pci_save_state(dev, tmp->regs);
237 srm_saved_configs = tmp;
241 pci_restore_srm_config(void)
243 struct pdev_srm_saved_conf *tmp;
245 /* No need to restore if probed only. */
249 /* Restore SRM config. */
250 for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
251 pci_restore_state(tmp->dev, tmp->regs);
257 pcibios_fixup_resource(struct resource *res, struct resource *root)
259 res->start += root->start;
260 res->end += root->start;
264 pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus)
266 /* Update device resources. */
267 struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
270 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
271 if (!dev->resource[i].start)
273 if (dev->resource[i].flags & IORESOURCE_IO)
274 pcibios_fixup_resource(&dev->resource[i],
276 else if (dev->resource[i].flags & IORESOURCE_MEM)
277 pcibios_fixup_resource(&dev->resource[i],
283 pcibios_fixup_bus(struct pci_bus *bus)
285 /* Propagate hose info into the subordinate devices. */
287 struct pci_controller *hose = bus->sysdata;
288 struct list_head *ln;
289 struct pci_dev *dev = bus->self;
294 u32 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
297 bus->resource[0] = hose->io_space;
298 bus->resource[1] = hose->mem_space;
300 /* Adjust hose mem_space limit to prevent PCI allocations
301 in the iommu windows. */
302 pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
303 end = hose->mem_space->start + pci_mem_end;
304 if (hose->mem_space->end > end)
305 hose->mem_space->end = end;
306 } else if (pci_probe_only &&
307 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
308 pci_read_bridge_bases(bus);
309 pcibios_fixup_device_resources(dev, bus);
312 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
313 struct pci_dev *dev = pci_dev_b(ln);
315 pdev_save_srm_config(dev);
316 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
317 pcibios_fixup_device_resources(dev, bus);
322 pcibios_update_irq(struct pci_dev *dev, int irq)
324 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
327 /* Most Alphas have straight-forward swizzling needs. */
330 common_swizzle(struct pci_dev *dev, u8 *pinp)
334 while (dev->bus->parent) {
335 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
336 /* Move up the chain of bridges. */
337 dev = dev->bus->self;
341 /* The slot is the slot of the last bridge. */
342 return PCI_SLOT(dev->devfn);
346 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
347 struct resource *res)
349 struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
350 unsigned long offset = 0;
352 if (res->flags & IORESOURCE_IO)
353 offset = hose->io_space->start;
354 else if (res->flags & IORESOURCE_MEM)
355 offset = hose->mem_space->start;
357 region->start = res->start - offset;
358 region->end = res->end - offset;
361 #ifdef CONFIG_HOTPLUG
362 EXPORT_SYMBOL(pcibios_resource_to_bus);
366 pcibios_enable_device(struct pci_dev *dev, int mask)
371 pci_read_config_word(dev, PCI_COMMAND, &cmd);
374 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
375 struct resource *res = &dev->resource[i];
377 if (res->flags & IORESOURCE_IO)
378 cmd |= PCI_COMMAND_IO;
379 else if (res->flags & IORESOURCE_MEM)
380 cmd |= PCI_COMMAND_MEMORY;
384 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
386 /* Enable the appropriate bits in the PCI command register. */
387 pci_write_config_word(dev, PCI_COMMAND, cmd);
393 * If we set up a device for bus mastering, we need to check the latency
394 * timer as certain firmware forgets to set it properly, as seen
395 * on SX164 and LX164 with SRM.
398 pcibios_set_master(struct pci_dev *dev)
401 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
402 if (lat >= 16) return;
403 printk("PCI: Setting latency timer of device %s to 64\n",
405 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
409 pcibios_claim_one_bus(struct pci_bus *b)
411 struct list_head *ld;
412 struct pci_bus *child_bus;
414 for (ld = b->devices.next; ld != &b->devices; ld = ld->next) {
415 struct pci_dev *dev = pci_dev_b(ld);
418 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
419 struct resource *r = &dev->resource[i];
421 if (r->parent || !r->start || !r->flags)
423 pci_claim_resource(dev, i);
427 list_for_each_entry(child_bus, &b->children, node)
428 pcibios_claim_one_bus(child_bus);
432 pcibios_claim_console_setup(void)
434 struct list_head *lb;
436 for(lb = pci_root_buses.next; lb != &pci_root_buses; lb = lb->next) {
437 struct pci_bus *b = pci_bus_b(lb);
438 pcibios_claim_one_bus(b);
443 common_init_pci(void)
445 struct pci_controller *hose;
448 int need_domain_info = 0;
450 /* Scan all of the recorded PCI controllers. */
451 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
452 bus = pci_scan_bus(next_busno, alpha_mv.pci_ops, hose);
454 hose->need_domain_info = need_domain_info;
455 next_busno = bus->subordinate + 1;
456 /* Don't allow 8-bit bus number overflow inside the hose -
457 reserve some space for bridges. */
458 if (next_busno > 224) {
460 need_domain_info = 1;
465 pcibios_claim_console_setup();
467 pci_assign_unassigned_resources();
468 pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
472 struct pci_controller * __init
473 alloc_pci_controller(void)
475 struct pci_controller *hose;
477 hose = alloc_bootmem(sizeof(*hose));
480 hose_tail = &hose->next;
485 struct resource * __init
488 struct resource *res;
490 res = alloc_bootmem(sizeof(*res));
496 /* Provide information on locations of various I/O regions in physical
497 memory. Do this on a per-card basis so that we choose the right hose. */
500 sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
502 struct pci_controller *hose;
505 /* from hose or from bus.devfn */
506 if (which & IOBASE_FROM_HOSE) {
507 for(hose = hose_head; hose; hose = hose->next)
508 if (hose->index == bus) break;
509 if (!hose) return -ENODEV;
511 /* Special hook for ISA access. */
512 if (bus == 0 && dfn == 0) {
515 dev = pci_find_slot(bus, dfn);
522 switch (which & ~IOBASE_FROM_HOSE) {
525 case IOBASE_SPARSE_MEM:
526 return hose->sparse_mem_base;
527 case IOBASE_DENSE_MEM:
528 return hose->dense_mem_base;
529 case IOBASE_SPARSE_IO:
530 return hose->sparse_io_base;
531 case IOBASE_DENSE_IO:
532 return hose->dense_io_base;
533 case IOBASE_ROOT_BUS:
534 return hose->bus->number;