2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/config.h>
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
21 #if defined(CONFIG_DEBUG_DC21285_PORT)
28 #elif defined(CONFIG_DEBUG_ICEDCC)
32 mcr p14, 0, \rb, c0, c1, 0
34 #elif defined(CONFIG_FOOTBRIDGE)
39 strb \rb, [r3, #0x3f8]
41 #elif defined(CONFIG_ARCH_RPC)
44 orr \rb, \rb, #0x00010000
47 strb \rb, [r3, #0x3f8 << 2]
49 #elif defined(CONFIG_ARCH_INTEGRATOR)
56 #elif defined(CONFIG_ARCH_PXA) /* Xscale-type */
59 orr \rb, \rb, #0x00100000
64 #elif defined(CONFIG_ARCH_SA1100)
66 mov \rb, #0x80000000 @ physical base address
67 # if defined(CONFIG_DEBUG_LL_SER3)
68 add \rb, \rb, #0x00050000 @ Ser3
70 add \rb, \rb, #0x00010000 @ Ser1
74 str \rb, [r3, #0x14] @ UTDR
76 #elif defined(CONFIG_ARCH_IXP4XX)
82 #elif defined(CONFIG_ARCH_LH7A40X)
84 ldr \rb, =0x80000700 @ UART2 UARTBASE
89 #elif defined(CONFIG_ARCH_OMAP)
91 mov \rb, #0xff000000 @ physical base address
92 add \rb, \rb, #0x00fb0000
93 #if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
94 add \rb, \rb, #0x00000800
96 #ifdef CONFIG_OMAP_LL_DEBUG_UART3
97 add \rb, \rb, #0x00009000
104 #error no serial architecture defined
119 .macro debug_reloc_start
122 kphex r6, 8 /* processor id */
124 kphex r7, 8 /* architecture id */
126 mrc p15, 0, r0, c1, c0
127 kphex r0, 8 /* control reg */
129 kphex r5, 8 /* decompressed kernel start */
131 kphex r8, 8 /* decompressed kernel end */
133 kphex r4, 8 /* kernel execution address */
138 .macro debug_reloc_end
140 kphex r5, 8 /* end of kernel */
143 bl memdump /* dump 256 bytes at start of kernel */
147 .section ".start", #alloc, #execinstr
149 * sort out different calling conventions
153 .type start,#function
159 .word 0x016f2818 @ Magic numbers to help the loader
160 .word start @ absolute load/run zImage address
161 .word _edata @ zImage end address
162 1: mov r7, r1 @ save architecture ID
165 #ifndef __ARM_ARCH_2__
167 * Booting from Angel - need to enter SVC mode and disable
168 * FIQs/IRQs (numeric definitions from angel arm.h source).
169 * We only do this if we were in user mode on entry.
171 mrs r2, cpsr @ get current mode
172 tst r2, #3 @ not user?
174 mov r0, #0x17 @ angel_SWIreason_EnterSVC
175 swi 0x123456 @ angel_SWI_ARM
177 mrs r2, cpsr @ turn off interrupts to
178 orr r2, r2, #0xc0 @ prevent angel from running
181 teqp pc, #0x0c000003 @ turn off interrupts
185 * Note that some cache flushing and other stuff may
186 * be needed here - is there an Angel SWI call for this?
190 * some architecture specific code can be inserted
191 * by the linker here, but it should preserve r7 and r8.
196 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
197 subs r0, r0, r1 @ calculate the delta offset
199 @ if delta is zero, we are
200 beq not_relocated @ running at the address we
204 * We're running at a different address. We need to fix
205 * up various pointers:
206 * r5 - zImage base address
214 #ifndef CONFIG_ZBOOT_ROM
216 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
217 * we need to fix up pointers into the BSS region.
227 * Relocate all entries in the GOT table.
229 1: ldr r1, [r6, #0] @ relocate entries in the GOT
230 add r1, r1, r0 @ table. This fixes up the
231 str r1, [r6], #4 @ C references.
237 * Relocate entries in the GOT table. We only relocate
238 * the entries that are outside the (relocated) BSS region.
240 1: ldr r1, [r6, #0] @ relocate entries in the GOT
241 cmp r1, r2 @ entry < bss_start ||
242 cmphs r3, r1 @ _end < entry
243 addlo r1, r1, r0 @ table. This fixes up the
244 str r1, [r6], #4 @ C references.
249 not_relocated: mov r0, #0
250 1: str r0, [r2], #4 @ clear bss
258 * The C runtime environment should now be setup
259 * sufficiently. Turn the cache on, set up some
260 * pointers, and start decompressing.
264 mov r1, sp @ malloc space above stack
265 add r2, sp, #0x10000 @ 64k max
268 * Check to see if we will overwrite ourselves.
269 * r4 = final kernel address
270 * r5 = start of this image
271 * r2 = end of malloc space (and therefore this image)
274 * r4 + image length <= r5 -> OK
278 add r0, r4, #4096*1024 @ 4MB largest kernel size
282 mov r5, r2 @ decompress after malloc space
288 bic r0, r0, #127 @ align the kernel length
290 * r0 = decompressed kernel length
292 * r4 = kernel execution address
293 * r5 = decompressed kernel start
295 * r7 = architecture ID
298 add r1, r5, r0 @ end of decompressed kernel
302 1: ldmia r2!, {r8 - r13} @ copy relocation code
303 stmia r1!, {r8 - r13}
304 ldmia r2!, {r8 - r13}
305 stmia r1!, {r8 - r13}
310 add pc, r5, r0 @ call relocation code
313 * We're not in danger of overwriting ourselves. Do this the simple way.
315 * r4 = kernel execution address
316 * r7 = architecture ID
318 wont_overwrite: mov r0, r4
325 .word __bss_start @ r2
329 .word _got_start @ r6
331 .word user_stack+4096 @ sp
332 LC1: .word reloc_end - reloc_start
336 * Turn on the cache. We need to setup some page tables so that we
337 * can have both the I and D caches on.
339 * We place the page tables 16k down from the kernel execution address,
340 * and we hope that nothing else is using it. If we're using it, we
344 * r4 = kernel execution address
346 * r7 = architecture number
347 * r8 = run-time address of "start"
349 * r1, r2, r3, r8, r9, r12 corrupted
350 * This routine must preserve:
354 cache_on: mov r3, #8 @ cache_on function
357 __setup_mmu: sub r3, r4, #16384 @ Page directory size
358 bic r3, r3, #0xff @ Align the pointer
361 * Initialise the page tables, turning on the cacheable and bufferable
362 * bits for the RAM area only.
366 mov r8, r8, lsl #18 @ start of RAM
367 add r9, r8, #0x10000000 @ a reasonable RAM size
371 1: cmp r1, r8 @ if virt > start of RAM
372 orrhs r1, r1, #0x0c @ set cacheable, bufferable
373 cmp r1, r9 @ if virt > end of RAM
374 bichs r1, r1, #0x0c @ clear cacheable, bufferable
375 str r1, [r0], #4 @ 1:1 mapping
380 * If ever we are running from Flash, then we surely want the cache
381 * to be enabled also for our execution instance... We map 2MB of it
382 * so there is no map overlap problem for up to 1 MB compressed kernel.
383 * If the execution is in RAM then we would only be duplicating the above.
388 orr r1, r1, r2, lsl #20
389 add r0, r3, r2, lsl #2
399 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
400 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
401 mrc p15, 0, r0, c1, c0, 0 @ read control reg
402 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
406 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
413 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
414 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
418 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
423 orr r0, r0, #0x000d @ Write buffer, mmu
426 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
427 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
428 mcr p15, 0, r0, c1, c0, 0 @ load control register
432 * All code following this line is relocatable. It is relocated by
433 * the above code to the end of the decompressed kernel image and
434 * executed there. During this time, we have no stacks.
436 * r0 = decompressed kernel length
438 * r4 = kernel execution address
439 * r5 = decompressed kernel start
441 * r7 = architecture ID
445 reloc_start: add r8, r5, r0
450 ldmia r5!, {r0, r2, r3, r9 - r13} @ relocate kernel
451 stmia r1!, {r0, r2, r3, r9 - r13}
458 call_kernel: bl cache_clean_flush
461 mov r1, r7 @ restore architecture number
462 mov pc, r4 @ call kernel
465 * Here follow the relocatable cache support functions for the
466 * various processors. This is a generic hook for locating an
467 * entry and jumping to an instruction at the specified offset
468 * from the start of the block. Please note this is all position
478 call_cache_fn: adr r12, proc_types
479 mrc p15, 0, r6, c0, c0 @ get processor ID
480 1: ldr r1, [r12, #0] @ get value
481 ldr r2, [r12, #4] @ get mask
482 eor r1, r1, r6 @ (real ^ match)
484 addeq pc, r12, r3 @ call cache function
489 * Table for cache operations. This is basically:
492 * - 'cache on' method instruction
493 * - 'cache off' method instruction
494 * - 'cache flush' method instruction
496 * We match an entry using: ((real_id ^ match) & mask) == 0
498 * Writethrough caches generally only need 'on' and 'off'
499 * methods. Writeback caches _must_ have the flush method
502 .type proc_types,#object
504 .word 0x41560600 @ ARM6/610
506 b __arm6_cache_off @ works, but slow
509 @ b __arm6_cache_on @ untested
511 @ b __armv3_cache_flush
513 .word 0x00000000 @ old ARM ID
519 .word 0x41007000 @ ARM7/710
525 .word 0x41807200 @ ARM720T (writethrough)
531 .word 0x00007000 @ ARM7 IDs
537 @ Everything from here on will be the new ID system.
539 .word 0x4401a100 @ sa110 / sa1100
543 b __armv4_cache_flush
545 .word 0x6901b110 @ sa1110
549 b __armv4_cache_flush
551 @ These match on the architecture ID
553 .word 0x00020000 @ ARMv4T
557 b __armv4_cache_flush
559 .word 0x00050000 @ ARMv5TE
563 b __armv4_cache_flush
565 .word 0x00060000 @ ARMv5TEJ
569 b __armv4_cache_flush
571 .word 0 @ unrecognised type
577 .size proc_types, . - proc_types
580 * Turn off the Cache and MMU. ARMv3 does not support
581 * reading the control register, but ARMv4 does.
583 * On entry, r6 = processor ID
584 * On exit, r0, r1, r2, r3, r12 corrupted
585 * This routine must preserve: r4, r6, r7
588 cache_off: mov r3, #12 @ cache_off function
592 mrc p15, 0, r0, c1, c0
594 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
596 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
597 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
601 mov r0, #0x00000030 @ ARM6 control reg.
605 mov r0, #0x00000070 @ ARM7 control reg.
609 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
611 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
612 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
616 * Clean and flush the cache to maintain consistency.
621 * r1, r2, r3, r11, r12 corrupted
622 * This routine must preserve:
631 mov r2, #64*1024 @ default: 32K dcache size (*2)
632 mov r11, #32 @ default: 32 byte line size
633 mrc p15, 0, r3, c0, c0, 1 @ read cache type
634 teq r3, r6 @ cache ID register present?
639 mov r2, r2, lsl r1 @ base dcache size *2
640 tst r3, #1 << 14 @ test M bit
641 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
645 mov r11, r11, lsl r3 @ cache line size in bytes
647 bic r1, pc, #63 @ align to longest cache line
649 1: ldr r3, [r1], r11 @ s/w flush D cache
653 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
654 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
655 mcr p15, 0, r1, c7, c10, 4 @ drain WB
660 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
664 * Various debugging routines for printing hex characters and
665 * memory, which again must be relocatable.
668 .type phexbuf,#object
670 .size phexbuf, . - phexbuf
672 phex: adr r3, phexbuf
709 2: mov r0, r11, lsl #2
717 ldr r0, [r12, r11, lsl #2]
738 .section ".stack", "w"
739 user_stack: .space 4096