2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/config.h>
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
21 #if defined(CONFIG_DEBUG_DC21285_PORT)
28 #elif defined(CONFIG_DEBUG_ICEDCC)
32 mcr p14, 0, \rb, c0, c1, 0
34 #elif defined(CONFIG_FOOTBRIDGE)
39 strb \rb, [r3, #0x3f8]
41 #elif defined(CONFIG_ARCH_RPC)
44 orr \rb, \rb, #0x00010000
47 strb \rb, [r3, #0x3f8 << 2]
49 #elif defined(CONFIG_ARCH_INTEGRATOR)
56 #elif defined(CONFIG_ARCH_PXA) /* Xscale-type */
59 orr \rb, \rb, #0x00100000
64 #elif defined(CONFIG_ARCH_SA1100)
66 mov \rb, #0x80000000 @ physical base address
67 # if defined(CONFIG_DEBUG_LL_SER3)
68 add \rb, \rb, #0x00050000 @ Ser3
70 add \rb, \rb, #0x00010000 @ Ser1
74 str \rb, [r3, #0x14] @ UTDR
76 #elif defined(CONFIG_ARCH_IXP4XX)
82 #elif defined(CONFIG_ARCH_LH7A40X)
84 ldr \rb, =0x80000700 @ UART2 UARTBASE
90 #error no serial architecture defined
105 .macro debug_reloc_start
108 kphex r6, 8 /* processor id */
110 kphex r7, 8 /* architecture id */
112 mrc p15, 0, r0, c1, c0
113 kphex r0, 8 /* control reg */
115 kphex r5, 8 /* decompressed kernel start */
117 kphex r8, 8 /* decompressed kernel end */
119 kphex r4, 8 /* kernel execution address */
124 .macro debug_reloc_end
126 kphex r5, 8 /* end of kernel */
129 bl memdump /* dump 256 bytes at start of kernel */
133 .section ".start", #alloc, #execinstr
135 * sort out different calling conventions
139 .type start,#function
145 .word 0x016f2818 @ Magic numbers to help the loader
146 .word start @ absolute load/run zImage address
147 .word _edata @ zImage end address
148 1: mov r7, r1 @ save architecture ID
151 #ifndef __ARM_ARCH_2__
153 * Booting from Angel - need to enter SVC mode and disable
154 * FIQs/IRQs (numeric definitions from angel arm.h source).
155 * We only do this if we were in user mode on entry.
157 mrs r2, cpsr @ get current mode
158 tst r2, #3 @ not user?
160 mov r0, #0x17 @ angel_SWIreason_EnterSVC
161 swi 0x123456 @ angel_SWI_ARM
163 mrs r2, cpsr @ turn off interrupts to
164 orr r2, r2, #0xc0 @ prevent angel from running
167 teqp pc, #0x0c000003 @ turn off interrupts
171 * Note that some cache flushing and other stuff may
172 * be needed here - is there an Angel SWI call for this?
176 * some architecture specific code can be inserted
177 * by the linker here, but it should preserve r7 and r8.
182 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
183 subs r0, r0, r1 @ calculate the delta offset
185 @ if delta is zero, we are
186 beq not_relocated @ running at the address we
190 * We're running at a different address. We need to fix
191 * up various pointers:
192 * r5 - zImage base address
200 #ifndef CONFIG_ZBOOT_ROM
202 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
203 * we need to fix up pointers into the BSS region.
213 * Relocate all entries in the GOT table.
215 1: ldr r1, [r6, #0] @ relocate entries in the GOT
216 add r1, r1, r0 @ table. This fixes up the
217 str r1, [r6], #4 @ C references.
223 * Relocate entries in the GOT table. We only relocate
224 * the entries that are outside the (relocated) BSS region.
226 1: ldr r1, [r6, #0] @ relocate entries in the GOT
227 cmp r1, r2 @ entry < bss_start ||
228 cmphs r3, r1 @ _end < entry
229 addlo r1, r1, r0 @ table. This fixes up the
230 str r1, [r6], #4 @ C references.
235 not_relocated: mov r0, #0
236 1: str r0, [r2], #4 @ clear bss
244 * The C runtime environment should now be setup
245 * sufficiently. Turn the cache on, set up some
246 * pointers, and start decompressing.
250 mov r1, sp @ malloc space above stack
251 add r2, sp, #0x10000 @ 64k max
254 * Check to see if we will overwrite ourselves.
255 * r4 = final kernel address
256 * r5 = start of this image
257 * r2 = end of malloc space (and therefore this image)
260 * r4 + image length <= r5 -> OK
264 add r0, r4, #4096*1024 @ 4MB largest kernel size
268 mov r5, r2 @ decompress after malloc space
274 bic r0, r0, #127 @ align the kernel length
276 * r0 = decompressed kernel length
278 * r4 = kernel execution address
279 * r5 = decompressed kernel start
281 * r7 = architecture ID
284 add r1, r5, r0 @ end of decompressed kernel
288 1: ldmia r2!, {r8 - r13} @ copy relocation code
289 stmia r1!, {r8 - r13}
290 ldmia r2!, {r8 - r13}
291 stmia r1!, {r8 - r13}
296 add pc, r5, r0 @ call relocation code
299 * We're not in danger of overwriting ourselves. Do this the simple way.
301 * r4 = kernel execution address
302 * r7 = architecture ID
304 wont_overwrite: mov r0, r4
311 .word __bss_start @ r2
313 .word _load_addr @ r4
315 .word _got_start @ r6
317 .word user_stack+4096 @ sp
318 LC1: .word reloc_end - reloc_start
322 * Turn on the cache. We need to setup some page tables so that we
323 * can have both the I and D caches on.
325 * We place the page tables 16k down from the kernel execution address,
326 * and we hope that nothing else is using it. If we're using it, we
330 * r4 = kernel execution address
332 * r7 = architecture number
333 * r8 = run-time address of "start"
335 * r1, r2, r3, r8, r9, r12 corrupted
336 * This routine must preserve:
340 cache_on: mov r3, #8 @ cache_on function
343 __setup_mmu: sub r3, r4, #16384 @ Page directory size
344 bic r3, r3, #0xff @ Align the pointer
347 * Initialise the page tables, turning on the cacheable and bufferable
348 * bits for the RAM area only.
352 mov r8, r8, lsl #18 @ start of RAM
353 add r9, r8, #0x10000000 @ a reasonable RAM size
357 1: cmp r1, r8 @ if virt > start of RAM
358 orrhs r1, r1, #0x0c @ set cacheable, bufferable
359 cmp r1, r9 @ if virt > end of RAM
360 bichs r1, r1, #0x0c @ clear cacheable, bufferable
361 str r1, [r0], #4 @ 1:1 mapping
366 * If ever we are running from Flash, then we surely want the cache
367 * to be enabled also for our execution instance... We map 2MB of it
368 * so there is no map overlap problem for up to 1 MB compressed kernel.
369 * If the execution is in RAM then we would only be duplicating the above.
374 orr r1, r1, r2, lsl #20
375 add r0, r3, r2, lsl #2
385 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
386 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
387 mrc p15, 0, r0, c1, c0, 0 @ read control reg
388 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
392 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
399 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
400 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
404 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
409 orr r0, r0, #0x000d @ Write buffer, mmu
412 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
413 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
414 mcr p15, 0, r0, c1, c0, 0 @ load control register
418 * All code following this line is relocatable. It is relocated by
419 * the above code to the end of the decompressed kernel image and
420 * executed there. During this time, we have no stacks.
422 * r0 = decompressed kernel length
424 * r4 = kernel execution address
425 * r5 = decompressed kernel start
427 * r7 = architecture ID
431 reloc_start: add r8, r5, r0
436 ldmia r5!, {r0, r2, r3, r9 - r13} @ relocate kernel
437 stmia r1!, {r0, r2, r3, r9 - r13}
444 call_kernel: bl cache_clean_flush
447 mov r1, r7 @ restore architecture number
448 mov pc, r4 @ call kernel
451 * Here follow the relocatable cache support functions for the
452 * various processors. This is a generic hook for locating an
453 * entry and jumping to an instruction at the specified offset
454 * from the start of the block. Please note this is all position
464 call_cache_fn: adr r12, proc_types
465 mrc p15, 0, r6, c0, c0 @ get processor ID
466 1: ldr r1, [r12, #0] @ get value
467 ldr r2, [r12, #4] @ get mask
468 eor r1, r1, r6 @ (real ^ match)
470 addeq pc, r12, r3 @ call cache function
475 * Table for cache operations. This is basically:
478 * - 'cache on' method instruction
479 * - 'cache off' method instruction
480 * - 'cache flush' method instruction
482 * We match an entry using: ((real_id ^ match) & mask) == 0
484 * Writethrough caches generally only need 'on' and 'off'
485 * methods. Writeback caches _must_ have the flush method
488 .type proc_types,#object
490 .word 0x41560600 @ ARM6/610
492 b __arm6_cache_off @ works, but slow
495 @ b __arm6_cache_on @ untested
497 @ b __armv3_cache_flush
499 .word 0x00000000 @ old ARM ID
505 .word 0x41007000 @ ARM7/710
511 .word 0x41807200 @ ARM720T (writethrough)
517 .word 0x00007000 @ ARM7 IDs
523 @ Everything from here on will be the new ID system.
525 .word 0x4401a100 @ sa110 / sa1100
529 b __armv4_cache_flush
531 .word 0x6901b110 @ sa1110
535 b __armv4_cache_flush
537 @ These match on the architecture ID
539 .word 0x00020000 @ ARMv4T
543 b __armv4_cache_flush
545 .word 0x00050000 @ ARMv5TE
549 b __armv4_cache_flush
551 .word 0x00060000 @ ARMv5TEJ
555 b __armv4_cache_flush
557 .word 0 @ unrecognised type
563 .size proc_types, . - proc_types
566 * Turn off the Cache and MMU. ARMv3 does not support
567 * reading the control register, but ARMv4 does.
569 * On entry, r6 = processor ID
570 * On exit, r0, r1, r2, r3, r12 corrupted
571 * This routine must preserve: r4, r6, r7
574 cache_off: mov r3, #12 @ cache_off function
578 mrc p15, 0, r0, c1, c0
580 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
582 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
583 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
587 mov r0, #0x00000030 @ ARM6 control reg.
591 mov r0, #0x00000070 @ ARM7 control reg.
595 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
597 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
598 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
602 * Clean and flush the cache to maintain consistency.
607 * r1, r2, r3, r11, r12 corrupted
608 * This routine must preserve:
617 mov r2, #64*1024 @ default: 32K dcache size (*2)
618 mov r11, #32 @ default: 32 byte line size
619 mrc p15, 0, r3, c0, c0, 1 @ read cache type
620 teq r3, r6 @ cache ID register present?
625 mov r2, r2, lsl r1 @ base dcache size *2
626 tst r3, #1 << 14 @ test M bit
627 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
631 mov r11, r11, lsl r3 @ cache line size in bytes
633 bic r1, pc, #63 @ align to longest cache line
635 1: ldr r3, [r1], r11 @ s/w flush D cache
639 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
640 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
641 mcr p15, 0, r1, c7, c10, 4 @ drain WB
646 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
650 * Various debugging routines for printing hex characters and
651 * memory, which again must be relocatable.
654 .type phexbuf,#object
656 .size phexbuf, . - phexbuf
658 phex: adr r3, phexbuf
695 2: mov r0, r11, lsl #2
703 ldr r0, [r12, r11, lsl #2]
724 .section ".stack", "w"
725 user_stack: .space 4096