2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/config.h>
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
21 #if defined(CONFIG_DEBUG_DC21285_PORT)
28 #elif defined(CONFIG_DEBUG_ICEDCC)
32 mcr p14, 0, \rb, c0, c1, 0
34 #elif defined(CONFIG_FOOTBRIDGE)
39 strb \rb, [r3, #0x3f8]
41 #elif defined(CONFIG_ARCH_RPC)
44 orr \rb, \rb, #0x00010000
47 strb \rb, [r3, #0x3f8 << 2]
49 #elif defined(CONFIG_ARCH_INTEGRATOR)
56 #elif defined(CONFIG_ARCH_PXA) /* Xscale-type */
59 orr \rb, \rb, #0x00100000
64 #elif defined(CONFIG_ARCH_SA1100)
66 mov \rb, #0x80000000 @ physical base address
67 # if defined(CONFIG_DEBUG_LL_SER3)
68 add \rb, \rb, #0x00050000 @ Ser3
70 add \rb, \rb, #0x00010000 @ Ser1
74 str \rb, [r3, #0x14] @ UTDR
76 #elif defined(CONFIG_ARCH_IXP4XX)
82 #elif defined(CONFIG_ARCH_IXP2000)
85 orr \rb, \rb, #0x00030000
90 #elif defined(CONFIG_ARCH_LH7A40X)
92 ldr \rb, =0x80000700 @ UART2 UARTBASE
97 #elif defined(CONFIG_ARCH_OMAP)
99 mov \rb, #0xff000000 @ physical base address
100 add \rb, \rb, #0x00fb0000
101 #if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
102 add \rb, \rb, #0x00000800
104 #ifdef CONFIG_OMAP_LL_DEBUG_UART3
105 add \rb, \rb, #0x00009000
111 #elif defined(CONFIG_ARCH_IOP331)
114 orr \rb, \rb, #0x00ff0000
115 orr \rb, \rb, #0x0000f700 @ location of the UART
121 #error no serial architecture defined
136 .macro debug_reloc_start
139 kphex r6, 8 /* processor id */
141 kphex r7, 8 /* architecture id */
143 mrc p15, 0, r0, c1, c0
144 kphex r0, 8 /* control reg */
146 kphex r5, 8 /* decompressed kernel start */
148 kphex r8, 8 /* decompressed kernel end */
150 kphex r4, 8 /* kernel execution address */
155 .macro debug_reloc_end
157 kphex r5, 8 /* end of kernel */
160 bl memdump /* dump 256 bytes at start of kernel */
164 .section ".start", #alloc, #execinstr
166 * sort out different calling conventions
170 .type start,#function
176 .word 0x016f2818 @ Magic numbers to help the loader
177 .word start @ absolute load/run zImage address
178 .word _edata @ zImage end address
179 1: mov r7, r1 @ save architecture ID
182 #ifndef __ARM_ARCH_2__
184 * Booting from Angel - need to enter SVC mode and disable
185 * FIQs/IRQs (numeric definitions from angel arm.h source).
186 * We only do this if we were in user mode on entry.
188 mrs r2, cpsr @ get current mode
189 tst r2, #3 @ not user?
191 mov r0, #0x17 @ angel_SWIreason_EnterSVC
192 swi 0x123456 @ angel_SWI_ARM
194 mrs r2, cpsr @ turn off interrupts to
195 orr r2, r2, #0xc0 @ prevent angel from running
198 teqp pc, #0x0c000003 @ turn off interrupts
202 * Note that some cache flushing and other stuff may
203 * be needed here - is there an Angel SWI call for this?
207 * some architecture specific code can be inserted
208 * by the linker here, but it should preserve r7 and r8.
213 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
214 subs r0, r0, r1 @ calculate the delta offset
216 @ if delta is zero, we are
217 beq not_relocated @ running at the address we
221 * We're running at a different address. We need to fix
222 * up various pointers:
223 * r5 - zImage base address
231 #ifndef CONFIG_ZBOOT_ROM
233 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
234 * we need to fix up pointers into the BSS region.
244 * Relocate all entries in the GOT table.
246 1: ldr r1, [r6, #0] @ relocate entries in the GOT
247 add r1, r1, r0 @ table. This fixes up the
248 str r1, [r6], #4 @ C references.
254 * Relocate entries in the GOT table. We only relocate
255 * the entries that are outside the (relocated) BSS region.
257 1: ldr r1, [r6, #0] @ relocate entries in the GOT
258 cmp r1, r2 @ entry < bss_start ||
259 cmphs r3, r1 @ _end < entry
260 addlo r1, r1, r0 @ table. This fixes up the
261 str r1, [r6], #4 @ C references.
266 not_relocated: mov r0, #0
267 1: str r0, [r2], #4 @ clear bss
275 * The C runtime environment should now be setup
276 * sufficiently. Turn the cache on, set up some
277 * pointers, and start decompressing.
281 mov r1, sp @ malloc space above stack
282 add r2, sp, #0x10000 @ 64k max
285 * Check to see if we will overwrite ourselves.
286 * r4 = final kernel address
287 * r5 = start of this image
288 * r2 = end of malloc space (and therefore this image)
291 * r4 + image length <= r5 -> OK
295 add r0, r4, #4096*1024 @ 4MB largest kernel size
299 mov r5, r2 @ decompress after malloc space
305 bic r0, r0, #127 @ align the kernel length
307 * r0 = decompressed kernel length
309 * r4 = kernel execution address
310 * r5 = decompressed kernel start
312 * r7 = architecture ID
315 add r1, r5, r0 @ end of decompressed kernel
319 1: ldmia r2!, {r8 - r13} @ copy relocation code
320 stmia r1!, {r8 - r13}
321 ldmia r2!, {r8 - r13}
322 stmia r1!, {r8 - r13}
327 add pc, r5, r0 @ call relocation code
330 * We're not in danger of overwriting ourselves. Do this the simple way.
332 * r4 = kernel execution address
333 * r7 = architecture ID
335 wont_overwrite: mov r0, r4
342 .word __bss_start @ r2
346 .word _got_start @ r6
348 .word user_stack+4096 @ sp
349 LC1: .word reloc_end - reloc_start
352 #ifdef CONFIG_ARCH_RPC
354 params: ldr r0, =params_phys
361 * Turn on the cache. We need to setup some page tables so that we
362 * can have both the I and D caches on.
364 * We place the page tables 16k down from the kernel execution address,
365 * and we hope that nothing else is using it. If we're using it, we
369 * r4 = kernel execution address
371 * r7 = architecture number
372 * r8 = run-time address of "start"
374 * r1, r2, r3, r8, r9, r12 corrupted
375 * This routine must preserve:
379 cache_on: mov r3, #8 @ cache_on function
382 __setup_mmu: sub r3, r4, #16384 @ Page directory size
383 bic r3, r3, #0xff @ Align the pointer
386 * Initialise the page tables, turning on the cacheable and bufferable
387 * bits for the RAM area only.
391 mov r8, r8, lsl #18 @ start of RAM
392 add r9, r8, #0x10000000 @ a reasonable RAM size
396 1: cmp r1, r8 @ if virt > start of RAM
397 orrhs r1, r1, #0x0c @ set cacheable, bufferable
398 cmp r1, r9 @ if virt > end of RAM
399 bichs r1, r1, #0x0c @ clear cacheable, bufferable
400 str r1, [r0], #4 @ 1:1 mapping
405 * If ever we are running from Flash, then we surely want the cache
406 * to be enabled also for our execution instance... We map 2MB of it
407 * so there is no map overlap problem for up to 1 MB compressed kernel.
408 * If the execution is in RAM then we would only be duplicating the above.
413 orr r1, r1, r2, lsl #20
414 add r0, r3, r2, lsl #2
424 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
425 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
426 mrc p15, 0, r0, c1, c0, 0 @ read control reg
427 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
431 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
438 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
439 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
443 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
448 orr r0, r0, #0x000d @ Write buffer, mmu
451 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
452 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
453 mcr p15, 0, r0, c1, c0, 0 @ load control register
457 * All code following this line is relocatable. It is relocated by
458 * the above code to the end of the decompressed kernel image and
459 * executed there. During this time, we have no stacks.
461 * r0 = decompressed kernel length
463 * r4 = kernel execution address
464 * r5 = decompressed kernel start
466 * r7 = architecture ID
470 reloc_start: add r8, r5, r0
475 ldmia r5!, {r0, r2, r3, r9 - r13} @ relocate kernel
476 stmia r1!, {r0, r2, r3, r9 - r13}
483 call_kernel: bl cache_clean_flush
486 mov r1, r7 @ restore architecture number
487 mov pc, r4 @ call kernel
490 * Here follow the relocatable cache support functions for the
491 * various processors. This is a generic hook for locating an
492 * entry and jumping to an instruction at the specified offset
493 * from the start of the block. Please note this is all position
503 call_cache_fn: adr r12, proc_types
504 mrc p15, 0, r6, c0, c0 @ get processor ID
505 1: ldr r1, [r12, #0] @ get value
506 ldr r2, [r12, #4] @ get mask
507 eor r1, r1, r6 @ (real ^ match)
509 addeq pc, r12, r3 @ call cache function
514 * Table for cache operations. This is basically:
517 * - 'cache on' method instruction
518 * - 'cache off' method instruction
519 * - 'cache flush' method instruction
521 * We match an entry using: ((real_id ^ match) & mask) == 0
523 * Writethrough caches generally only need 'on' and 'off'
524 * methods. Writeback caches _must_ have the flush method
527 .type proc_types,#object
529 .word 0x41560600 @ ARM6/610
531 b __arm6_cache_off @ works, but slow
534 @ b __arm6_cache_on @ untested
536 @ b __armv3_cache_flush
538 .word 0x00000000 @ old ARM ID
544 .word 0x41007000 @ ARM7/710
550 .word 0x41807200 @ ARM720T (writethrough)
556 .word 0x00007000 @ ARM7 IDs
562 @ Everything from here on will be the new ID system.
564 .word 0x4401a100 @ sa110 / sa1100
568 b __armv4_cache_flush
570 .word 0x6901b110 @ sa1110
574 b __armv4_cache_flush
576 @ These match on the architecture ID
578 .word 0x00020000 @ ARMv4T
582 b __armv4_cache_flush
584 .word 0x00050000 @ ARMv5TE
588 b __armv4_cache_flush
590 .word 0x00060000 @ ARMv5TEJ
594 b __armv4_cache_flush
596 .word 0x00070000 @ ARMv6
600 b __armv6_cache_flush
602 .word 0 @ unrecognised type
608 .size proc_types, . - proc_types
611 * Turn off the Cache and MMU. ARMv3 does not support
612 * reading the control register, but ARMv4 does.
614 * On entry, r6 = processor ID
615 * On exit, r0, r1, r2, r3, r12 corrupted
616 * This routine must preserve: r4, r6, r7
619 cache_off: mov r3, #12 @ cache_off function
623 mrc p15, 0, r0, c1, c0
625 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
627 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
628 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
632 mov r0, #0x00000030 @ ARM6 control reg.
636 mov r0, #0x00000070 @ ARM7 control reg.
640 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
642 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
643 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
647 * Clean and flush the cache to maintain consistency.
652 * r1, r2, r3, r11, r12 corrupted
653 * This routine must preserve:
663 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
664 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
665 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
666 mcr p15, 0, r1, c7, c10, 4 @ drain WB
670 mov r2, #64*1024 @ default: 32K dcache size (*2)
671 mov r11, #32 @ default: 32 byte line size
672 mrc p15, 0, r3, c0, c0, 1 @ read cache type
673 teq r3, r6 @ cache ID register present?
678 mov r2, r2, lsl r1 @ base dcache size *2
679 tst r3, #1 << 14 @ test M bit
680 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
684 mov r11, r11, lsl r3 @ cache line size in bytes
686 bic r1, pc, #63 @ align to longest cache line
688 1: ldr r3, [r1], r11 @ s/w flush D cache
692 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
693 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
694 mcr p15, 0, r1, c7, c10, 4 @ drain WB
699 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
703 * Various debugging routines for printing hex characters and
704 * memory, which again must be relocatable.
707 .type phexbuf,#object
709 .size phexbuf, . - phexbuf
711 phex: adr r3, phexbuf
748 2: mov r0, r11, lsl #2
756 ldr r0, [r12, r11, lsl #2]
777 .section ".stack", "w"
778 user_stack: .space 4096