2 * linux/arch/arm/kernel/debug-armv.S
4 * Copyright (C) 1994-1999 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * 32-bit debugging code
12 #include <linux/config.h>
13 #include <linux/linkage.h>
14 #include <asm/hardware.h>
19 * Some debugging routines (useful if you've got MM problems and
20 * printk isn't working). For DEBUGGING ONLY!!! Do not leave
21 * references to these in a production kernel!
23 #if defined(CONFIG_ARCH_RPC)
26 orr \rx, \rx, #0x00010000
27 orr \rx, \rx, #0x00000fe0
35 1001: ldrb \rd, [\rx, #0x14]
42 1001: ldrb \rd, [\rx, #0x18]
47 #elif defined(CONFIG_DEBUG_ICEDCC)
48 @@ debug using ARM EmbeddedICE DCC channel
52 .macro senduart, rd, rx
53 mcr p14, 0, \rd, c1, c0, 0
56 .macro busyuart, rd, rx
58 mrc p14, 0, \rx, c0, c0, 0
64 .macro waituart, rd, rx
69 mrc p14, 0, \rx, c0, c0, 0
75 #elif defined(CONFIG_ARCH_EBSA110)
78 orr \rx, \rx, #0x00000be0
86 1002: ldrb \rd, [\rx, #0x14]
93 1001: ldrb \rd, [\rx, #0x18]
98 #elif defined(CONFIG_ARCH_SHARK)
101 orr \rx, \rx, #0x000003f8
104 .macro senduart,rd,rx
108 .macro busyuart,rd,rx
110 1001: add \rd, \rd, #1
115 .macro waituart,rd,rx
118 #elif defined(CONFIG_FOOTBRIDGE)
120 #include <asm/hardware/dec21285.h>
122 #ifndef CONFIG_DEBUG_DC21285_PORT
123 /* For NetWinder debugging */
125 mrc p15, 0, \rx, c1, c0
126 tst \rx, #1 @ MMU enabled?
127 moveq \rx, #0x7c000000 @ physical
128 movne \rx, #0xff000000 @ virtual
129 orr \rx, \rx, #0x000003f8
132 .macro senduart,rd,rx
136 .macro busyuart,rd,rx
137 1002: ldrb \rd, [\rx, #0x5]
143 .macro waituart,rd,rx
144 1001: ldrb \rd, [\rx, #0x6]
149 /* For EBSA285 debugging */
150 .equ dc21285_high, ARMCSR_BASE & 0xff000000
151 .equ dc21285_low, ARMCSR_BASE & 0x00ffffff
154 mov \rx, #dc21285_high
156 orr \rx, \rx, #dc21285_low
160 .macro senduart,rd,rx
161 str \rd, [\rx, #0x160] @ UARTDR
164 .macro busyuart,rd,rx
165 1001: ldr \rd, [\rx, #0x178] @ UARTFLG
170 .macro waituart,rd,rx
173 #elif defined(CONFIG_ARCH_FTVPCI)
175 mrc p15, 0, \rx, c1, c0
176 tst \rx, #1 @ MMU enabled?
177 movne \rx, #0xe0000000
178 moveq \rx, #0x10000000
181 .macro senduart,rd,rx
185 .macro busyuart,rd,rx
186 1001: ldr \rd, [\rx, #0x4]
191 .macro waituart,rd,rx
194 #elif defined(CONFIG_ARCH_SA1100)
197 mrc p15, 0, \rx, c1, c0
198 tst \rx, #1 @ MMU enabled?
199 moveq \rx, #0x80000000 @ physical base address
200 movne \rx, #0xf8000000 @ virtual address
202 @ We probe for the active serial port here, coherently with
203 @ the comment in include/asm-arm/arch-sa1100/uncompress.h.
204 @ We assume r1 can be clobbered.
206 @ see if Ser3 is active
207 add \rx, \rx, #0x00050000
208 ldr r1, [\rx, #UTCR3]
211 @ if Ser3 is inactive, then try Ser1
212 addeq \rx, \rx, #(0x00010000 - 0x00050000)
213 ldreq r1, [\rx, #UTCR3]
216 @ if Ser1 is inactive, then try Ser2
217 addeq \rx, \rx, #(0x00030000 - 0x00010000)
218 ldreq r1, [\rx, #UTCR3]
221 @ if all ports are inactive, then there is nothing we can do
225 .macro senduart,rd,rx
226 str \rd, [\rx, #UTDR]
229 .macro waituart,rd,rx
230 1001: ldr \rd, [\rx, #UTSR1]
235 .macro busyuart,rd,rx
236 1001: ldr \rd, [\rx, #UTSR1]
241 #elif defined(CONFIG_ARCH_PXA)
244 mrc p15, 0, \rx, c1, c0
245 tst \rx, #1 @ MMU enabled?
246 moveq \rx, #0x40000000 @ physical
247 movne \rx, #io_p2v(0x40000000) @ virtual
248 orr \rx, \rx, #0x00100000
251 .macro senduart,rd,rx
255 .macro busyuart,rd,rx
256 1002: ldr \rd, [\rx, #0x14]
261 .macro waituart,rd,rx
262 1001: ldr \rd, [\rx, #0x14]
266 #elif defined(CONFIG_ARCH_CLPS7500)
269 orr \rx, \rx, #0x00010000
270 orr \rx, \rx, #0x00000be0
273 .macro senduart,rd,rx
277 .macro busyuart,rd,rx
280 .macro waituart,rd,rx
281 1001: ldrb \rd, [\rx, #0x14]
286 #elif defined(CONFIG_ARCH_L7200)
288 .equ io_virt, IO_BASE
289 .equ io_phys, IO_START
292 mrc p15, 0, \rx, c1, c0
293 tst \rx, #1 @ MMU enabled?
294 moveq \rx, #io_phys @ physical base address
295 movne \rx, #io_virt @ virtual address
296 add \rx, \rx, #0x00044000 @ UART1
297 @ add \rx, \rx, #0x00045000 @ UART2
300 .macro senduart,rd,rx
301 str \rd, [\rx, #0x0] @ UARTDR
304 .macro waituart,rd,rx
305 1001: ldr \rd, [\rx, #0x18] @ UARTFLG
306 tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
310 .macro busyuart,rd,rx
311 1001: ldr \rd, [\rx, #0x18] @ UARTFLG
312 tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
316 #elif defined(CONFIG_ARCH_INTEGRATOR)
318 #include <asm/hardware/amba_serial.h>
321 mrc p15, 0, \rx, c1, c0
322 tst \rx, #1 @ MMU enabled?
323 moveq \rx, #0x16000000 @ physical base address
324 movne \rx, #0xf0000000 @ virtual base
325 addne \rx, \rx, #0x16000000 >> 4
328 .macro senduart,rd,rx
329 strb \rd, [\rx, #UART01x_DR]
332 .macro waituart,rd,rx
333 1001: ldr \rd, [\rx, #0x18] @ UARTFLG
334 tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
338 .macro busyuart,rd,rx
339 1001: ldr \rd, [\rx, #0x18] @ UARTFLG
340 tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
344 #elif defined(CONFIG_ARCH_CLPS711X)
346 #include <asm/hardware/clps7111.h>
349 mrc p15, 0, \rx, c1, c0
350 tst \rx, #1 @ MMU enabled?
351 moveq \rx, #CLPS7111_PHYS_BASE
352 movne \rx, #CLPS7111_VIRT_BASE
353 #ifndef CONFIG_DEBUG_CLPS711X_UART2
354 add \rx, \rx, #0x0000 @ UART1
356 add \rx, \rx, #0x1000 @ UART2
360 .macro senduart,rd,rx
361 str \rd, [\rx, #0x0480] @ UARTDR
364 .macro waituart,rd,rx
365 1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx
366 tst \rd, #1 << 11 @ UBUSYx
370 .macro busyuart,rd,rx
371 tst \rx, #0x1000 @ UART2 does not have CTS here
373 1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx
374 tst \rd, #1 << 8 @ CTS
379 #elif defined(CONFIG_ARCH_CAMELOT)
381 #include <asm/arch/excalibur.h>
383 #include <asm/arch/uart00.h>
386 mrc p15, 0, \rx, c1, c0
387 tst \rx, #1 @ MMU enabled?
388 ldr \rx, =EXC_UART00_BASE @ physical base address
389 orrne \rx, \rx, #0xff000000 @ virtual base
390 orrne \rx, \rx, #0x00f00000
393 .macro senduart,rd,rx
394 str \rd, [\rx, #UART_TD(0)]
397 .macro waituart,rd,rx
398 1001: ldr \rd, [\rx, #UART_TSR(0)]
399 and \rd, \rd, #UART_TSR_TX_LEVEL_MSK
404 .macro busyuart,rd,rx
405 1001: ldr \rd, [\rx, #UART_TSR(0)]
406 ands \rd, \rd, #UART_TSR_TX_LEVEL_MSK
410 #elif defined(CONFIG_ARCH_IOP3XX)
413 mov \rx, #0xfe000000 @ physical
414 #ifdef CONFIG_ARCH_IQ80310
415 orr \rx, \rx, #0x00810000 @ location of the UART
416 #elif defined(CONFIG_ARCH_IQ80321)
417 orr \rx, \rx, #0x00800000 @ location of the UART
419 #error Unknown IOP3XX implementation
423 .macro senduart,rd,rx
427 .macro busyuart,rd,rx
428 1002: ldrb \rd, [\rx, #0x5]
434 .macro waituart,rd,rx
435 #ifndef CONFIG_ARCH_IQ80321
436 1001: ldrb \rd, [\rx, #0x6]
442 #elif defined(CONFIG_ARCH_IXP4XX)
445 mrc p15, 0, \rx, c1, c0
446 tst \rx, #1 @ MMU enabled?
447 moveq \rx, #0xc8000000
448 movne \rx, #0xff000000
449 add \rx,\rx,#3 @ Uart regs are at off set of 3 if
450 @ byte writes used - Big Endian.
453 .macro senduart,rd,rx
457 .macro waituart,rd,rx
458 1002: ldrb \rd, [\rx, #0x14]
459 and \rd, \rd, #0x60 @ check THRE and TEMT bits
464 .macro busyuart,rd,rx
467 #elif defined(CONFIG_ARCH_OMAP)
470 mrc p15, 0, \rx, c1, c0
471 tst \rx, #1 @ MMU enabled?
472 moveq \rx, #0xff000000 @ physical base address
473 movne \rx, #0xfe000000 @ virtual base
474 orr \rx, \rx, #0x00fb0000
475 #ifdef CONFIG_OMAP_LL_DEBUG_UART3
476 orr \rx, \rx, #0x00009000 @ UART 3
478 #if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
479 orr \rx, \rx, #0x00000800 @ UART 2 & 3
483 .macro senduart,rd,rx
487 .macro busyuart,rd,rx
488 1001: ldrb \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends
492 ldrb \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only
499 .macro waituart,rd,rx
502 #elif defined(CONFIG_ARCH_S3C2410)
503 #include <asm/arch/map.h>
504 #include <asm/arch/regs-serial.h>
507 mrc p15, 0, \rx, c1, c0
509 ldreq \rx, = S3C2410_PA_UART
510 ldrne \rx, = S3C2410_VA_UART
511 #if CONFIG_DEBUG_S3C2410_UART != 0
512 add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C2410_UART)
516 .macro senduart,rd,rx
517 str \rd, [\rx, # S3C2410_UTXH ]
520 .macro busyuart, rd, rx
521 ldr \rd, [ \rx, # S3C2410_UFCON ]
522 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
526 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
527 tst \rd, #S3C2410_UFSTAT_TXFULL
532 @ busy waiting for non fifo
533 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
534 tst \rd, #S3C2410_UTRSTAT_TXFE
537 1002: @ exit busyuart
540 .macro waituart,rd,rx
542 ldr \rd, [ \rx, # S3C2410_UFCON ]
543 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
547 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
548 ands \rd, \rd, #15<<S3C2410_UFSTAT_TXSHIFT
553 @ idle waiting for non fifo
554 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
555 tst \rd, #S3C2410_UTRSTAT_TXFE
558 1002: @ exit busyuart
561 #elif defined(CONFIG_ARCH_LH7A40X)
562 @ It is not known if this will be appropriate for every 40x
566 mrc p15, 0, \rx, c1, c0
567 tst \rx, #1 @ MMU enabled?
568 mov \rx, #0x00000700 @ offset from base
569 orreq \rx, \rx, #0x80000000 @ physical base
570 orrne \rx, \rx, #0xf8000000 @ virtual base
573 .macro senduart,rd,rx
574 strb \rd, [\rx] @ DATA
577 .macro busyuart,rd,rx @ spin while busy
578 1001: ldr \rd, [\rx, #0x10] @ STATUS
579 tst \rd, #1 << 3 @ BUSY (TX FIFO not empty)
580 bne 1001b @ yes, spin
583 .macro waituart,rd,rx @ wait for Tx FIFO room
584 1001: ldrb \rd, [\rx, #0x10] @ STATUS
585 tst \rd, #1 << 5 @ TXFF (TX FIFO full)
586 bne 1001b @ yes, spin
590 #elif defined(CONFIG_ARCH_VERSATILE_PB)
592 #include <asm/hardware/amba_serial.h>
595 mrc p15, 0, \rx, c1, c0
596 tst \rx, #1 @ MMU enabled?
597 moveq \rx, #0x10000000
598 movne \rx, #0xf1000000 @ virtual base
599 orr \rx, \rx, #0x001F0000
600 orr \rx, \rx, #0x00001000
603 .macro senduart,rd,rx
604 strb \rd, [\rx, #UART01x_DR]
607 .macro waituart,rd,rx
608 1001: ldr \rd, [\rx, #0x18] @ UARTFLG
609 tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
613 .macro busyuart,rd,rx
614 1001: ldr \rd, [\rx, #0x18] @ UARTFLG
615 tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
619 #error Unknown architecture
623 * Useful debugging routines
635 printhex: adr r2, hexbuf
643 addge r1, r1, #'a' - 10