2 * linux/arch/arm/kernel/head-armv.S
4 * Copyright (C) 1994-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Kernel startup code for all 32-bit CPUs
12 #include <linux/config.h>
13 #include <linux/linkage.h>
14 #include <linux/init.h>
16 #include <asm/assembler.h>
17 #include <asm/mach-types.h>
18 #include <asm/procinfo.h>
19 #include <asm/ptrace.h>
20 #include <asm/constants.h>
23 * We place the page tables 16K below TEXTADDR. Therefore, we must make sure
24 * that TEXTADDR is correctly set. Currently, we expect the least significant
25 * 16 bits to be 0x8000, but we could probably relax this restriction to
26 * TEXTADDR > PAGE_OFFSET + 0x4000
28 * Note that swapper_pg_dir is the virtual address of the page tables, and
29 * pgtbl gives us a position-independent reference to these tables. We can
30 * do this because stext == TEXTADDR
32 * swapper_pg_dir, pgtbl and krnladr are all closely related.
34 #if (TEXTADDR & 0xffff) != 0x8000
35 #error TEXTADDR must start at 0xXXXX8000
39 .equ swapper_pg_dir, TEXTADDR - 0x4000
43 sub \reg, \reg, #0x4000
47 * Since the page table is closely related to the kernel start address, we
48 * can convert the page table base address to the base address of the section
51 .macro krnladr, rd, pgtable
52 bic \rd, \pgtable, #0x000ff000
56 * Kernel startup entry point.
57 * ---------------------------
59 * This is normally called from the decompressor code. The requirements
60 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
63 * This code is mostly position independent, so if you link the kernel at
64 * 0xc0008000, you call this at __pa(0xc0008000).
66 * See linux/arch/arm/tools/mach-types for the complete list of machine
69 * We're trying to keep crap to a minimum; DO NOT add any machine specific
70 * crap here - that's what the boot loader (or in extreme, well justified
71 * circumstances, zImage) is for.
74 .type stext, #function
77 mov r0, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ make sure svc mode
78 msr cpsr_c, r0 @ and all irqs disabled
79 bl __lookup_processor_type
80 teq r10, #0 @ invalid processor?
81 moveq r0, #'p' @ yes, error 'p'
83 bl __lookup_architecture_type
84 teq r7, #0 @ invalid architecture?
85 moveq r0, #'a' @ yes, error 'a'
87 bl __create_page_tables
90 * The following calls CPU specific code in a position independent
91 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
92 * xxx_proc_info structure selected by __lookup_architecture_type
93 * above. On return, the CPU will be ready for the MMU to be
94 * turned on, and r0 will hold the CPU control register value.
96 adr lr, __turn_mmu_on @ return (PIC) address
99 .type __switch_data, %object
101 .long __mmap_switched
102 .long __bss_start @ r4
104 .long processor_id @ r6
105 .long __machine_arch_type @ r7
106 .long cr_alignment @ r8
107 .long init_thread_union+8192 @ sp
110 * Enable the MMU. This completely changes the structure of the visible
111 * memory space. You will not be able to trace execution through this.
112 * If you have an enquiry about this, *please* check the linux-arm-kernel
113 * mailing list archives BEFORE sending another post to the list.
116 .type __turn_mmu_on, %function
118 ldr lr, __switch_data
119 #ifdef CONFIG_ALIGNMENT_TRAP
120 orr r0, r0, #2 @ ...........A.
122 mcr p15, 0, r0, c1, c0, 0 @ write control reg
123 mrc p15, 0, r3, c0, c0, 0 @ read id reg
129 * The following fragment of code is executed with the MMU on, and uses
130 * absolute addresses; this is not position independent.
132 * r0 = processor control register
135 * r12 = value of r0 when kernel was called (currently always zero)
139 adr r3, __switch_data + 4
140 ldmia r3, {r4, r5, r6, r7, r8, sp}
141 mov fp, #0 @ Clear BSS (and zero fp)
145 str r9, [r6] @ Save processor ID
146 str r1, [r7] @ Save machine type
147 bic r2, r0, #2 @ Clear 'A' bit
148 stmia r8, {r0, r2} @ Save control register values
155 * Setup the initial page tables. We only setup the barest
156 * amount which are required to get the kernel running, which
157 * generally means mapping in the kernel code.
159 * We only map in 4MB of RAM, which should be sufficient in
162 * r5 = physical address of start of RAM
163 * r6 = physical IO address
164 * r7 = byte offset into page tables for IO
165 * r8 = page table flags
167 __create_page_tables:
168 pgtbl r4 @ page table address
171 * Clear the 16K level 1 swapper page table
184 * Create identity mapping for first MB of kernel to
185 * cater for the MMU enable. This identity mapping
186 * will be removed by paging_init()
188 krnladr r2, r4 @ start of kernel
189 add r3, r8, r2 @ flags + kernel base
190 str r3, [r4, r2, lsr #18] @ identity mapping
193 * Now setup the pagetables for our kernel direct
194 * mapped region. We round TEXTADDR down to the
195 * nearest megabyte boundary.
197 add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel
198 bic r2, r3, #0x00f00000
199 str r2, [r0] @ PAGE_OFFSET + 0MB
200 add r0, r0, #(TEXTADDR & 0x00f00000) >> 18
201 str r3, [r0], #4 @ KERNEL + 0MB
203 str r3, [r0], #4 @ KERNEL + 1MB
205 str r3, [r0], #4 @ KERNEL + 2MB
207 str r3, [r0], #4 @ KERNEL + 3MB
209 bic r8, r8, #0x0c @ turn off cacheable
210 @ and bufferable bits
211 #ifdef CONFIG_DEBUG_LL
213 * Map in IO space for serial debugging.
214 * This allows debug messages to be output
215 * via a serial console before paging_init.
218 rsb r3, r7, #0x4000 @ PTRS_PER_PGD*sizeof(long)
220 addge r2, r0, #0x0800
227 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
229 * If we're using the NetWinder, we need to map in
230 * the 16550-type serial port for the debug messages
232 teq r1, #MACH_TYPE_NETWINDER
233 teqne r1, #MACH_TYPE_CATS
235 add r0, r4, #0x3fc0 @ ff000000
244 #ifdef CONFIG_ARCH_RPC
246 * Map in screen at 0x02000000 & SCREEN2_BASE
247 * Similar reasons here - for debug. This is
248 * only for Acorn RiscPC architectures.
250 add r0, r4, #0x80 @ 02000000
254 add r0, r4, #0x3600 @ d8000000
262 * Exception handling. Something went wrong and we can't proceed. We
263 * ought to tell the user, but since we don't have any guarantee that
264 * we're even running on the right architecture, we do virtually nothing.
266 * r0 = ascii error character:
267 * a = invalid architecture
268 * p = invalid processor
269 * i = invalid calling convention
271 * Generally, only serious errors cause this.
274 #ifdef CONFIG_DEBUG_LL
275 mov r8, r0 @ preserve r0
281 #ifdef CONFIG_ARCH_RPC
283 * Turn the screen red on a error - RiscPC only.
287 orr r3, r3, r3, lsl #8
288 orr r3, r3, r3, lsl #16
297 #ifdef CONFIG_DEBUG_LL
304 * Read processor ID register (CP#15, CR0), and look up in the linker-built
305 * supported processor list. Note that we can't use the absolute addresses
306 * for the __proc_info lists since we aren't running with the MMU on
307 * (and therefore, we are not in the correct address space). We have to
308 * calculate the offset.
311 * r5, r6, r7 corrupted
312 * r8 = page table flags
314 * r10 = pointer to processor structure
316 __lookup_processor_type:
318 ldmia r5, {r7, r9, r10}
319 sub r5, r5, r10 @ convert addresses
320 add r7, r7, r5 @ to our address space
322 mrc p15, 0, r9, c0, c0 @ get processor id
323 1: ldmia r10, {r5, r6, r8} @ value, mask, mmuflags
324 and r6, r6, r9 @ mask wanted bits
327 add r10, r10, #PROC_INFO_SZ @ sizeof(proc_info_list)
330 mov r10, #0 @ unknown processor
334 * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for
335 * more information about the __proc_info and __arch_info structures.
337 2: .long __proc_info_end
338 .long __proc_info_begin
340 .long __arch_info_begin
341 .long __arch_info_end
344 * Lookup machine architecture in the linker-build list of architectures.
345 * Note that we can't use the absolute addresses for the __arch_info
346 * lists since we aren't running with the MMU on (and therefore, we are
347 * not in the correct address space). We have to calculate the offset.
349 * r1 = machine architecture number
351 * r2, r3, r4 corrupted
352 * r5 = physical start address of RAM
353 * r6 = physical address of IO
354 * r7 = byte offset into page tables for IO
356 __lookup_architecture_type:
358 ldmia r4, {r2, r3, r5, r6, r7} @ throw away r2, r3
359 sub r5, r4, r5 @ convert addresses
360 add r4, r6, r5 @ to our address space
362 1: ldr r5, [r4] @ get machine type
363 teq r5, r1 @ matches loader number?
365 add r4, r4, #SIZEOF_MACHINE_DESC @ next machine_desc
368 mov r7, #0 @ unknown architecture
370 2: ldmib r4, {r5, r6, r7} @ found, get results