2 * linux/arch/arm/kernel/head.S
4 * Copyright (C) 1994-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Kernel startup code for all 32-bit CPUs
12 #include <linux/config.h>
13 #include <linux/linkage.h>
14 #include <linux/init.h>
16 #include <asm/assembler.h>
17 #include <asm/mach-types.h>
18 #include <asm/procinfo.h>
19 #include <asm/ptrace.h>
20 #include <asm/constants.h>
22 #ifndef CONFIG_XIP_KERNEL
24 * We place the page tables 16K below TEXTADDR. Therefore, we must make sure
25 * that TEXTADDR is correctly set. Currently, we expect the least significant
26 * 16 bits to be 0x8000, but we could probably relax this restriction to
27 * TEXTADDR >= PAGE_OFFSET + 0x4000
29 * Note that swapper_pg_dir is the virtual address of the page tables, and
30 * pgtbl gives us a position-independent reference to these tables. We can
31 * do this because stext == TEXTADDR
33 #if (TEXTADDR & 0xffff) != 0x8000
34 #error TEXTADDR must start at 0xXXXX8000
38 .equ swapper_pg_dir, TEXTADDR - 0x4000
40 .macro pgtbl, rd, phys
48 * We place the page tables 16K below DATAADDR. Therefore, we must make sure
49 * that DATAADDR is correctly set. Currently, we expect the least significant
50 * 16 bits to be 0x8000, but we could probably relax this restriction to
51 * DATAADDR >= PAGE_OFFSET + 0x4000
53 * Note that pgtbl is meant to return the physical address of swapper_pg_dir.
54 * We can't make it relative to the kernel position in this case since
55 * the kernel can physically be anywhere.
57 #if (DATAADDR & 0xffff) != 0x8000
58 #error DATAADDR must start at 0xXXXX8000
62 .equ swapper_pg_dir, DATAADDR - 0x4000
64 .macro pgtbl, rd, phys
65 ldr \rd, =((DATAADDR - 0x4000) - VIRT_OFFSET)
71 * Kernel startup entry point.
72 * ---------------------------
74 * This is normally called from the decompressor code. The requirements
75 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
78 * This code is mostly position independent, so if you link the kernel at
79 * 0xc0008000, you call this at __pa(0xc0008000).
81 * See linux/arch/arm/tools/mach-types for the complete list of machine
84 * We're trying to keep crap to a minimum; DO NOT add any machine specific
85 * crap here - that's what the boot loader (or in extreme, well justified
86 * circumstances, zImage) is for.
89 .type stext, #function
92 mov r0, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ make sure svc mode
93 msr cpsr_c, r0 @ and all irqs disabled
94 bl __lookup_processor_type
95 teq r10, #0 @ invalid processor?
96 moveq r0, #'p' @ yes, error 'p'
98 bl __lookup_architecture_type
99 teq r7, #0 @ invalid architecture?
100 moveq r0, #'a' @ yes, error 'a'
102 bl __create_page_tables
105 * The following calls CPU specific code in a position independent
106 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
107 * xxx_proc_info structure selected by __lookup_architecture_type
108 * above. On return, the CPU will be ready for the MMU to be
109 * turned on, and r0 will hold the CPU control register value.
111 adr lr, __turn_mmu_on @ return (PIC) address
114 .type __switch_data, %object
116 .long __mmap_switched
117 .long __data_loc @ r2
118 .long __data_start @ r3
119 .long __bss_start @ r4
121 .long processor_id @ r6
122 .long __machine_arch_type @ r7
123 .long cr_alignment @ r8
124 .long init_thread_union+8192 @ sp
127 * Enable the MMU. This completely changes the structure of the visible
128 * memory space. You will not be able to trace execution through this.
129 * If you have an enquiry about this, *please* check the linux-arm-kernel
130 * mailing list archives BEFORE sending another post to the list.
133 .type __turn_mmu_on, %function
135 ldr lr, __switch_data
136 #ifdef CONFIG_ALIGNMENT_TRAP
137 orr r0, r0, #2 @ ...........A.
139 mcr p15, 0, r0, c1, c0, 0 @ write control reg
140 mrc p15, 0, r3, c0, c0, 0 @ read id reg
146 * The following fragment of code is executed with the MMU on, and uses
147 * absolute addresses; this is not position independent.
149 * r0 = processor control register
152 * r12 = value of r0 when kernel was called (currently always zero)
156 adr r2, __switch_data + 4
157 ldmia r2, {r2, r3, r4, r5, r6, r7, r8, sp}
159 cmp r2, r3 @ Copy data segment if needed
165 mov fp, #0 @ Clear BSS (and zero fp)
170 str r9, [r6] @ Save processor ID
171 str r1, [r7] @ Save machine type
172 bic r2, r0, #2 @ Clear 'A' bit
173 stmia r8, {r0, r2} @ Save control register values
180 * Setup the initial page tables. We only setup the barest
181 * amount which are required to get the kernel running, which
182 * generally means mapping in the kernel code.
184 * r5 = physical address of start of RAM
185 * r6 = physical IO address
186 * r7 = byte offset into page tables for IO
187 * r8 = page table flags
189 __create_page_tables:
190 pgtbl r4, r5 @ page table address
193 * Clear the 16K level 1 swapper page table
206 * Create identity mapping for first MB of kernel to
207 * cater for the MMU enable. This identity mapping
208 * will be removed by paging_init(). We use our current program
209 * counter to determine corresponding section base address.
211 mov r2, pc, lsr #20 @ start of kernel section
212 add r3, r8, r2, lsl #20 @ flags + kernel base
213 str r3, [r4, r2, lsl #2] @ identity mapping
216 * Now setup the pagetables for our kernel direct
217 * mapped region. We round TEXTADDR down to the
218 * nearest megabyte boundary. It is assumed that
219 * the kernel fits within 4 contigous 1MB sections.
221 add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel
222 str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]!
224 str r3, [r0, #4]! @ KERNEL + 1MB
226 str r3, [r0, #4]! @ KERNEL + 2MB
228 str r3, [r0, #4] @ KERNEL + 3MB
231 * Then map first 1MB of ram in case it contains our boot params.
233 add r0, r4, #VIRT_OFFSET >> 18
237 #ifdef CONFIG_XIP_KERNEL
239 * Map some ram to cover our .data and .bss areas.
240 * Mapping 3MB should be plenty.
244 add r0, r0, r3, lsl #2
245 add r2, r2, r3, lsl #20
247 add r2, r2, #(1 << 20)
249 add r2, r2, #(1 << 20)
253 bic r8, r8, #0x0c @ turn off cacheable
254 @ and bufferable bits
255 #ifdef CONFIG_DEBUG_LL
257 * Map in IO space for serial debugging.
258 * This allows debug messages to be output
259 * via a serial console before paging_init.
262 rsb r3, r7, #0x4000 @ PTRS_PER_PGD*sizeof(long)
264 addge r2, r0, #0x0800
271 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
273 * If we're using the NetWinder, we need to map in
274 * the 16550-type serial port for the debug messages
276 teq r1, #MACH_TYPE_NETWINDER
277 teqne r1, #MACH_TYPE_CATS
279 add r0, r4, #0x3fc0 @ ff000000
288 #ifdef CONFIG_ARCH_RPC
290 * Map in screen at 0x02000000 & SCREEN2_BASE
291 * Similar reasons here - for debug. This is
292 * only for Acorn RiscPC architectures.
294 add r0, r4, #0x80 @ 02000000
298 add r0, r4, #0x3600 @ d8000000
307 * Exception handling. Something went wrong and we can't proceed. We
308 * ought to tell the user, but since we don't have any guarantee that
309 * we're even running on the right architecture, we do virtually nothing.
311 * r0 = ascii error character:
312 * a = invalid architecture
313 * p = invalid processor
314 * i = invalid calling convention
316 * Generally, only serious errors cause this.
319 #ifdef CONFIG_DEBUG_LL
320 mov r8, r0 @ preserve r0
326 #ifdef CONFIG_ARCH_RPC
328 * Turn the screen red on a error - RiscPC only.
332 orr r3, r3, r3, lsl #8
333 orr r3, r3, r3, lsl #16
342 #ifdef CONFIG_DEBUG_LL
349 * Read processor ID register (CP#15, CR0), and look up in the linker-built
350 * supported processor list. Note that we can't use the absolute addresses
351 * for the __proc_info lists since we aren't running with the MMU on
352 * (and therefore, we are not in the correct address space). We have to
353 * calculate the offset.
356 * r5, r6, r7 corrupted
357 * r8 = page table flags
359 * r10 = pointer to processor structure
361 __lookup_processor_type:
363 ldmia r5, {r7, r9, r10}
364 sub r5, r5, r10 @ convert addresses
365 add r7, r7, r5 @ to our address space
367 mrc p15, 0, r9, c0, c0 @ get processor id
368 1: ldmia r10, {r5, r6, r8} @ value, mask, mmuflags
369 and r6, r6, r9 @ mask wanted bits
372 add r10, r10, #PROC_INFO_SZ @ sizeof(proc_info_list)
375 mov r10, #0 @ unknown processor
379 * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for
380 * more information about the __proc_info and __arch_info structures.
382 2: .long __proc_info_end
383 .long __proc_info_begin
385 .long __arch_info_begin
386 .long __arch_info_end
389 * Lookup machine architecture in the linker-build list of architectures.
390 * Note that we can't use the absolute addresses for the __arch_info
391 * lists since we aren't running with the MMU on (and therefore, we are
392 * not in the correct address space). We have to calculate the offset.
394 * r1 = machine architecture number
396 * r2, r3, r4 corrupted
397 * r5 = physical start address of RAM
398 * r6 = physical address of IO
399 * r7 = byte offset into page tables for IO
401 __lookup_architecture_type:
403 ldmia r4, {r2, r3, r5, r6, r7} @ throw away r2, r3
404 sub r5, r4, r5 @ convert addresses
405 add r4, r6, r5 @ to our address space
407 1: ldr r5, [r4] @ get machine type
408 teq r5, r1 @ matches loader number?
410 add r4, r4, #SIZEOF_MACHINE_DESC @ next machine_desc
413 mov r7, #0 @ unknown architecture
415 2: ldmib r4, {r5, r6, r7} @ found, get results