2 * linux/arch/arm/mach-ebsa110/isamem.c
4 * Copyright (C) 2001 Russell King
6 * Perform "ISA" memory and IO accesses. The EBSA110 has some "peculiarities"
7 * in the way it handles accesses to odd IO ports on 16-bit devices. These
8 * devices have their D0-D15 lines connected to the processors D0-D15 lines.
9 * Since they expect all byte IO operations to be performed on D0-D7, and the
10 * StrongARM expects to transfer the byte to these odd addresses on D8-D15,
11 * we must use a trick to get the required behaviour.
13 * The trick employed here is to use long word stores to odd address -1. The
14 * glue logic picks this up as a "trick" access, and asserts the LSB of the
15 * peripherals address bus, thereby accessing the odd IO port. Meanwhile, the
16 * StrongARM transfers its data on D0-D7 as expected.
18 * Things get more interesting on the pass-1 EBSA110 - the PCMCIA controller
19 * wiring was screwed in such a way that it had limited memory space access.
20 * Luckily, the work-around for this is not too horrible. See
21 * __isamem_convert_addr for the details.
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/types.h>
30 static void __iomem *__isamem_convert_addr(void __iomem *addr)
32 u32 ret, a = (u32 __force) addr;
35 * The PCMCIA controller is wired up as follows:
36 * +---------+---------+---------+---------+---------+---------+
37 * PCMCIA | 2 2 2 2 | 1 1 1 1 | 1 1 1 1 | 1 1 | | |
38 * | 3 2 1 0 | 9 8 7 6 | 5 4 3 2 | 1 0 9 8 | 7 6 5 4 | 3 2 1 0 |
39 * +---------+---------+---------+---------+---------+---------+
40 * CPU | 2 2 2 2 | 2 1 1 1 | 1 1 1 1 | 1 1 1 | | |
41 * | 4 3 2 1 | 0 9 9 8 | 7 6 5 4 | 3 2 0 9 | 8 7 6 5 | 4 3 2 x |
42 * +---------+---------+---------+---------+---------+---------+
44 * This means that we can access PCMCIA regions as follows:
45 * 0x*10000 -> 0x*1ffff
46 * 0x*70000 -> 0x*7ffff
47 * 0x*90000 -> 0x*9ffff
48 * 0x*f0000 -> 0x*fffff
50 ret = (a & 0xf803fe) << 1;
51 ret |= (a & 0x03fc00) << 2;
55 if ((a & 0x20000) == (a & 0x40000) >> 1)
56 return (void __iomem *)ret;
63 * read[bwl] and write[bwl]
65 u8 __readb(void __iomem *addr)
67 void __iomem *a = __isamem_convert_addr(addr);
70 if ((unsigned long)addr & 1)
77 u16 __readw(void __iomem *addr)
79 void __iomem *a = __isamem_convert_addr(addr);
81 if ((unsigned long)addr & 1)
84 return __raw_readw(a);
87 u32 __readl(void __iomem *addr)
89 void __iomem *a = __isamem_convert_addr(addr);
92 if ((unsigned long)addr & 3)
96 ret |= __raw_readw(a + 4) << 16;
100 EXPORT_SYMBOL(__readb);
101 EXPORT_SYMBOL(__readw);
102 EXPORT_SYMBOL(__readl);
104 void __writeb(u8 val, void __iomem *addr)
106 void __iomem *a = __isamem_convert_addr(addr);
108 if ((unsigned long)addr & 1)
109 __raw_writel(val, a);
111 __raw_writeb(val, a);
114 void __writew(u16 val, void __iomem *addr)
116 void __iomem *a = __isamem_convert_addr(addr);
118 if ((unsigned long)addr & 1)
121 __raw_writew(val, a);
124 void __writel(u32 val, void __iomem *addr)
126 void __iomem *a = __isamem_convert_addr(addr);
128 if ((unsigned long)addr & 3)
131 __raw_writew(val, a);
132 __raw_writew(val >> 16, a + 4);
135 EXPORT_SYMBOL(__writeb);
136 EXPORT_SYMBOL(__writew);
137 EXPORT_SYMBOL(__writel);
139 #define SUPERIO_PORT(p) \
140 (((p) >> 3) == (0x3f8 >> 3) || \
141 ((p) >> 3) == (0x2f8 >> 3) || \
142 ((p) >> 3) == (0x378 >> 3))
145 * We're addressing an 8 or 16-bit peripheral which tranfers
146 * odd addresses on the low ISA byte lane.
148 u8 __inb8(unsigned int port)
153 * The SuperIO registers use sane addressing techniques...
155 if (SUPERIO_PORT(port))
156 ret = __raw_readb(ISAIO_BASE + (port << 2));
158 void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
161 * Shame nothing else does
164 ret = __raw_readl(a);
166 ret = __raw_readb(a);
172 * We're addressing a 16-bit peripheral which transfers odd
173 * addresses on the high ISA byte lane.
175 u8 __inb16(unsigned int port)
180 * The SuperIO registers use sane addressing techniques...
182 if (SUPERIO_PORT(port))
183 ret = __raw_readb(ISAIO_BASE + (port << 2));
185 void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
188 * Shame nothing else does
190 ret = __raw_readb(a + (port & 1));
195 u16 __inw(unsigned int port)
200 * The SuperIO registers use sane addressing techniques...
202 if (SUPERIO_PORT(port))
203 ret = __raw_readw(ISAIO_BASE + (port << 2));
205 void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
208 * Shame nothing else does
213 ret = __raw_readw(a);
219 * Fake a 32-bit read with two 16-bit reads. Needed for 3c589.
221 u32 __inl(unsigned int port)
225 if (SUPERIO_PORT(port) || port & 3)
228 a = ISAIO_BASE + (port << 1);
230 return __raw_readw(a) | __raw_readw(a + 4) << 16;
233 EXPORT_SYMBOL(__inb8);
234 EXPORT_SYMBOL(__inb16);
235 EXPORT_SYMBOL(__inw);
236 EXPORT_SYMBOL(__inl);
238 void __outb8(u8 val, unsigned int port)
241 * The SuperIO registers use sane addressing techniques...
243 if (SUPERIO_PORT(port))
244 __raw_writeb(val, ISAIO_BASE + (port << 2));
246 void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
249 * Shame nothing else does
252 __raw_writel(val, a);
254 __raw_writeb(val, a);
258 void __outb16(u8 val, unsigned int port)
261 * The SuperIO registers use sane addressing techniques...
263 if (SUPERIO_PORT(port))
264 __raw_writeb(val, ISAIO_BASE + (port << 2));
266 void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
269 * Shame nothing else does
271 __raw_writeb(val, a + (port & 1));
275 void __outw(u16 val, unsigned int port)
280 * The SuperIO registers use sane addressing techniques...
282 if (SUPERIO_PORT(port))
290 __raw_writew(val, ISAIO_BASE + off);
293 void __outl(u32 val, unsigned int port)
298 EXPORT_SYMBOL(__outb8);
299 EXPORT_SYMBOL(__outb16);
300 EXPORT_SYMBOL(__outw);
301 EXPORT_SYMBOL(__outl);
303 extern void __arch_writesb(unsigned long virt, const void *from, int len);
304 extern void __arch_writesw(unsigned long virt, const void *from, int len);
305 extern void __arch_writesl(unsigned long virt, const void *from, int len);
306 extern void __arch_readsb(unsigned long virt, void *from, int len);
307 extern void __arch_readsw(unsigned long virt, void *from, int len);
308 extern void __arch_readsl(unsigned long virt, void *from, int len);
310 void outsb(unsigned int port, const void *from, int len)
314 if (SUPERIO_PORT(port))
317 off = (port & ~1) << 1;
322 __raw_writesb(ISAIO_BASE + off, from, len);
325 void insb(unsigned int port, void *from, int len)
329 if (SUPERIO_PORT(port))
332 off = (port & ~1) << 1;
337 __raw_readsb(ISAIO_BASE + off, from, len);
340 EXPORT_SYMBOL(outsb);
343 void outsw(unsigned int port, const void *from, int len)
347 if (SUPERIO_PORT(port))
350 off = (port & ~1) << 1;
355 __raw_writesw(ISAIO_BASE + off, from, len);
358 void insw(unsigned int port, void *from, int len)
362 if (SUPERIO_PORT(port))
365 off = (port & ~1) << 1;
370 __raw_readsw(ISAIO_BASE + off, from, len);
373 EXPORT_SYMBOL(outsw);
377 * We implement these as 16-bit insw/outsw, mainly for
380 void outsl(unsigned int port, const void *from, int len)
384 if (SUPERIO_PORT(port) || port & 3)
387 __raw_writesw(ISAIO_BASE + off, from, len << 1);
390 void insl(unsigned int port, void *from, int len)
394 if (SUPERIO_PORT(port) || port & 3)
397 __raw_readsw(ISAIO_BASE + off, from, len << 1);
400 EXPORT_SYMBOL(outsl);