2 * linux/arch/arm/mach-integrator/integrator_ap.c
4 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/device.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/sysdev.h>
29 #include <asm/hardware.h>
32 #include <asm/setup.h>
33 #include <asm/mach-types.h>
34 #include <asm/hardware/amba.h>
35 #include <asm/hardware/amba_kmi.h>
37 #include <asm/arch/lm.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/flash.h>
41 #include <asm/mach/irq.h>
42 #include <asm/mach/map.h>
43 #include <asm/mach/time.h>
48 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
51 * Setup a VA for the Integrator interrupt controller (for header #0,
54 #define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
55 #define VA_SC_BASE IO_ADDRESS(INTEGRATOR_SC_BASE)
56 #define VA_EBI_BASE IO_ADDRESS(INTEGRATOR_EBI_BASE)
57 #define VA_CMIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_IC_OFFSET
61 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
62 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
63 * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
64 * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
65 * ef000000 Cache flush
66 * f1000000 10000000 Core module registers
67 * f1100000 11000000 System controller registers
68 * f1200000 12000000 EBI registers
69 * f1300000 13000000 Counter/Timer
70 * f1400000 14000000 Interrupt controller
71 * f1500000 15000000 RTC
72 * f1600000 16000000 UART 0
73 * f1700000 17000000 UART 1
74 * f1a00000 1a000000 Debug LEDs
75 * f1b00000 1b000000 GPIO
78 static struct map_desc ap_io_desc[] __initdata = {
79 { IO_ADDRESS(INTEGRATOR_HDR_BASE), INTEGRATOR_HDR_BASE, SZ_4K, MT_DEVICE },
80 { IO_ADDRESS(INTEGRATOR_SC_BASE), INTEGRATOR_SC_BASE, SZ_4K, MT_DEVICE },
81 { IO_ADDRESS(INTEGRATOR_EBI_BASE), INTEGRATOR_EBI_BASE, SZ_4K, MT_DEVICE },
82 { IO_ADDRESS(INTEGRATOR_CT_BASE), INTEGRATOR_CT_BASE, SZ_4K, MT_DEVICE },
83 { IO_ADDRESS(INTEGRATOR_IC_BASE), INTEGRATOR_IC_BASE, SZ_4K, MT_DEVICE },
84 { IO_ADDRESS(INTEGRATOR_RTC_BASE), INTEGRATOR_RTC_BASE, SZ_4K, MT_DEVICE },
85 { IO_ADDRESS(INTEGRATOR_UART0_BASE), INTEGRATOR_UART0_BASE, SZ_4K, MT_DEVICE },
86 { IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K, MT_DEVICE },
87 { IO_ADDRESS(INTEGRATOR_DBG_BASE), INTEGRATOR_DBG_BASE, SZ_4K, MT_DEVICE },
88 { IO_ADDRESS(INTEGRATOR_GPIO_BASE), INTEGRATOR_GPIO_BASE, SZ_4K, MT_DEVICE },
89 { PCI_MEMORY_VADDR, PHYS_PCI_MEM_BASE, SZ_16M, MT_DEVICE },
90 { PCI_CONFIG_VADDR, PHYS_PCI_CONFIG_BASE, SZ_16M, MT_DEVICE },
91 { PCI_V3_VADDR, PHYS_PCI_V3_BASE, SZ_64K, MT_DEVICE },
92 { PCI_IO_VADDR, PHYS_PCI_IO_BASE, SZ_64K, MT_DEVICE }
95 static void __init ap_map_io(void)
97 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
100 #define INTEGRATOR_SC_VALID_INT 0x003fffff
102 static void sc_mask_irq(unsigned int irq)
104 writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_CLEAR);
107 static void sc_unmask_irq(unsigned int irq)
109 writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_SET);
112 static struct irqchip sc_chip = {
115 .unmask = sc_unmask_irq,
118 static void __init ap_init_irq(void)
122 /* Disable all interrupts initially. */
123 /* Do the core module ones */
124 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
126 /* do the header card stuff next */
127 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
128 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
130 for (i = 0; i < NR_IRQS; i++) {
131 if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) {
132 set_irq_chip(i, &sc_chip);
133 set_irq_handler(i, do_level_IRQ);
134 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
140 static unsigned long ic_irq_enable;
142 static int irq_suspend(struct sys_device *dev, u32 state)
144 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
148 static int irq_resume(struct sys_device *dev)
150 /* disable all irq sources */
151 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
152 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
153 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
155 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
159 #define irq_suspend NULL
160 #define irq_resume NULL
163 static struct sysdev_class irq_class = {
164 set_kset_name("irq"),
165 .suspend = irq_suspend,
166 .resume = irq_resume,
169 static struct sys_device irq_device = {
174 static int __init irq_init_sysfs(void)
176 int ret = sysdev_class_register(&irq_class);
178 ret = sysdev_register(&irq_device);
182 device_initcall(irq_init_sysfs);
187 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
188 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
189 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
190 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
192 static int ap_flash_init(void)
196 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
198 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
199 writel(tmp, EBI_CSR1);
201 if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
202 writel(0xa05f, EBI_LOCK);
203 writel(tmp, EBI_CSR1);
209 static void ap_flash_exit(void)
213 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
215 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
216 writel(tmp, EBI_CSR1);
218 if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
219 writel(0xa05f, EBI_LOCK);
220 writel(tmp, EBI_CSR1);
225 static void ap_flash_set_vpp(int on)
227 unsigned long reg = on ? SC_CTRLS : SC_CTRLC;
229 writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
232 static struct flash_platform_data ap_flash_data = {
233 .map_name = "cfi_probe",
235 .init = ap_flash_init,
236 .exit = ap_flash_exit,
237 .set_vpp = ap_flash_set_vpp,
240 static struct resource cfi_flash_resource = {
241 .start = INTEGRATOR_FLASH_BASE,
242 .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
243 .flags = IORESOURCE_MEM,
246 static struct platform_device cfi_flash_device = {
250 .platform_data = &ap_flash_data,
253 .resource = &cfi_flash_resource,
256 static void __init ap_init(void)
258 unsigned long sc_dec;
261 platform_device_register(&cfi_flash_device);
263 sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
264 for (i = 0; i < 4; i++) {
265 struct lm_device *lmdev;
267 if ((sc_dec & (16 << i)) == 0)
270 lmdev = kmalloc(sizeof(struct lm_device), GFP_KERNEL);
274 memset(lmdev, 0, sizeof(struct lm_device));
276 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
277 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
278 lmdev->resource.flags = IORESOURCE_MEM;
279 lmdev->irq = IRQ_AP_EXPINT0 + i;
282 lm_device_register(lmdev);
286 static void __init ap_init_timer(void)
288 integrator_time_init(1000000 * TICKS_PER_uSEC / HZ, 0);
291 static struct sys_timer ap_timer = {
292 .init = ap_init_timer,
293 .offset = integrator_gettimeoffset,
296 MACHINE_START(INTEGRATOR, "ARM-Integrator")
297 MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd")
298 BOOT_MEM(0x00000000, 0x16000000, 0xf1600000)
299 BOOT_PARAMS(0x00000100)
303 INIT_MACHINE(ap_init)