2 * linux/arch/arm/mach-integrator/integrator_cp.c
4 * Copyright (C) 2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
16 #include <linux/string.h>
17 #include <linux/sysdev.h>
19 #include <asm/hardware.h>
22 #include <asm/setup.h>
23 #include <asm/mach-types.h>
24 #include <asm/hardware/amba.h>
25 #include <asm/hardware/amba_kmi.h>
27 #include <asm/arch/lm.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/flash.h>
31 #include <asm/mach/irq.h>
32 #include <asm/mach/mmc.h>
33 #include <asm/mach/map.h>
35 #define INTCP_PA_MMC_BASE 0x1c000000
36 #define INTCP_PA_AACI_BASE 0x1d000000
38 #define INTCP_PA_FLASH_BASE 0x24000000
39 #define INTCP_FLASH_SIZE SZ_32M
41 #define INTCP_VA_CIC_BASE 0xf1000040
42 #define INTCP_VA_PIC_BASE 0xf1400000
43 #define INTCP_VA_SIC_BASE 0xfca00000
45 #define INTCP_PA_ETH_BASE 0xc8000000
46 #define INTCP_ETH_SIZE 0x10
48 #define INTCP_VA_CTRL_BASE 0xfcb00000
49 #define INTCP_FLASHPROG 0x04
50 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
51 #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
55 * f1000000 10000000 Core module registers
56 * f1100000 11000000 System controller registers
57 * f1200000 12000000 EBI registers
58 * f1300000 13000000 Counter/Timer
59 * f1400000 14000000 Interrupt controller
60 * f1600000 16000000 UART 0
61 * f1700000 17000000 UART 1
62 * f1a00000 1a000000 Debug LEDs
63 * f1b00000 1b000000 GPIO
66 static struct map_desc intcp_io_desc[] __initdata = {
67 { IO_ADDRESS(INTEGRATOR_HDR_BASE), INTEGRATOR_HDR_BASE, SZ_4K, MT_DEVICE },
68 { IO_ADDRESS(INTEGRATOR_SC_BASE), INTEGRATOR_SC_BASE, SZ_4K, MT_DEVICE },
69 { IO_ADDRESS(INTEGRATOR_EBI_BASE), INTEGRATOR_EBI_BASE, SZ_4K, MT_DEVICE },
70 { IO_ADDRESS(INTEGRATOR_CT_BASE), INTEGRATOR_CT_BASE, SZ_4K, MT_DEVICE },
71 { IO_ADDRESS(INTEGRATOR_IC_BASE), INTEGRATOR_IC_BASE, SZ_4K, MT_DEVICE },
72 { IO_ADDRESS(INTEGRATOR_UART0_BASE), INTEGRATOR_UART0_BASE, SZ_4K, MT_DEVICE },
73 { IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K, MT_DEVICE },
74 { IO_ADDRESS(INTEGRATOR_DBG_BASE), INTEGRATOR_DBG_BASE, SZ_4K, MT_DEVICE },
75 { IO_ADDRESS(INTEGRATOR_GPIO_BASE), INTEGRATOR_GPIO_BASE, SZ_4K, MT_DEVICE },
76 { 0xfc900000, 0xc9000000, SZ_4K, MT_DEVICE },
77 { 0xfca00000, 0xca000000, SZ_4K, MT_DEVICE },
78 { 0xfcb00000, 0xcb000000, SZ_4K, MT_DEVICE },
81 static void __init intcp_map_io(void)
83 iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
86 #define cic_writel __raw_writel
87 #define cic_readl __raw_readl
88 #define pic_writel __raw_writel
89 #define pic_readl __raw_readl
90 #define sic_writel __raw_writel
91 #define sic_readl __raw_readl
93 static void cic_mask_irq(unsigned int irq)
96 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
99 static void cic_unmask_irq(unsigned int irq)
101 irq -= IRQ_CIC_START;
102 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
105 static struct irqchip cic_chip = {
107 .mask = cic_mask_irq,
108 .unmask = cic_unmask_irq,
111 static void pic_mask_irq(unsigned int irq)
113 irq -= IRQ_PIC_START;
114 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
117 static void pic_unmask_irq(unsigned int irq)
119 irq -= IRQ_PIC_START;
120 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
123 static struct irqchip pic_chip = {
125 .mask = pic_mask_irq,
126 .unmask = pic_unmask_irq,
129 static void sic_mask_irq(unsigned int irq)
131 irq -= IRQ_SIC_START;
132 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
135 static void sic_unmask_irq(unsigned int irq)
137 irq -= IRQ_SIC_START;
138 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
141 static struct irqchip sic_chip = {
143 .mask = sic_mask_irq,
144 .unmask = sic_unmask_irq,
148 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
150 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
153 do_bad_IRQ(irq, desc, regs);
158 irq = ffs(status) - 1;
159 status &= ~(1 << irq);
161 irq += IRQ_SIC_START;
163 desc = irq_desc + irq;
164 desc->handle(irq, desc, regs);
168 static void __init intcp_init_irq(void)
173 * Disable all interrupt sources
175 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
176 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
178 for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
181 if (i == IRQ_CP_CPPLDINT)
185 set_irq_chip(i, &pic_chip);
186 set_irq_handler(i, do_level_IRQ);
187 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
190 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
191 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
193 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
194 set_irq_chip(i, &cic_chip);
195 set_irq_handler(i, do_level_IRQ);
196 set_irq_flags(i, IRQF_VALID);
199 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
200 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
202 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
203 set_irq_chip(i, &sic_chip);
204 set_irq_handler(i, do_level_IRQ);
205 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
208 set_irq_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
209 pic_unmask_irq(IRQ_CP_CPPLDINT);
215 static int intcp_flash_init(void)
219 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
220 val |= CINTEGRATOR_FLASHPROG_FLWREN;
221 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
226 static void intcp_flash_exit(void)
230 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
231 val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
232 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
235 static void intcp_flash_set_vpp(int on)
239 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
241 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
243 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
244 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
247 static struct flash_platform_data intcp_flash_data = {
248 .map_name = "cfi_probe",
250 .init = intcp_flash_init,
251 .exit = intcp_flash_exit,
252 .set_vpp = intcp_flash_set_vpp,
255 static struct resource intcp_flash_resource = {
256 .start = INTCP_PA_FLASH_BASE,
257 .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
258 .flags = IORESOURCE_MEM,
261 static struct platform_device intcp_flash_device = {
265 .platform_data = &intcp_flash_data,
268 .resource = &intcp_flash_resource,
271 static struct resource smc91x_resources[] = {
273 .start = INTCP_PA_ETH_BASE,
274 .end = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1,
275 .flags = IORESOURCE_MEM,
278 .start = IRQ_CP_ETHINT,
279 .end = IRQ_CP_ETHINT,
280 .flags = IORESOURCE_IRQ,
284 static struct platform_device smc91x_device = {
287 .num_resources = ARRAY_SIZE(smc91x_resources),
288 .resource = smc91x_resources,
291 static struct platform_device *intcp_devs[] __initdata = {
297 * It seems that the card insertion interrupt remains active after
298 * we've acknowledged it. We therefore ignore the interrupt, and
299 * rely on reading it from the SIC. This also means that we must
300 * clear the latched interrupt.
302 static unsigned int mmc_status(struct device *dev)
304 unsigned int status = readl(0xfca00004);
305 writel(8, 0xfcb00008);
310 static struct mmc_platform_data mmc_data = {
312 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
313 .status = mmc_status,
316 static struct amba_device mmc_device = {
319 .platform_data = &mmc_data,
322 .start = INTCP_PA_MMC_BASE,
323 .end = INTCP_PA_MMC_BASE + SZ_4K - 1,
324 .flags = IORESOURCE_MEM,
326 .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
330 static struct amba_device aaci_device = {
335 .start = INTCP_PA_AACI_BASE,
336 .end = INTCP_PA_AACI_BASE + SZ_4K - 1,
337 .flags = IORESOURCE_MEM,
339 .irq = { IRQ_CP_AACIINT, NO_IRQ },
343 static struct amba_device *amba_devs[] __initdata = {
348 static void __init intcp_init(void)
352 platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
354 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
355 struct amba_device *d = amba_devs[i];
356 amba_device_register(d, &iomem_resource);
360 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
361 MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd")
362 BOOT_MEM(0x00000000, 0x16000000, 0xf1600000)
363 BOOT_PARAMS(0x00000100)
365 INITIRQ(intcp_init_irq)
366 INIT_MACHINE(intcp_init)