2 * arch/arm/mach-iop3xx/iop310-pci.c
4 * PCI support for the Intel IOP310 chipset
6 * Matt Porter <mporter@mvista.com>
8 * Copyright (C) 2001 MontaVista Software, Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
23 #include <asm/system.h>
24 #include <asm/hardware.h>
25 #include <asm/mach/pci.h>
27 #include <asm/arch/iop310.h>
30 * *** Special note - why the IOP310 should NOT be used ***
32 * The PCI ATU is a brain dead implementation, only allowing 32-bit
33 * accesses to PCI configuration space. This is especially brain
34 * dead for writes to this space. A simple for-instance:
36 * You want to modify the command register *without* corrupting the
39 * To perform this, you need to read *32* bits of data from offset 4,
40 * mask off the low 16, replace them with the new data, and write *32*
43 * Writing the status register at offset 6 with status bits set *clears*
46 * Hello? Could we have a *SANE* implementation of a PCI ATU some day
51 #define DBG(x...) printk(x)
53 #define DBG(x...) do { } while (0)
57 * Calculate the address, etc from the bus, devfn and register
58 * offset. Note that we have two root buses, so we need some
59 * method to determine whether we need config type 0 or 1 cycles.
60 * We use a root bus number in our bus->sysdata structure for this.
62 static u32 iop310_cfg_address(struct pci_bus *bus, int devfn, int where)
64 struct pci_sys_data *sys = bus->sysdata;
67 if (sys->busnr == bus->number)
68 addr = 1 << (PCI_SLOT(devfn) + 16);
70 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
72 addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
78 * Primary PCI interface support.
80 static int iop310_pri_pci_status(void)
85 status = *IOP310_PATUSR;
86 if (status & 0xf900) {
87 *IOP310_PATUSR = status & 0xf900;
90 status = *IOP310_PATUISR;
91 if (status & 0x0000018f) {
92 *IOP310_PATUISR = status & 0x0000018f;
96 if (status & 0xf900) {
97 *IOP310_PSR = status & 0xf900;
100 status = *IOP310_PBISR;
101 if (status & 0x003f) {
102 *IOP310_PBISR = status & 0x003f;
109 * Simply write the address register and read the configuration
110 * data. Note that the 4 nop's ensure that we are able to handle
111 * a delayed abort (in theory.)
113 static inline u32 iop310_pri_read(unsigned long addr)
117 __asm__ __volatile__(
125 : "r" (addr), "r" (IOP310_POCCAR), "r" (IOP310_POCCDR));
131 iop310_pri_read_config(struct pci_bus *bus, unsigned int devfn, int where,
132 int size, u32 *value)
134 unsigned long addr = iop310_cfg_address(bus, devfn, where);
135 u32 val = iop310_pri_read(addr) >> ((where & 3) * 8);
137 if (iop310_pri_pci_status())
142 return PCIBIOS_SUCCESSFUL;
146 iop310_pri_write_config(struct pci_bus *bus, unsigned int devfn, int where,
149 unsigned long addr = iop310_cfg_address(bus, devfn, where);
153 val = iop310_pri_read(addr);
154 if (!iop310_pri_pci_status() == 0)
155 return PCIBIOS_SUCCESSFUL;
157 where = (where & 3) * 8;
160 val &= ~(0xff << where);
162 val &= ~(0xffff << where);
164 *IOP310_POCCDR = val | value << where;
174 : "r" (value), "r" (addr),
175 "r" (IOP310_POCCAR), "r" (IOP310_POCCDR));
178 return PCIBIOS_SUCCESSFUL;
181 static struct pci_ops iop310_primary_ops = {
182 .read = iop310_pri_read_config,
183 .write = iop310_pri_write_config,
187 * Secondary PCI interface support.
189 static int iop310_sec_pci_status(void)
191 unsigned int usr, uisr;
194 usr = *IOP310_SATUSR;
195 uisr = *IOP310_SATUISR;
197 *IOP310_SATUSR = usr & 0xf900;
200 if (uisr & 0x0000069f) {
201 *IOP310_SATUISR = uisr & 0x0000069f;
205 DBG("ERROR (%08x %08x)", usr, uisr);
210 * Simply write the address register and read the configuration
211 * data. Note that the 4 nop's ensure that we are able to handle
212 * a delayed abort (in theory.)
214 static inline u32 iop310_sec_read(unsigned long addr)
218 __asm__ __volatile__(
226 : "r" (addr), "r" (IOP310_SOCCAR), "r" (IOP310_SOCCDR));
232 iop310_sec_read_config(struct pci_bus *bus, unsigned int devfn, int where,
233 int size, u32 *value)
235 unsigned long addr = iop310_cfg_address(bus, devfn, where);
236 u32 val = iop310_sec_read(addr) >> ((where & 3) * 8);
238 if (iop310_sec_pci_status())
243 return PCIBIOS_SUCCESSFUL;
247 iop310_sec_write_config(struct pci_bus *bus, unsigned int devfn, int where,
250 unsigned long addr = iop310_cfg_address(bus, devfn, where);
254 val = iop310_sec_read(addr);
256 if (!iop310_sec_pci_status() == 0)
257 return PCIBIOS_SUCCESSFUL;
259 where = (where & 3) * 8;
262 val &= ~(0xff << where);
264 val &= ~(0xffff << where);
266 *IOP310_SOCCDR = val | value << where;
276 : "r" (value), "r" (addr),
277 "r" (IOP310_SOCCAR), "r" (IOP310_SOCCDR));
280 return PCIBIOS_SUCCESSFUL;
283 static struct pci_ops iop310_secondary_ops = {
284 .read = iop310_sec_read_config,
285 .write = iop310_sec_write_config,
289 * When a PCI device does not exist during config cycles, the 80200 gets
290 * an external abort instead of returning 0xffffffff. If it was an
291 * imprecise abort, we need to correct the return address to point after
292 * the instruction. Also note that the Xscale manual says:
294 * "if a stall-until-complete LD or ST instruction triggers an
295 * imprecise fault, then that fault will be seen by the program
296 * within 3 instructions."
298 * This does not appear to be the case. With 8 NOPs after the load, we
299 * see the imprecise abort occurring on the STM of iop310_sec_pci_status()
300 * which is about 10 instructions away.
302 * Always trust reality!
305 iop310_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
307 DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
308 addr, fsr, regs->ARM_pc, regs->ARM_lr);
311 * If it was an imprecise abort, then we need to correct the
312 * return address to be _after_ the instruction.
321 * Scan an IOP310 PCI bus. sys->bus defines which bus we scan.
323 struct pci_bus *iop310_scan_bus(int nr, struct pci_sys_data *sys)
328 ops = &iop310_secondary_ops;
330 ops = &iop310_primary_ops;
332 return pci_scan_bus(sys->busnr, ops, sys);
336 * Setup the system data for controller 'nr'. Return 0 if none found,
337 * 1 if found, or negative error.
340 * io_offset - offset between IO resources and PCI bus BARs
341 * mem_offset - offset between mem resources and PCI bus BARs
342 * resource[0] - parent IO resource
343 * resource[1] - parent non-prefetchable memory resource
344 * resource[2] - parent prefetchable memory resource
345 * swizzle - bridge swizzling function
346 * map_irq - irq mapping function
348 * Note that 'io_offset' and 'mem_offset' are left as zero since
349 * the IOP310 doesn't attempt to perform any address translation
350 * on accesses from the host to the bus.
352 int iop310_setup(int nr, struct pci_sys_data *sys)
354 struct resource *res;
359 res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL);
361 panic("PCI: unable to alloc resources");
363 memset(res, 0, sizeof(struct resource) * 2);
367 res[0].start = IOP310_PCIPRI_LOWER_IO + 0x6e000000;
368 res[0].end = IOP310_PCIPRI_LOWER_IO + 0x6e00ffff;
369 res[0].name = "PCI IO Primary";
370 res[0].flags = IORESOURCE_IO;
372 res[1].start = IOP310_PCIPRI_LOWER_MEM;
373 res[1].end = IOP310_PCIPRI_LOWER_MEM + IOP310_PCI_WINDOW_SIZE;
374 res[1].name = "PCI Memory Primary";
375 res[1].flags = IORESOURCE_MEM;
379 res[0].start = IOP310_PCISEC_LOWER_IO + 0x6e000000;
380 res[0].end = IOP310_PCISEC_LOWER_IO + 0x6e00ffff;
381 res[0].name = "PCI IO Secondary";
382 res[0].flags = IORESOURCE_IO;
384 res[1].start = IOP310_PCISEC_LOWER_MEM;
385 res[1].end = IOP310_PCISEC_LOWER_MEM + IOP310_PCI_WINDOW_SIZE;
386 res[1].name = "PCI Memory Secondary";
387 res[1].flags = IORESOURCE_MEM;
391 request_resource(&ioport_resource, &res[0]);
392 request_resource(&iomem_resource, &res[1]);
394 sys->resource[0] = &res[0];
395 sys->resource[1] = &res[1];
396 sys->resource[2] = NULL;
397 sys->io_offset = 0x6e000000;
402 void iop310_init(void)
404 DBG("PCI: Intel 80312 PCI-to-PCI init code.\n");
405 DBG(" ATU secondary: ATUCR =0x%08x\n", *IOP310_ATUCR);
406 DBG(" ATU secondary: SOMWVR=0x%08x SOIOWVR=0x%08x\n",
407 *IOP310_SOMWVR, *IOP310_SOIOWVR);
408 DBG(" ATU secondary: SIABAR=0x%08x SIALR =0x%08x SIATVR=%08x\n",
409 *IOP310_SIABAR, *IOP310_SIALR, *IOP310_SIATVR);
410 DBG(" ATU primary: POMWVR=0x%08x POIOWVR=0x%08x\n",
411 *IOP310_POMWVR, *IOP310_POIOWVR);
412 DBG(" ATU primary: PIABAR=0x%08x PIALR =0x%08x PIATVR=%08x\n",
413 *IOP310_PIABAR, *IOP310_PIALR, *IOP310_PIATVR);
414 DBG(" P2P: PCR=0x%04x BCR=0x%04x EBCR=0x%04x\n",
415 *IOP310_PCR, *IOP310_BCR, *IOP310_EBCR);
418 * Windows have to be carefully opened via a nice set of calls
419 * here or just some direct register fiddling in the board
420 * specific init when we want transactions to occur between the
423 * To do this, we will have manage RETRY assertion between the
424 * firmware and the kernel. This will ensure that the host
425 * system's enumeration code is held off until we have tweaked
426 * the interrupt routing and public/private IDSELs.
428 * For now we will simply default to disabling the integrated type
431 *IOP310_PCR &= 0xfff8;
433 hook_fault_code(16+6, iop310_pci_abort, SIGBUS, "imprecise external abort");