2 * arch/arm/mach-iop3xx/iop321-pci.c
4 * PCI support for the Intel IOP321 chipset
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
23 #include <asm/system.h>
24 #include <asm/hardware.h>
25 #include <asm/mach/pci.h>
27 #include <asm/arch/iop321.h>
32 #define DBG(x...) printk(x)
34 #define DBG(x...) do { } while (0)
38 * This routine builds either a type0 or type1 configuration command. If the
39 * bus is on the 80321 then a type0 made, else a type1 is created.
41 static u32 iop321_cfg_address(struct pci_bus *bus, int devfn, int where)
43 struct pci_sys_data *sys = bus->sysdata;
46 if (sys->busnr == bus->number)
47 addr = 1 << (PCI_SLOT(devfn) + 16);
49 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
51 addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
57 * This routine checks the status of the last configuration cycle. If an error
58 * was detected it returns a 1, else it returns a 0. The errors being checked
59 * are parity, master abort, target abort (master and target). These types of
60 * errors occure during a config cycle where there is no device, like during
61 * the discovery stage.
63 static int iop321_pci_status(void)
69 * Check the status registers.
71 status = *IOP321_ATUSR;
74 DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
75 *IOP321_ATUSR = status & 0xf900;
78 status = *IOP321_ATUISR;
81 DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
82 *IOP321_ATUISR = status & 0x679f;
89 * Simply write the address register and read the configuration
90 * data. Note that the 4 nop's ensure that we are able to handle
91 * a delayed abort (in theory.)
93 static inline u32 iop321_read(unsigned long addr)
105 : "r" (addr), "r" (IOP321_OCCAR), "r" (IOP321_OCCDR));
111 * The read routines must check the error status of the last configuration
112 * cycle. If there was an error, the routine returns all hex f's.
115 iop321_read_config(struct pci_bus *bus, unsigned int devfn, int where,
116 int size, u32 *value)
118 unsigned long addr = iop321_cfg_address(bus, devfn, where);
119 u32 val = iop321_read(addr) >> ((where & 3) * 8);
121 if( iop321_pci_status() )
126 return PCIBIOS_SUCCESSFUL;
130 iop321_write_config(struct pci_bus *bus, unsigned int devfn, int where,
133 unsigned long addr = iop321_cfg_address(bus, devfn, where);
137 val = iop321_read(addr);
138 if (!iop321_pci_status() == 0)
139 return PCIBIOS_SUCCESSFUL;
141 where = (where & 3) * 8;
144 val &= ~(0xff << where);
146 val &= ~(0xffff << where);
148 *IOP321_OCCDR = val | value << where;
158 : "r" (value), "r" (addr),
159 "r" (IOP321_OCCAR), "r" (IOP321_OCCDR));
163 static struct pci_ops iop321_ops = {
164 .read = iop321_read_config,
165 .write = iop321_write_config,
169 * When a PCI device does not exist during config cycles, the 80200 gets a
170 * bus error instead of returning 0xffffffff. This handler simply returns.
173 iop321_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
175 DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
176 addr, fsr, regs->ARM_pc, regs->ARM_lr);
179 * If it was an imprecise abort, then we need to correct the
180 * return address to be _after_ the instruction.
189 * Scan an IOP321 PCI bus. sys->bus defines which bus we scan.
191 struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *sys)
193 return pci_scan_bus(sys->busnr, &iop321_ops, sys);
197 * Setup the system data for controller 'nr'. Return 0 if none found,
198 * 1 if found, or negative error.
200 int iop321_setup(int nr, struct pci_sys_data *sys)
202 struct resource *res;
207 res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL);
209 panic("PCI: unable to alloc resources");
211 memset(res, 0, sizeof(struct resource) * 2);
215 res[0].start = IOP321_PCI_IO_BASE + 0x6e000000;
216 res[0].end = IOP321_PCI_IO_BASE + IOP321_PCI_IO_SIZE-1 + 0x6e000000;
217 res[0].name = "PCI IO Primary";
218 res[0].flags = IORESOURCE_IO;
220 res[1].start = IOP321_PCI_MEM_BASE;
221 res[1].end = IOP321_PCI_MEM_BASE + IOP321_PCI_MEM_SIZE;
222 res[1].name = "PCI Memory Primary";
223 res[1].flags = IORESOURCE_MEM;
227 request_resource(&ioport_resource, &res[0]);
228 request_resource(&iomem_resource, &res[1]);
230 sys->resource[0] = &res[0];
231 sys->resource[1] = &res[1];
232 sys->resource[2] = NULL;
233 sys->io_offset = 0x6e000000;
241 void iop321_init(void)
243 DBG("PCI: Intel 80321 PCI init code.\n");
244 DBG("\tATU: IOP321_ATUCMD=0x%04x\n", *IOP321_ATUCMD);
245 DBG("\tATU: IOP321_OMWTVR0=0x%04x, IOP321_OIOWTVR=0x%04x\n",
248 DBG("\tATU: IOP321_ATUCR=0x%08x\n", *IOP321_ATUCR);
249 DBG("\tATU: IOP321_IABAR0=0x%08x IOP321_IALR0=0x%08x IOP321_IATVR0=%08x\n", *IOP321_IABAR0, *IOP321_IALR0, *IOP321_IATVR0);
250 DBG("\tATU: IOP321_ERBAR=0x%08x IOP321_ERLR=0x%08x IOP321_ERTVR=%08x\n", *IOP321_ERBAR, *IOP321_ERLR, *IOP321_ERTVR);
251 DBG("\tATU: IOP321_IABAR2=0x%08x IOP321_IALR2=0x%08x IOP321_IATVR2=%08x\n", *IOP321_IABAR2, *IOP321_IALR2, *IOP321_IATVR2);
252 DBG("\tATU: IOP321_IABAR3=0x%08x IOP321_IALR3=0x%08x IOP321_IATVR3=%08x\n", *IOP321_IABAR3, *IOP321_IALR3, *IOP321_IATVR3);
254 hook_fault_code(16+6, iop321_pci_abort, SIGBUS, "imprecise external abort");