2 * arch/arm/mach-ixp2000/common.c
4 * Common routines used by all IXP2400/2800 based platforms.
6 * Author: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2004 (C) MontaVista Software, Inc.
10 * Based on work Copyright (C) 2002-2003 Intel Corporation
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
17 #include <linux/config.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/spinlock.h>
21 #include <linux/sched.h>
22 #include <linux/interrupt.h>
23 #include <linux/serial.h>
24 #include <linux/tty.h>
25 #include <linux/bitops.h>
26 #include <linux/serial_core.h>
29 #include <asm/types.h>
30 #include <asm/setup.h>
31 #include <asm/memory.h>
32 #include <asm/hardware.h>
33 #include <asm/mach-types.h>
35 #include <asm/system.h>
36 #include <asm/hardware.h>
37 #include <asm/tlbflush.h>
38 #include <asm/pgtable.h>
39 #include <asm/mach-types.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach/time.h>
43 #include <asm/mach/irq.h>
45 static spinlock_t ixp2000_slowport_lock = SPIN_LOCK_UNLOCKED;
46 static unsigned long ixp2000_slowport_irq_flags;
48 /*************************************************************************
49 * Slowport access routines
50 *************************************************************************/
51 void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
54 spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
56 old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
57 old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
58 old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
59 old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
60 old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
62 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
63 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
64 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
65 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
66 ixp2000_reg_write(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
69 void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
71 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
72 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
73 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
74 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
75 ixp2000_reg_write(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
77 spin_unlock_irqrestore(&ixp2000_slowport_lock,
78 ixp2000_slowport_irq_flags);
81 /*************************************************************************
82 * Chip specific mappings shared by all IXP2000 systems
83 *************************************************************************/
84 static struct map_desc ixp2000_small_io_desc[] __initdata = {
86 .virtual = IXP2000_GLOBAL_REG_VIRT_BASE,
87 .physical = IXP2000_GLOBAL_REG_PHYS_BASE,
88 .length = IXP2000_GLOBAL_REG_SIZE,
91 .virtual = IXP2000_GPIO_VIRT_BASE,
92 .physical = IXP2000_GPIO_PHYS_BASE,
93 .length = IXP2000_GPIO_SIZE,
96 .virtual = IXP2000_TIMER_VIRT_BASE,
97 .physical = IXP2000_TIMER_PHYS_BASE,
98 .length = IXP2000_TIMER_SIZE,
101 .virtual = IXP2000_UART_VIRT_BASE,
102 .physical = IXP2000_UART_PHYS_BASE,
103 .length = IXP2000_UART_SIZE,
106 .virtual = IXP2000_SLOWPORT_CSR_VIRT_BASE,
107 .physical = IXP2000_SLOWPORT_CSR_PHYS_BASE,
108 .length = IXP2000_SLOWPORT_CSR_SIZE,
111 .virtual = IXP2000_INTCTL_VIRT_BASE,
112 .physical = IXP2000_INTCTL_PHYS_BASE,
113 .length = IXP2000_INTCTL_SIZE,
116 .virtual = IXP2000_PCI_CREG_VIRT_BASE,
117 .physical = IXP2000_PCI_CREG_PHYS_BASE,
118 .length = IXP2000_PCI_CREG_SIZE,
123 static struct map_desc ixp2000_large_io_desc[] __initdata = {
125 .virtual = IXP2000_PCI_CSR_VIRT_BASE,
126 .physical = IXP2000_PCI_CSR_PHYS_BASE,
127 .length = IXP2000_PCI_CSR_SIZE,
130 .virtual = IXP2000_PCI_IO_VIRT_BASE,
131 .physical = IXP2000_PCI_IO_PHYS_BASE,
132 .length = IXP2000_PCI_IO_SIZE,
135 .virtual = IXP2000_PCI_CFG0_VIRT_BASE,
136 .physical = IXP2000_PCI_CFG0_PHYS_BASE,
137 .length = IXP2000_PCI_CFG0_SIZE,
140 .virtual = IXP2000_PCI_CFG1_VIRT_BASE,
141 .physical = IXP2000_PCI_CFG1_PHYS_BASE,
142 .length = IXP2000_PCI_CFG1_SIZE,
147 static struct uart_port ixp2000_serial_port = {
148 .membase = (char *)(IXP2000_UART_VIRT_BASE + 3),
149 .mapbase = IXP2000_UART_PHYS_BASE + 3,
150 .irq = IRQ_IXP2000_UART,
151 .flags = UPF_SKIP_TEST,
160 void __init ixp2000_map_io(void)
162 iotable_init(ixp2000_small_io_desc, ARRAY_SIZE(ixp2000_small_io_desc));
163 iotable_init(ixp2000_large_io_desc, ARRAY_SIZE(ixp2000_large_io_desc));
164 early_serial_setup(&ixp2000_serial_port);
167 /*************************************************************************
168 * Timer-tick functions for IXP2000
169 *************************************************************************/
170 static unsigned ticks_per_jiffy;
171 static unsigned ticks_per_usec;
173 static unsigned long ixp2000_gettimeoffset (void)
175 unsigned long elapsed;
177 /* Get ticks since last perfect jiffy */
178 elapsed = ticks_per_jiffy - *IXP2000_T1_CSR;
180 return elapsed / ticks_per_usec;
183 static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
186 ixp2000_reg_write(IXP2000_T1_CLR, 1);
193 static struct irqaction ixp2000_timer_irq = {
194 .name = "IXP2000 Timer Tick",
195 .flags = SA_INTERRUPT,
196 .handler = ixp2000_timer_interrupt
199 void __init ixp2000_init_time(unsigned long tick_rate)
201 gettimeoffset = ixp2000_gettimeoffset;
203 ixp2000_reg_write(IXP2000_T1_CLR, 0);
204 ixp2000_reg_write(IXP2000_T2_CLR, 0);
206 ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
207 ticks_per_usec = tick_rate / 1000000;
209 ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy);
210 ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
212 /* register for interrupt */
213 setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
216 /*************************************************************************
218 *************************************************************************/
219 static unsigned long GPIO_IRQ_rising_edge;
220 static unsigned long GPIO_IRQ_falling_edge;
221 static unsigned long GPIO_IRQ_level_low;
222 static unsigned long GPIO_IRQ_level_high;
224 void gpio_line_config(int line, int style)
228 local_irq_save(flags);
230 if(style == GPIO_OUT) {
231 /* if it's an output, it ain't an interrupt anymore */
232 ixp2000_reg_write(IXP2000_GPIO_PDSR, (1 << line));
233 GPIO_IRQ_falling_edge &= ~(1 << line);
234 GPIO_IRQ_rising_edge &= ~(1 << line);
235 GPIO_IRQ_level_low &= ~(1 << line);
236 GPIO_IRQ_level_high &= ~(1 << line);
237 ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
238 ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
239 ixp2000_reg_write(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
240 ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
241 irq_desc[line+IRQ_IXP2000_GPIO0].valid = 0;
242 } else if(style == GPIO_IN) {
243 ixp2000_reg_write(IXP2000_GPIO_PDCR, (1 << line));
246 local_irq_restore(flags);
250 /*************************************************************************
251 * IRQ handling IXP2000
252 *************************************************************************/
253 static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
256 unsigned long status = *IXP2000_GPIO_INST;
258 for (i = 0; i <= 7; i++) {
259 if (status & (1<<i)) {
260 desc = irq_desc + i + IRQ_IXP2000_GPIO0;
261 desc->handle(i + IRQ_IXP2000_GPIO0, desc, regs);
266 static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
268 ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
269 ixp2000_reg_write(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
272 static void ixp2000_GPIO_irq_mask(unsigned int irq)
274 ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
277 static void ixp2000_GPIO_irq_unmask(unsigned int irq)
279 ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
282 static struct irqchip ixp2000_GPIO_irq_chip = {
283 .ack = ixp2000_GPIO_irq_mask_ack,
284 .mask = ixp2000_GPIO_irq_mask,
285 .unmask = ixp2000_GPIO_irq_unmask
288 static void ixp2000_pci_irq_mask(unsigned int irq)
290 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
291 if (irq == IRQ_IXP2000_PCIA)
292 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
293 else if (irq == IRQ_IXP2000_PCIB)
294 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
297 static void ixp2000_pci_irq_unmask(unsigned int irq)
299 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
300 if (irq == IRQ_IXP2000_PCIA)
301 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
302 else if (irq == IRQ_IXP2000_PCIB)
303 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
306 static struct irqchip ixp2000_pci_irq_chip = {
307 .ack = ixp2000_pci_irq_mask,
308 .mask = ixp2000_pci_irq_mask,
309 .unmask = ixp2000_pci_irq_unmask
313 * Error interrupts. These are used extensively by the microengine drivers
315 static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
318 unsigned long status = *IXP2000_IRQ_ERR_STATUS;
321 for (i = 0; i <= 12; i++) {
322 if (status & (1 << i)) {
323 desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
324 desc->handle(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc, regs);
329 static void ixp2000_err_irq_mask(unsigned int irq)
331 ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
332 (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
335 static void ixp2000_err_irq_unmask(unsigned int irq)
337 ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
338 (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
341 static struct irqchip ixp2000_err_irq_chip = {
342 .ack = ixp2000_err_irq_mask,
343 .mask = ixp2000_err_irq_mask,
344 .unmask = ixp2000_err_irq_unmask
347 static void ixp2000_irq_mask(unsigned int irq)
349 ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
352 static void ixp2000_irq_unmask(unsigned int irq)
354 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
357 static struct irqchip ixp2000_irq_chip = {
358 .ack = ixp2000_irq_mask,
359 .mask = ixp2000_irq_mask,
360 .unmask = ixp2000_irq_unmask
363 void __init ixp2000_init_irq(void)
370 ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
371 ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
373 /* clear all GPIO edge/level detects */
374 ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
375 ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
376 ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
377 ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
378 ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
380 /* clear PCI interrupt sources */
381 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
384 * Certain bits in the IRQ status register of the
385 * IXP2000 are reserved. Instead of trying to map
386 * things non 1:1 from bit position to IRQ number,
387 * we mark the reserved IRQs as invalid. This makes
388 * our mask/unmask code much simpler.
390 for (irq = IRQ_IXP2000_SWI; irq <= IRQ_IXP2000_THDB3; irq++) {
391 if((1 << irq) & IXP2000_VALID_IRQ_MASK) {
392 set_irq_chip(irq, &ixp2000_irq_chip);
393 set_irq_handler(irq, do_level_IRQ);
394 set_irq_flags(irq, IRQF_VALID);
395 } else set_irq_flags(irq, 0);
399 * GPIO IRQs are invalid until someone sets the interrupt mode
400 * by calling gpio_line_set();
402 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
403 set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
404 set_irq_handler(irq, do_level_IRQ);
405 set_irq_flags(irq, 0);
407 set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
412 *(IXP2000_IRQ_ENABLE_SET) = (1 << IRQ_IXP2000_PCI);
413 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
414 set_irq_chip(irq, &ixp2000_pci_irq_chip);
415 set_irq_handler(irq, do_level_IRQ);
416 set_irq_flags(irq, IRQF_VALID);
419 for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
420 set_irq_chip(irq, &ixp2000_err_irq_chip);
421 set_irq_handler(irq, do_level_IRQ);
422 set_irq_flags(irq, IRQF_VALID);
424 set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);