3 config ARCH_SUPPORTS_BIG_ENDIAN
7 menu "Intel IXP4xx Implementation Options"
9 comment "IXP4xx Platforms"
14 Say 'Y' here if you want your kernel to support the Gateworks
15 Avila Network Platform. For more information on this platform,
16 see Documentation/arm/IXP4xx.
18 config ARCH_ADI_COYOTE
21 Say 'Y' here if you want your kernel to support the ADI
22 Engineering Coyote Gateway Reference Platform. For more
23 information on this platform, see Documentation/arm/IXP4xx.
28 Say 'Y' here if you want your kernel to support Intel's
29 IXDP425 Development Platform (Also known as Richfield).
30 For more information on this platform, see Documentation/arm/IXP4xx.
35 Say 'Y' here if you want your kernel to support Intel's
36 IXDPG425 Development Platform (Also known as Montajade).
37 For more information on this platform, see Documentation/arm/IXP4xx.
40 # IXCDP1100 is the exact same HW as IXDP425, but with a different machine
41 # number from the bootloader due to marketing monkeys, so we just enable it
42 # by default if IXDP425 is enabled.
46 depends on ARCH_IXDP425
52 Say 'Y' here if you want your kernel to support the Motorola
53 PrPCM1100 Processor Mezanine Module. For more information on
54 this platform, see Documentation/arm/IXP4xx.
57 # Avila and IXDP share the same source for now. Will change in future
61 depends on ARCH_IXDP425 || ARCH_AVILA
64 comment "IXP4xx Options"
66 config IXP4XX_INDIRECT_PCI
67 bool "Use indirect PCI memory access"
69 IXP4xx provides two methods of accessing PCI memory space:
71 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
72 To access PCI via this space, we simply ioremap() the BAR
73 into the kernel and we can use the standard read[bwl]/write[bwl]
74 macros. This is the preffered method due to speed but it
75 limits the system to just 64MB of PCI memory. This can be
76 problamatic if using video cards and other memory-heavy devices.
78 2) If > 64MB of memory space is required, the IXP4xx can be
79 configured to use indirect registers to access PCI This allows
80 for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus.
81 The disadvantadge of this is that every PCI access requires
82 three local register accesses plus a spinlock, but in some
83 cases the performance hit is acceptable. In addition, you cannot
84 mmap() PCI devices in this case due to the indirect nature
87 By default, the direct method is used. Choose this option if you
88 need to use the indirect method instead. If you don't know
89 what you need, leave this option unselected.