2 * arch/arm/mach-ixp4xx/common.c
4 * Generic code shared across all IXP4XX platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/serial.h>
21 #include <linux/sched.h>
22 #include <linux/tty.h>
23 #include <linux/serial_core.h>
24 #include <linux/bootmem.h>
25 #include <linux/interrupt.h>
26 #include <linux/bitops.h>
27 #include <linux/time.h>
28 #include <linux/timex.h>
30 #include <asm/hardware.h>
31 #include <asm/uaccess.h>
33 #include <asm/pgtable.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/irq.h>
39 #include <asm/mach/time.h>
42 /*************************************************************************
43 * GPIO acces functions
44 *************************************************************************/
47 * Configure GPIO line for input, interrupt, or output operation
49 * TODO: Enable/disable the irq_desc based on interrupt or output mode.
50 * TODO: Should these be named ixp4xx_gpio_?
52 void gpio_line_config(u8 line, u32 style)
55 volatile u32 *int_reg;
58 enable = *IXP4XX_GPIO_GPOER;
60 if (style & IXP4XX_GPIO_OUT) {
61 enable &= ~((1) << line);
62 } else if (style & IXP4XX_GPIO_IN) {
63 enable |= ((1) << line);
65 switch (style & IXP4XX_GPIO_INTSTYLE_MASK)
67 case (IXP4XX_GPIO_ACTIVE_HIGH):
68 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
70 case (IXP4XX_GPIO_ACTIVE_LOW):
71 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
73 case (IXP4XX_GPIO_RISING_EDGE):
74 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
76 case (IXP4XX_GPIO_FALLING_EDGE):
77 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
79 case (IXP4XX_GPIO_TRANSITIONAL):
80 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
83 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
87 if (line >= 8) { /* pins 8-15 */
89 int_reg = IXP4XX_GPIO_GPIT2R;
92 int_reg = IXP4XX_GPIO_GPIT1R;
95 /* Clear the style for the appropriate pin */
96 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
97 (line * IXP4XX_GPIO_STYLE_SIZE));
99 /* Set the new style */
100 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
103 *IXP4XX_GPIO_GPOER = enable;
106 EXPORT_SYMBOL(gpio_line_config);
108 /*************************************************************************
109 * IXP4xx chipset I/O mapping
110 *************************************************************************/
111 static struct map_desc ixp4xx_io_desc[] __initdata = {
112 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
113 .virtual = IXP4XX_PERIPHERAL_BASE_VIRT,
114 .physical = IXP4XX_PERIPHERAL_BASE_PHYS,
115 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
117 }, { /* Expansion Bus Config Registers */
118 .virtual = IXP4XX_EXP_CFG_BASE_VIRT,
119 .physical = IXP4XX_EXP_CFG_BASE_PHYS,
120 .length = IXP4XX_EXP_CFG_REGION_SIZE,
122 }, { /* PCI Registers */
123 .virtual = IXP4XX_PCI_CFG_BASE_VIRT,
124 .physical = IXP4XX_PCI_CFG_BASE_PHYS,
125 .length = IXP4XX_PCI_CFG_REGION_SIZE,
130 void __init ixp4xx_map_io(void)
132 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
136 /*************************************************************************
137 * IXP4xx chipset IRQ handling
139 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
140 * (be it PCI or something else) configures that GPIO line
141 * as an IRQ. Also, we should use a different chip structure for
142 * level-based GPIO vs edge-based GPIO. Currently nobody needs this as
143 * all HW that's publically available uses level IRQs, so we'll
144 * worry about it if/when we have HW to test.
145 **************************************************************************/
146 static void ixp4xx_irq_mask(unsigned int irq)
148 if (cpu_is_ixp46x() && irq >= 32)
149 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
151 *IXP4XX_ICMR &= ~(1 << irq);
154 static void ixp4xx_irq_mask_ack(unsigned int irq)
156 ixp4xx_irq_mask(irq);
159 static void ixp4xx_irq_unmask(unsigned int irq)
161 static int irq2gpio[32] = {
162 -1, -1, -1, -1, -1, -1, 0, 1,
163 -1, -1, -1, -1, -1, -1, -1, -1,
164 -1, -1, -1, 2, 3, 4, 5, 6,
165 7, 8, 9, 10, 11, 12, -1, -1,
167 int line = (irq < 32) ? irq2gpio[irq] : -1;
170 * This only works for LEVEL gpio IRQs as per the IXP4xx developer's
171 * manual. If edge-triggered, need to move it to the mask_ack.
172 * Nobody seems to be using the edge-triggered mode on the GPIOs.
175 gpio_line_isr_clear(line);
177 if (cpu_is_ixp46x() && irq >= 32)
178 *IXP4XX_ICMR2 |= (1 << (irq - 32));
180 *IXP4XX_ICMR |= (1 << irq);
183 static struct irqchip ixp4xx_irq_chip = {
184 .ack = ixp4xx_irq_mask_ack,
185 .mask = ixp4xx_irq_mask,
186 .unmask = ixp4xx_irq_unmask,
189 void __init ixp4xx_init_irq(void)
193 /* Route all sources to IRQ instead of FIQ */
196 /* Disable all interrupt */
199 if (cpu_is_ixp46x()) {
200 /* Route upper 32 sources to IRQ instead of FIQ */
201 *IXP4XX_ICLR2 = 0x00;
203 /* Disable upper 32 interrupts */
204 *IXP4XX_ICMR2 = 0x00;
207 for(i = 0; i < NR_IRQS; i++)
209 set_irq_chip(i, &ixp4xx_irq_chip);
210 set_irq_handler(i, do_level_IRQ);
211 set_irq_flags(i, IRQF_VALID);
216 /*************************************************************************
218 * We use OS timer1 on the CPU for the timer tick and the timestamp
219 * counter as a source of real clock ticks to account for missed jiffies.
220 *************************************************************************/
222 static unsigned volatile last_jiffy_time;
224 #define CLOCK_TICKS_PER_USEC ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
226 /* IRQs are disabled before entering here from do_gettimeofday() */
227 static unsigned long ixp4xx_gettimeoffset(void)
231 elapsed = *IXP4XX_OSTS - last_jiffy_time;
233 return elapsed / CLOCK_TICKS_PER_USEC;
236 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
238 write_seqlock(&xtime_lock);
240 /* Clear Pending Interrupt by writing '1' to it */
241 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
244 * Catch up with the real idea of time
246 while ((*IXP4XX_OSTS - last_jiffy_time) > LATCH) {
248 last_jiffy_time += LATCH;
251 write_sequnlock(&xtime_lock);
256 static struct irqaction ixp4xx_timer_irq = {
257 .name = "IXP4xx Timer Tick",
258 .flags = SA_INTERRUPT,
259 .handler = ixp4xx_timer_interrupt
262 static void __init ixp4xx_timer_init(void)
264 /* Clear Pending Interrupt by writing '1' to it */
265 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
267 /* Setup the Timer counter value */
268 *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
270 /* Reset time-stamp counter */
274 /* Connect the interrupt handler and enable the interrupt */
275 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
278 struct sys_timer ixp4xx_timer = {
279 .init = ixp4xx_timer_init,
280 .offset = ixp4xx_gettimeoffset,
283 static struct resource ixp46x_i2c_resources[] = {
287 .flags = IORESOURCE_MEM,
290 .start = IRQ_IXP4XX_I2C,
291 .end = IRQ_IXP4XX_I2C,
292 .flags = IORESOURCE_IRQ
297 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
298 * we just use the same device name.
300 static struct platform_device ixp46x_i2c_controller = {
301 .name = "IOP3xx-I2C",
304 .resource = ixp46x_i2c_resources
307 static struct platform_device *ixp46x_devices[] __initdata = {
308 &ixp46x_i2c_controller
311 void __init ixp4xx_sys_init(void)
313 if (cpu_is_ixp46x()) {
314 platform_add_devices(ixp46x_devices,
315 ARRAY_SIZE(ixp46x_devices));